840002AGI-01LFT [IDT]
FemtoClock, Crystal-to-LVCMOS/LVTTL Frequency Synthesizer;
| 型号： | 840002AGI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock, Crystal-to-LVCMOS/LVTTL Frequency Synthesizer 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock®, Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
840002I-01
DATA SHEET
General Description
Features
The 840002I-01 is a two output LVCMOS/LVTTL Synthesizer
optimized to generate Ethernet reference clock frequencies. Using a
25MHz 18pF parallel resonant crystal, the following frequencies can
be generated based on the two frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz, and 62.5MHz. The 840002I-01 uses IDT’s 3RD
generation low phase noise VCO technology and can achieve 1ps or
lower typical random rms phase jitter, easily meeting Ethernet jitter
requirements. The 840002I-01 is packaged in a small 16-pin TSSOP
package.
• Two LVCMOS/LVTTL outputs@ 3.3V,
17 typical output impedance
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended TEST_CLK
• Supports the following output frequencies: 156.25MHz, 125MHz
and 62.5MHz
• Output frequency range: 56MHz to 175MHz
• VCO range: 560MHz to 700MHz
• Output skew: 12ps (maximum)
• RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz):
0.47ps (typical)
Phase Noise:
Offset
Noise Power
100Hz................ -97.4 dBc/Hz
1kHz .................. -120.2 dBc/Hz
10kHz ................ -127.6 dBc/Hz
100kHz .............. -126.1 dBc/Hz
Frequency Select Function Table
Inputs
Output
M Divider N Divider
Frequency
(25MHz Ref.)
• Power Supply Modes:
Core / Output
3.3V / 3.3V
F_SEL1
F_SEL0
Value
Value
0
0
1
1
0
1
0
1
25
4
5
156.25
125
3.3V / 2.5V
2.5V / 2.5V
25
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
25
10
5
62.5
125
25
Pin Assignment
Block Diagram
F_SEL1
F_SEL0
nXTAL_SEL
TEST_CLK
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
Pullup
OE
GND
GND
Q0
2
Pullup:Pullup
F_SEL1:0
Pulldown
nPLL_SEL
MR
nPLL_SEL
VDDA
Q1
VDDO
10 XTAL_IN
XTAL_OUT
Pulldown
nXTAL_SEL
9
VDD
XTAL_IN
F_SEL1:0
N
0
Q0
Q1
OSC
840002I-01
1
0
XTAL_OUT
TEST_CLK
0 0
4
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
0 1
5
Phase
Detector
Pulldown
1
VCO
1 0 10
1 1
5
G Package
Top View
M = 25 (fixed)
Pulldown
MR
840002I-01 Rev B 8/5/15
1
©2015 Integrated Device Technology, Inc.
840002I-01 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
1
F_SEL0
Input
Input
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
2
nXTAL_SEL
Pulldown
3
4
TEST_CLK
OE
Input
Input
Pulldown
Pullup
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Output enable. When logic HIGH, the outputs are active. When LOW, the
outputs are in high-impedance state. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the active outputs to go low. When Logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
5
6
MR
Input
Input
Pulldown
Pulldown
PLL Bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
nPLL_SEL
7
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
9,
10
XTAL_OUT
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Input
11
VDDO
Power
Output
Power
Input
Output supply pin.
12, 13
14, 15
16
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Q1, Q0
GND
F_SEL1
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
4
CPD
Power Dissipation Capacitance
Input Pullup Resistor
8
pF
RPULLUP
51
51
17
21
k
k
RPULLDOWN Input Pulldown Resistor
VDDO = 3.3V 5%
VDDO = 2.5V 5%
14
16
21
25
ROUT Output Impedance
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
2
Rev B 8/5/15
840002I-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
0V to VDD
Other Inputs
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
89C/W (0 lfpm)
-65C to 150C
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
3.465
2.625
100
Units
V
Core Supply Voltage
Analog Supply Voltage
VDDA
3.135
3.3
V
3.135
3.3
V
VDDO
Output Supply Voltage
2.375
2.5
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
12
5
Table 3B. Power Supply DC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
2.625
95
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDDA
VDDO
IDD
2.375
2.5
V
2.375
2.5
V
mA
mA
mA
IDDA
12
IDDO
5
Rev B 8/5/15
3
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V 5% or 2.5V 5%ꢀ or
VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.3V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
V
2
VIH
VIL
Input High Voltage
VDD = 2.5V
VDD = 3.3V
1.7
-0.3
-0.3
V
V
Input Low Voltage
VDD = 2.5V
0.7
V
OE, F_SEL0, F_SEL1
V
DD = VIN = 3.465V or 2.625V
5
µA
Input
High Current
IIH
MR, TEST_CLK,
nXTAL_SEL, nPLL_SEL
VDD = VIN =3.465V or 2.625V
150
µA
µA
µA
VDD = 3.465V or 2.625V,
OE, F_SEL0, F_SEL1
-150
-5
V
IN = 0V
Input
Low Current
IIL
MR, TEST_CLK,
nXTAL_SEL, nPLL_SEL
VDD = 3.465V or 2.625V,
IN = 0V
V
VDDO = 3.3V 5%
VDDO = 2.5V 5%
2.6
1.8
V
V
V
VOH
VOL
Output High Voltageꢀ NOTE 1
Output Low Voltageꢀ NOTE 1
VDDO = 3.3V 5% or 2.5V 5%
0.5
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section, Output Load Test Circuit diagrams.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
4
Rev B 8/5/15
840002I-01 DATA SHEET
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum
140
Typical
Maximum
175
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
112
140
56
70
tsk(o)
tjit(Ø)
Output Skewꢀ NOTE 1, 2
RMS Phase Jitter, Randomꢀ NOTE 3
12
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.47
0.57
0.51
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum
140
Typical
Maximum
175
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
112
140
56
70
tsk(o)
tjit(Ø)
Output Skewꢀ NOTE 1, 2
RMS Phase Jitter, Randomꢀ NOTE 3
12
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.47
0.55
0.49
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
For NOTES, see Table 5A above.
Table 5C. AC Characteristics, VDD = VDDA = VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
Minimum
140
Typical
Maximum
175
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
112
140
56
70
tsk(o)
tjit(Ø)
Output Skewꢀ NOTE 1, 2
RMS Phase Jitter, Randomꢀ NOTE 3
12
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
0.49
0.56
0.52
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
46
700
54
ps
%
fOUT = 125MHz
47
53
%
For NOTES, see Table 5A above.
Rev B 8/5/15
5
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Typical Phase Noise at 62.5MHz (3.3V)
1Gb Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
1Gb Ethernet filter to raw data
Offset Frequency (Hz)
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
6
Rev B 8/5/15
840002I-01 DATA SHEET
Typical Phase Noise at 156.25MHz (3.3V)
10Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
Offset Frequency (Hz)
Rev B 8/5/15
7
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Parameter Measurement Information
1.65V 5%
2.05V 5%
1.25V 5%
SCOPE
SCOPE
VDD,
VDD,
VDDA,
VDDA
VDDO
Qx
VDDO
GND
Qx
LVCMOS
GND
VDDO
2
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V Output Load AC Test Circuit
3.3V Core/2.5V Output Load AC Test Circuit
1.25V 5%
Phase Noise Plot
SCOPE
VDD,
VDDA,
Phase Noise Mask
VDDO
Qx
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V 5%
2.5V Core/2.5V Output Load AC Test Circuit
RMS Phase Jitter
VDDO
2
VDDO
Qx
Q[0:1]
2
tPW
tPERIOD
VDDO
Qy
2
tPW
tsk(o)
x 100%
odc =
tPERIOD
Output Skew
Output Duty Cycle/Pulse Width/Period
80%
80%
tR
20%
20%
Q[0:1]
tF
Output Rise/Fall Time
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
8
Rev B 8/5/15
840002I-01 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
LVCMOS Outputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldownsꢀ additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Rev B 8/5/15
9
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 1A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50
applications, R1 and R2 can be 100. This can also be
accomplished by removing R1 and making R2 50. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
10
Rev B 8/5/15
840002I-01 DATA SHEET
Layout Guideline
Figure 2 shows a schematic example of the 840002I-01 application
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
schematic. In this example, the device is operated at VDD = VDDA
=
VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The
load capacitance C1 = 22pF and C2 = 22pF are recommended for
frequency accuracy. Depending on the parasitic of the printed circuit
board layout, these values might require a slight adjustment to
optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will required adjusting
C1 and C2.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The 840002I-01 provides separate power
supplies to isolate from coupling into the internal PLL.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
Figure 2. 840002I-01 Application Schematic Example
Rev B 8/5/15
11
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Reliability Information
Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP
JA by Velocity
0
Linear Feet per Minute
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
Transistor Count
The transistor count for 840002I-01 is: 3356
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
12
Rev B 8/5/15
840002I-01 DATA SHEET
Ordering Information
Table 8. Ordering Information
Part/Order Number
840002AGI-01LF
840002AGI-01LFT
Marking
002AI01L
002AI01L
Package
“Lead-Free”, 16 Lead LQFP
“Lead-Free”, 16 Lead LQFP
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Rev B 8/5/15
13
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002I-01 DATA SHEET
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T8
12
Ordering Information Table - corrected standard marking and added Lead-Free part
number, marking and note.
A
10/18/07
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
A
T8
12
14
11/18/10
12/6/10
T5A - T5C
4 - 5
8
AC Characteristics Tables - added thermal note.
Power Supply Filtering Techniques - corrected figure 1.
Added Overdriving the Crystal Interface section.
9
10
Added Recommendations for Unused Input & Output Pins section.
T5B
T5C
5
3.3V/2.5V AC Characteristics Table -corrected FOUT from 56MHz min - 68MHz max to
56MHz min - 70MHz max.
5
2.5V AC Characteristics Table - added 2nd odc spec and added thermal note.
Corrected FOUT from 56MHz min - 68MHz max to 56MHz min - 70MHz max.
8
8
Deleted Power Supply Filtering Techniques section, added to schematic layout.
Deleted Crystal Input Interface section.
B
2/3/11
9
Added Overdriving the XTAL Interface section.
Updated Layout Guideline and diagram.
10
Converted datasheet format.
B
B
5A, 5B, 5C
5
AC Tableꢀ fOUT = F_SEL[1:0] = 01 or 11, F_SEL[1:0] = 10
Deleted Quantity from Tape and Reel
9/28/12
8/5/15
8
13
13
T8
Ordering Information - removed leaded devices.
Updated data sheet format.
B
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
14
Rev B 8/5/15
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San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
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this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
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Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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