8430252-45T [IDT]
Clock Generator;
| 型号： | 8430252-45T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总13页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430252-45 is a 2 output LVPECL and
• One differential 3.3V LVPECL output and
One LVCMOS/LVTTL output
ICS
LVCMOS/LVTTL Synthesizer optimized to gen-
erate Ethernet reference clock frequencies and
is a member of the HiPerClocks™family of high
performance clock solutions from ICS. Using a
HiPerClockS™
• Crystal oscillator interface designed for a 25MHz,
18pF parallel resonant crystal
25MHz, 18pF parallel resonant crystal, the following fre-
quencies can be generated: 156.25MHz LVPECL output
and, 125MHz LVCMOS output. The 8430252-45 uses ICS’
3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meet-
ing Ethernet jitter requirements. The ICS8430252-45 is
packaged in a small 16-pin TSSOP package.
• A 25MHz crystal generates both an output frequency of
156.25MHz (LVPECL) and 125MHz (LVCMOS)
• VCO frequency: 625MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using
a 25MHz crystal: 0.39ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
2
3
4
5
6
7
8
OE
VEE
QA
16
15
14
13
12
11
10
9
CLK_EN
VEE
QB
25MHz
QA
÷5
÷4
XTAL_IN
Phase
Detector
VCO
OSC
VCCO_A
nc
nc
VCCA
VCC
nQB
625MHz
VCCO_B
XTAL_IN
XTAL_OUT
VEE
QB
XTAL_OUT
nQB
Feedback Divider
÷25
Pullup
CLK_EN
ICS8430252-45
16-LeadTSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430252CG-45
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REV.B DECEMBER 9, 2005
1
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
Output enable pin. LVCMOS/LVTTL interface levels.
See Table 3A Function Table.
1
OE
Input
2, 9, 15
VEE
QA
Power
Output
Power
Negative supply pin.
LVCMOS/LVTTL clock output.
Output supply pin for QA output.
No connect.
3
4
VCCO_A
nc
5, 6
7
Unused
Power
Power
VCCA
VCC
Analog supply pin.
8
Core supply pin.
XTAL_OUT,
XTAL_IN
10, 11
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
12
VCCO_B
Power
Output
Output supply pin for QB, nQB outputs.
13, 14
nQB, QB
Differential clock outputs. LVPECL interface levels.
Clock enable pin. LVCMOS/LVTTL interface levels.
See Table 3B Function Table.
16
CLK_EN
Input
Pullup
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
CPD
Power Dissipation Capacitance
Input Pullup Resistor
VCC, VCCA, VCCO_A, VCCO_B = 3.465V
10
51
RPULLUP
TABLE 3A. OE SELECT FUNCTION TABLE
Input
OE
0
Output
QA
Hi-Z
1
Active
TABLE 3B. CLK_EN SELECT FUNCTION TABLE
Input
Outputs
CLK_EN
QB
nQB
High
0
1
Low
Active
Active
8430252CG-45
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REV.B DECEMBER 9, 2005
2
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
89°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A.POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA = VCCO_A, VCCO_B = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
75
8
3.465
3.465
3.465
V
V
VCCA
V
CCO_A, VCCO_B Output Supply Voltage
V
IEE
ICCA
Power Supply Current
Analog Supply Current
mA
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE, CLK_EN
Input Low Current OE, CLK_EN
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VCC = VIN = 3.465V
IIL
VCC = 3.465V, VIN = 0V
-150
2.6
VOH
VOL
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCCO_A/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC =VCCA =VCCO_B = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_B - 2V.
8430252CG-45
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REV.B DECEMBER 9, 2005
3
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Fundamental
Frequency
25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
156.25
125
0.41
0.39
775
390
50
MHz
MHz
ps
fOUT
Output Frequency Range
QA
125MHz (1.875MHz - 20MHz)
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
tR / tF
odc
QB, nQB
QA
156.25MHz (1.875MHz - 20MHz)
ps
ps
Output
20ꢀ to 80ꢀ
Rise/Fall Time
QB, nQB
QA
ps
ꢀ
Output Duty Cycle
QB, nQB
50
ꢀ
NOTE 1: Please refer to the Phase Noise Plots.
8430252CG-45
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REV.B DECEMBER 9, 2005
4
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
10Gb Ethernet Filter
-30
-40
-50
-60
-70
-80
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.39ps (typical)
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filterto raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
8430252CG-45
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REV.B DECEMBER 9, 2005
5
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
1.65V 5ꢀ
SCOPE
VCC
,
Qx
SCOPE
VCC
,
VCCA, VCCO_B
VCCA, VCCO_A
LVPECL
Qx
LVCMOS
nQx
VEE
VEE
-1.3V 0.165V
-1.65V 5ꢀ
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VCCO_LVCMOS
2
QA
tPW
Phase Noise Mask
tPERIOD
tPW
odc =
x 100ꢀ
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB
QB
80ꢀ
tF
80ꢀ
tR
tPW
20ꢀ
tPERIOD
20ꢀ
Clock
Outputs
tPW
odc =
x 100ꢀ
tPERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
LVPECL OUTPUT RISE/FALL TIME
8430252CG-45
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REV.B DECEMBER 9, 2005
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PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS8430252-45 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, andVCCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8430252-45 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error.
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
8430252CG-45
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REV.B DECEMBER 9, 2005
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PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
SELECT PINS:
OUTPUTS:
LVCMOS OUTPUT:
All select pins have internal pull-ups and pull-downs; additional All unused LVCMOS output can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached.
protection. A 1kΩ resistor can be used.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
8430252CG-45
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REV.B DECEMBER 9, 2005
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PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430252-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 75mA = 259.88mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 90mW
Total Power_MAX (3.465V, with all outputs switching) = 259.9mW + 60mW = 319.9mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W perTable 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.320W * 81.8°C/W = 96.2°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8430252CG-45
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REV.B DECEMBER 9, 2005
9
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8430252CG-45
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REV.B DECEMBER 9, 2005
10
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430252-45 is: 2070
8430252CG-45
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REV.B DECEMBER 9, 2005
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PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8430252CG-45
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REV.B DECEMBER 9, 2005
12
PRELIMINARY
ICS8430252-45
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS8430252CG-45
Marking
30252C45
30252C45
TBD
Package
Shipping Packaging Temperature
16 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8430252CG-45T
ICS8430252CG-45LF
ICS8430252CG-45LFT
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
8430252CG-45
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REV.B DECEMBER 9, 2005
13
相关型号：
8430252CGI-45T
Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
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