843034AYLF [IDT]
Clock Generator, 750MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48;
| 型号： | 843034AYLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 750MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBC, LQFP-48 时钟 外围集成电路 晶体 |
| 文件： | 总24页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ MULTI-RATE 3.3V, 2.5V
LFPECL FREQUENCY SYNTHESIZER
ICS843034
GENERAL DESCRIPTION
FEATURES
The ICS843034 is a general purpose, low phase
• Dual differential 3.3V LVPECL outputs which can be set
ICS
noise LVPECL synthesizer which can generate
frequencies for a wide variety of applications. The
ICS843034 has a 4:1 input Multiplexer from which
the following inputs can be selected: 1 differential
input, 1 single-ended input, or two crystal
independently for either 3.3V or 2.5V
HiPerClockS™
• 4:1 Input Mux:
One differential input
One single-ended input
Two crystal oscillator interfaces
oscillators, thus making the device ideal for frequency
translation or frequency generation. Each differential LVPECL
output pair has an output divider which can be independently
set so that two different frequencies can be generated.
Additionally, each LVPECL output pair has a dedicated power
supply pin so the outputs can run at 3.3V or 2.5V. The
ICS843034-02 also supplies a buffered copy of the reference
clock or crystal frequency on the single-ended REF_CLK pin
which can be enabled or disabled (disabled by default). The
output frequency can be programmed using either a serial or
parallel programming interface.
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• TEST_CLK accepts LVCMOS or LVTTL input levels
• Output frequency range: 35MHz to 750MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 560MHz to 750MHz
• Parallel or serial interface for programming feedback divider
and output dividers
The phase jitter of the ICS843034 is less than 1ps rms, making
it suitable for use in Fibre Channel, SONET, and Ethernet
applications.
• RMS phase jitter at 333.33MHz, using a 22.222MHz crystal
(12kHz to 20MHz): 0.80ps (typical)
• Supply voltage modes:
Example applications include systems which must support both
FEC and non FEC rates. In 10Gb Fibre Channel, for example,
you can use a 25.5MHz crystal to generate a 159.375MHz
reference clock, and then switch to a 20.544MHz crystal to
generate 164.355MHz for 66/64 FEC. Other applications could
include supporting both Ethernet frequencies and SONET
frequencies in an application. When Ethernet frequencies are
needed, a 25MHz crystal can be used and when SONET
frequencies are needed, the input MUX can be switched to
select a 38.88MHz crystal.
LVPECL outputs (core/outputs):
3.3V/3.3V
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
• 0°C to 70°C ambient operating temperature
• Industrial temperature available upon request
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
XTAL_OUT1
M8
NB0
1
36
35
34
33
32
31
30
29
28
27
26
25
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
2
NB1
3
NB2
4
ICS843034
OE_REF
OE_A
OE_B
VCC
5
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
6
7
SEL0
VCCA
8
Y Package
S_LOAD
S_DATA
S_CLOCK
MR
NA0
9
Top View
NA1
10
11
12
NA2
VEE
13 14 15 16 17 18 19 20 21 22 23 24
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization.Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
1
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
BLOCK DIAGRAM
OE_A
000 1
001 2
010 3
011 4
5
VCO_SEL
XTAL_IN0
FOUTA0
nFOUTA0
OSC
OSC
XTAL_OUT0
XTAL_IN1
101 6
8
VCCO_A
1
111 16
XTAL_OUT1
P
HASE
VCO
ETECTO
R
CLK
VCCO_B
001
nCLK
FOUTB0
nFOUTB0
011
TEST_CLK
M
101
SEL1
SEL0
OE_B
MR
VCCO_REF
REF_CLK
TEST
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M8:M0
C
L
NA2:NA0
NB2:NB0
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
2
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
specific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal
fVCO = fxtal x M
frequency and the M divider is defined as follows:
The ICS843034 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscil-
lator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency.The VCO of the PLL operates over a range of 560MHz
to 750MHz. The output of the M divider is also applied to the
phase detector.
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23 ≤ M ≤ 30. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and Nx output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and Nx output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and Nx output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and Nx bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M,
NA, and NB inputs are passed directly to the M divider and
both N output dividers. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M and N dividers
remain loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and Nx bits can
be hardwired to set the M divider and Nx output divider to a
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Output
Output of M divider
FOUTA0 same frequency
SERIAL LOADING
S_CLOCK
S_DATA
T1
T0
NB2 NB1 NB0 NA2 NA1 NA0
M8
M7
M6
M5
M4
M3
M2
M1
M0
tS tH
S_LOAD
nP_LOAD
tS
P
ARALLEL LOADING
M0:M8, NA0:NA2, NB0:NB2
nP_LOAD
M, N
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
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ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 41, 42,
43, 44,
Name
M8, M0, M1,
M2, M3,
Type
Pulldown
Description
M divider input. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS/LVTTL interface levels.
Input
45, 47, 48
M4, M6, M7
2, 3
4
NB0, NB1
NB2
Input
Input
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS/LVTTL interface levels.
Pulldown
Output enable. Controls enabling and disabling of REF_CLK output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
5
6
7
OE_REF
OE_A
Input
Input
Input
Pulldown
Pullup
OE_B
Pullup
8, 14
9, 10
11
VCC
NA0, NA1
NA2
Power
Input
Core supply pins.
Pullup
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS/LVTTL interface levels.
Input
Pulldown
12, 24
VEE
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
13
TEST
Output
LVCMOS/LVTTL interface levels.
FOUTA0,
nFOUTA0
15, 16
17
Output
Power
Output
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
VCCO_A
FOUTB0,
nFOUTB0
18, 19
Differential output for the synthesizer. LVPECL interface levels.
20
21
22
23
VCCO_B
REF_CLK
VCCO_REF
nc
Power
Output
Power
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_CLK.
Unused
No connect.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
25
MR
Input
Pulldown inverted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not
affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
26
27
28
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
S_LOAD
Pulldown
29
30, 31
32
VCCA
Power
Input
Input
Analog supply pin.
SEL0, SEL1
TEST_CLK
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
Crystal oscillator interface. XTAL_IN0 is the input,
XTAL_OUT0 is the output.
Crystal oscillator interface. XTAL_IN1 is the input,
XTAL_OUT1 is the output.
33, 34
35, 36
Input
Input
XTAL_OUT1
Continued on next page...
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
4
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS, CONTINUED
Number
Name
Type
Description
37
CLK
Input Pulldown Non-inverting differential clock input.
Pullup/
38
39
nCLK
Input
Inverting differential clock input.VCC/2 default when left floating.
Pulldown
Parallel load input. Determines when data present at M8:M0 is
loaded into M divider, and when data present at NA2:NA0 and
NB2:NB0 is loaded into the N output dividers.
LVCMOS/LVTTL interface levels.
nP_LOAD
Input Pulldown
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS/LVTTL interface levels.
40
46
VCO_SEL
M5
Input
Input
Pullup
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation
Capacitance
CPD
REF_CLK
VCC, VCCA, VCCO_REF = 3.465V
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance REF_CLK
5
12
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
5
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
H
H
L
L
↑
X
↑
L
X
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
1
8
M3
0
4
M2
1
2
M1
1
1
M0
1
VCO Frequency
(MHz)
M Divide
575
•
23
•
•
•
•
•
•
•
•
•
•
700
•
28
•
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
750
30
0
0
0
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
*NX2
*NX1
*NX0
Minimum
560
Maximum
750
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
280
375
3
186.66
140
250
4
187.5
150
5
112
6
93.33
70
125
8
93.75
46.875
16
35
*NOTE: X denotes Bank A or Bank B
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
6
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Supply Voltage, VCC
4.6V
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
Core Supply Voltage
3.465
VCC
V
V
VCCA
Analog Supply Voltage
3.135
3.3
3.135
3.3
3.465
2.625
3.465
V
VCCO_A,
VCCO_B
Output Supply Voltage
2.375
2.5
V
VCCO_REF Output Supply
REF_CLK
3.135
3.3
V
IEE
Power Supply Current
Analog Supply Current
185
20
mA
mA
ICCA
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
7
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = VCCO_REF = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
VCC/2 + 0.2V
0.8
Units
VIH
VIM
VIL
Input High Voltage
2
V
V
V
Input Mid Voltage
Input Low Voltage
VCC/2 - 0.2V
-0.3
TEST_CLK, MR,
SEL[1:0], OE_REF,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD,
Nx2, M1:M4, M6:M8
VCC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
Nx0, Nx1, M5, OE_A,
OE_B, VCO_SEL
V
CC = VIN = 3.465V
TEST_CLK, MR,
SEL[1:0], OE_REF,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD,
Nx2, M1:M4, M6:M8
VCC = 3.465V,
VIN = 0V
-5
Input
Low Current
IIL
V
CC = 3.465V,
VIN = 0V
Nx0, Nx1, M5, OE_A,
OE_B, VCO_SEL
-150
µA
TEST; NOTE 1
REF_CLK
2.6
V
V
Output
High Voltage
VOH
VOL
V
CCO_REF = 3.3V 5%
VCCO_REF - 0.3V
0.4
0.5
Output
Low Voltage
TEST; NOTE 1
VCCO_REF = 3.3V 5%
V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = VCC = 3.465V
IN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
150
150
µA
µA
µA
µA
V
nCLK
CLK
V
-150
-5
IIL
Input Low Current
VIN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_A, VCCO_B - 2V.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
8
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
XTAL_IN0/XTAL_OUT0,
XTAL_IN1/XTAL_OUT1
12
12
40
MHz
fIN
Input Frequency
CLK/nCLK, TEST_CLK
S_CLOCK
TBD
50
MHz
MHz
ns
TEST_CLK
TBD
TBD
Input Rise/Fall
Time
tR/tF
S_LOAD, S_DATA,
S_CLOCK
ns
NOTE: For the input crystal, CLK/nCLK and TEST_CLK frequency range, the M value must be set for the VCO to operate
within the 560MHz to 750MHz range. Using the minimum input frequency of 12MHz, valid values of M are 47 ≤ M ≤ 62.
Using the maximum frequency of 40MHz, valid values of M are 14 ≤ M ≤ 18.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7A. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
35
750
MHz
333.33MHz,
Integration Range:
12kHz - 20MHz
Phase Jitter, RMS (Random);
NOTE 1, 2
tjit(Ø)
0.80
ps
tjit(cc)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 3, 4
Output Skew; NOTE 2, 4, 5
51
50
ps
ps
Measured @ the same
Output Frequency
LVPECL Outputs
Output
Rise/Fall Time
tR / tF
20% to 80%
200
700
ps
REF_CLK
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
%
tS
Setup Time
Hold Time
tH
odc
Output Duty Cycle
PLL Lock Time
50
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Characterized with REF_CLK output disabled.
NOTE 3: Jitter perforance using XTAL inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
9
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 7B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, VCCO_A = VCCO_B = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
35
750
MHz
333.33MHz,
Integration Range:
12kHz - 20MHz
Phase Jitter, RMS (Random);
NOTE 1, 2
tjit(Ø)
TBD
ps
tjit(cc)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 3, 4
Output Skew; NOTE 2, 4, 5
52
50
ps
ps
Measured @ the same
Output Frequency
LVPECL Outputs
Output
Rise/Fall Time
tR / tF
20% to 80%
200
700
ps
REF_CLK
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
%
tS
Setup Time
Hold Time
tH
odc
Output Duty Cycle
PLL Lock Time
50
tLOCK
1
ms
For notes, see Table 7A above.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
10
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 333.33MHZ
0
-10
-20
Filter
-30
-40
333.33MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.80ps (typical)
-50
-60
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
a Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
11
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
SCOPE
SCOPE
Qx
,
V
V
CC
Qx
,
V
V
V
CC
CCA
V
CCA, V
CCO__B
CCO_A,
CCO_A,
V
CCO__B
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-0.5V 0.125V
-1.3V 0.165V
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
FOUTA0/nFOUTA0, FOUTB0/nFOUTB0
1.65V 5%
VOH
VREF
SCOPE
,
V
V
CC
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
,
V
CCO_REF
CCA
Qx
LVCMOS
VEE
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
-1.65V 5%
3.3VCORE/3.3V REF_CLK OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nFOUTx
FOUTx
nFOUTA0
FOUTA0
tPW
tPERIOD
nFOUTy
tPW
FOUTy
tsk(o)
odc =
x 100%
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
80%
80%
80%
80%
VSWING
20%
Clock
Outputs
20%
20%
20%
Clock
Outputs
tR
tF
tF
tR
LVPECL OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
12
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS843034 provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, power supply isolation is required.
Figure 2 illustrates how a 10Ω resistor along with a 10µF and a
.01µF bypass capacitor should be connected to each VCCA pin.
3.3V, 2.5V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
13
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
14
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
CRYSTAL INPUT INTERFACE
The ICS843034 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 5 below were determined using a 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum
C1 and C2 values can be slightly adjusted for different board
layouts.
XTAL_OUT
C1
18p
X1
18pF Parallel Crystal
XTAL_IN
843034
C2
22p
Figure 5. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 6. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 6. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
15
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 7A and 7B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board de-
signers simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 7A. LVPECL OUTPUT TERMINATION
FIGURE 7B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
16
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 8A and Figure 8B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 8B can be eliminated and the termination
is shown in Figure 8C.
CC
CC
CC
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 8A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 8B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 8C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
17
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION SCHEMATIC EXAMPLE
Figure 9shows a schematic example of using an ICS843034. In
this example, the CLK/nCLK input is driven by a 3.3V LVPECL
driver. The data sheet also shows the CLK/nCLK input driven by
various types of drivers. The crystal inputs are parallel resonant
crystal with load capacitor CL=18pF. The frequency fine tuning
capacitors C1 and C2 are 22pF. This schematic example shows
hardwired logic control input handling. The logic inputs can also
be driven by 3.3V LVCMOS drivers. It is recommended to have
one decouple capacitor per power pin. In general, the decoupling
capacitor values are ranged from 0.01uF to 0.1uF. Each
decoupling capacitor should be located as close as possible to
the power pin. The low pass filter R9, C11 and C16 for clean
analog supply should also be located as close to the VCCA pin
as possible. Only two examples of 3.3V LVPECL termination are
shown in this schematic example.Additional LVPECL terminations
can be found in the LVPECL Termination Application Note. The
data sheet also shows 2.5V LVPECL terminations.The REF_CLK
is LVCMOS driver with 7Ω output impedance. Series termination
for REF_CLK is shown in the example. Additional LVCMOS
termination can be found in the LVCMOS Application Note. If the
REF_CLK is not used, it is recommended to disable this output
by setting REF_OE to logic low. To disable REF_CLK, REF_OE
pin can be left floating (default logic low by internal 51K pull down)
or pull down using an external 1kΩ resistor.
3.3V
Zo = 50
Zo = 50
C1
X1
C2
LVPECL
R10
50
R11
50
22p
CL=18pF 22p
C3
X1
C4
R12
50
1
2
3
4
5
6
7
8
9
10
11
12
36
22p
CL=18pF 22p
M8
X_OUT1
X_I N1
X_OUT0
X_I N0
TEST_CLK
SEL1
SEL0
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
35
34
33
32
31
30
29
28
27
26
25
NB0
NB1
NB2
OE_REF
OE_A
OE_B
VCC
NA0
NA1
NA2
VEE
VCC
VCC
C9
0.1u
R9
10
VCCA
U1
ICS843034
C11
0.01u
C16
10u
VCC
C5
0.1u
VCCO_REF
VCCO
C6
0.1u
Zo = 50 Ohm
C7
0.1u
C8
0.1u
+
-
Zo = 50 Ohm
VCC=3.3V
R2
50
R1
50
VCCO=3.3V
VCCO_REF=3.3V
R8
43 Zo = 50 Ohm
R3
50
LVCMOS
Logic Input Pin Examples
VCCO
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VCC
VCC
R4
133
R6
133
Zo = 50 Ohm
Zo = 50 Ohm
RU1
1K
RU2
SPARE
+
-
To Logic
Input
To Logic
Input
pins
pins
RD1
RD2
1K
R5
82.5
R7
82.5
SPARE
Alternative
Termination
Exmaple
FIGURE 9. ICS843034 APPLICATION SCHEMATIC EXAMPLE
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
18
ICS843034AY REV B JULY 18, 2006
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FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843034 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·
·
Power (core) = V
* I
= 3.465V * 185mA = 641mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 641mW + 60mW = 701mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.701W * 42.1°C/W = 99.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θ FOR 48-PIN LQFP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
19
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 10.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 10. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
20
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 9. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843034 is: 11,748
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
21
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
22
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS843034AY
Marking
Package
Shipping Packaging
tray
Temperature
ICS843034AY
ICS843034AY
ICS843034AYL
ICS843034AYL
48 Lead LQFP
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843034AYT
ICS843034AYLF
ICS843034AYLFT
48 Lead LQFP
1000 tape & reel
tray
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
23
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS™ MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo and HiPerClockS are trademarks of
Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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