843256AGILFT [IDT]
Clock Generator;
| 型号： | 843256AGILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总13页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS843256I is a Crystal-to-3.3V LVPECL • Six LVPECL outputs
ICS
HiPerClockS™
Clock Synthesizer/Fanout Buffer designed for
• Crystal oscillator interface
Fibre Channel and Gigabit Ethernet applications
and is a member of the HiperClockS™ family of
High Performance Clock Solutions from ICS.The
• Output frequency range: 53.125MHz to 333.3333MHz
• Crystal input frequency range: 25MHz to 33.333MHz
output frequency can be set using the frequency select
pins and a 25MHz crystal for Ethernet frequencies, or a
19.44MHz crystal for SONET. The low phase noise charac-
teristics of the ICS843256I make it an ideal clock for these
demanding applications.
• RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.33ps (typical)
• Full 3.3V or 3.3V core, 2.5V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
SELECT FUNCTION TABLE
Inputs
Function
FB_SEL N_SEL1 N_SEL0 M Divide N Divide
M/N
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
25
25
25
32
32
32
32
1
2
4
5
1
2
4
8
25
12.5
6.25
5
32
16
8
4
BLOCK DIAGRAM
PIN ASSIGNMENT
VCCO
VCCO
1
24
23
22
Q3
Q0
2
nQ3
3
nQ2
Q4
nQ0
4
Q2
nQ1
Q1
nQ0
nQ4
Q5
nQ5
N_SEL1
VEE
21
20
19
18
17
16
15
14
13
Pullup
PLL_BYPASS
5
6
7
Q1
1
0
nQ1
Q0
8
9
10
11
12
Output
Divider
PLL_BYPASS
VCCA
VEE
XTAL_IN
OSC
PLL
Q2
N_SEL0
XTAL_OUT
XTAL_IN
VCC
FB_SEL
XTAL_OUT
nQ2
ICS843256I
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm
body package
Q3
Feedback
Divider
nQ3
M Package
Top View
Pulldown
Pullup
Q4
FB_SEL
N_SEL1
nQ4
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
body package
Pullup
N_SEL0
Q5
G Package
Top View
nQ5
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843256AMI
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REV.A JUNE 16, 2006
1
PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
VCCO
Type
Description
Power
Output
Output
Output
Output supply pins.
3, 4
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
5, 6
7, 8
Differential output pair. LVPECL interface levels.
Selects between the PLL and crystal inputs as the input to the dividers.
9
PLL_BYPASS
Input
Pullup
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
10
11
12
VCCA
VCC
Power
Power
Analog supply pin.
Core supply pin.
FB_SEL
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
13,
14
15,
18
XTAL_IN,
XTAL_OUT
N_SEL0
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Input
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
N_SEL1
16, 17
19, 20
21, 22
23, 24
VEE
Negative supply pin.
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
843256AMI
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REV.A JUNE 16, 2006
2
PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 3. CRYSTAL FUNCTION TABLE
Inputs
Function
XTAL (MHz) FB_SEL N_SEL1 N_SEL0
M
25
25
25
25
25
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
VCO (MHz)
500
N
1
2
4
5
5
1
2
4
5
1
2
4
5
4
8
8
1
2
4
8
1
2
4
8
1
2
4
8
8
Output (MHz)
500
20
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
500
250
20
500
125
20
500
100
21.25
24
531.25
600
106.25
600
24
600
300
24
600
150
24
600
120
25
625
625
25
625
312.5
156.25
125
25
625
25
625
25.5
637.5
500
159.375
62.5
15.625
18.5625
18.75
18.75
18.75
18.75
19.44
19.44
19.44
19.44
19.53125
19.53125
19.53125
19.53125
20
594
74.25
600
600
600
300
600
150
600
75
622.08
622.08
622.08
622.08
625
622.08
311.04
155.52
77.76
625
625
312.5
156.25
78.125
80
625
625
640
843256AMI
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REV.A JUNE 16, 2006
3
PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θJA
24 Lead SOIC
24 LeadTSSOP
50°C/W (0 lfpm)
70°C/W (0 mps)
StorageTemperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – ICCA*10Ω
3.135
3.3
3.3
3.465
V
TBD
TBD
mA
mA
ICCA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – ICCA*10Ω
2.375
3.3
2.5
2.625
V
TBD
TBD
mA
mA
ICCA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL
VCC = VIN = 3.465V
150
µA
IIH
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
CC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
5
µA
µA
µA
FB_SEL
-5
IIL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
-150
843256AMI
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REV.A JUNE 16, 2006
4
PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
15.625
25.5
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VCC =VCCA = VCCO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
ps
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.33
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
TBD
50
ps
ps
%
20% to 80%
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
ps
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.32
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
TBD
50
ps
ps
%
20% to 80%
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
843256AMI
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REV.A JUNE 16, 2006
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
0
-10
-20
-30
Ethernet Filter
-40
-50
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.33ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Ethernet Filter to raw data
-200
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V/2.5V
0
-10
-20
Ethernet Filter
-30
-40
125MHz
-50
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.32ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
Phase Noise Result by adding
Ethernet Filter to raw data
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843256AMI
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REV.A JUNE 16, 2006
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
2.8V±0.04V
2V
2V
2V
SCOPE
SCOPE
VCC
VCCA
VCC
VCCO
,
Qx
Qx
VCCA
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0:nQ5
nQx
Qx
Q0:Q5
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100%
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSWING
20%
Clock
20%
Outputs
tF
tR
OUTPUT RISE/FALL TIME
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843256I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA and VCCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin.To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a .01µF bypass capacitor should be con-
nected to each VCCA pin. The 10Ω resistor can also be re-
placed by a ferrite bead.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
The ICS843256I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
LVPECL OUTPUT
All control pins have internal pull-ups or pull-downs; additional All unused LVPECL outputs can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached. Both sides of the
protection. A 1kΩ resistor can be used.
differential output pair should either be left floating or
terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 3A and
3B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUTTERMINATION
FIGURE 3B. LVPECL OUTPUTT ERMINATION
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REV.A JUNE 16, 2006
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for close to ground level. The R3 in Figure 4B can be eliminated
2.5V LVPECL driver. These terminations are equivalent to and the termination is shown in Figure 4C.
terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 4C. 2.5V LVPECLTERMINATION EXAMPLE
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REV.A JUNE 16, 2006
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOWT ABLE FOR 24 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOWT ABLE FOR 24 LEADTSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843256I is: 3863
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REV.A JUNE 16, 2006
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8B. PACKAGE DIMENSIONS
TABLE 8A. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Millimeters
SYMBOL
Minimum
Maximum
Minimum
Maximum
N
A
24
N
A
24
--
2.65
--
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
A1
A2
b
0.05
0.80
0.19
0.09
7.70
2.55
0.51
0.32
15.85
7.60
C
D
E
c
D
E
6.40 BASIC
0.65 BASIC
e
1.27 BASIC
E1
e
4.30
4.50
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
0.45
0°
0.75
8°
L
α
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-013, MO-119
Reference Document: JEDEC Publication 95, MO-153
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PRELIMINARY
ICS843256I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS843256AMI
Marking
TBD
Package
Shipping Packaging Temperature
24 Lead SOIC
tube
1000 tape & reel
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS843256AMIT
ICS843256AMILF
ICS843256AMILFT
ICS843256AGI
TBD
24 Lead SOIC
TBD
24 Lead "Lead-Free" SOIC
24 Lead "Lead-Free" SOIC
24 Lead TSSOP
TBD
1000 tape & reel
tube
TBD
ICS843256AGIT
ICS843256AGILF
ICS843256AGILFT
TBD
24 Lead TSSOP
2500 tape & reel
tube
TBD
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
843256AMI
www.icst.com/products/hiperclocks.html
REV.A JUNE 16, 2006
13
相关型号：
843256CK-24LF
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843256CK-24LFT
Clock Generator, 390.625MHz, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-24
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