843256BG [IDT]
Clock Generator, 625MHz, PDSO24, 4.40 X 7.80 MM, 0.92MM, MO-153, TSSOP-24;
| 型号： | 843256BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 625MHz, PDSO24, 4.40 X 7.80 MM, 0.92MM, MO-153, TSSOP-24 光电二极管 |
| 文件： | 总16页 (文件大小：2036K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY
SYNTHESIZER WITH/INTEGRATED FANOUT BUFFER
ICS843256
GENERAL DESCRIPTION
FEATURES
The ICS843256 is a Crystal-to-3.3V LVPECL Clock
• Six 3.3V differential LVPECL output pairs
ICS
HiPerClockS™
Synthesizer/Fanout Buffer designed for Fibre
Channel and Gigabit Ethernet applications and is
a member of the HiperClockS™ family of High
Performance Clock Solutions from IDT. The output
• Output frequency range: 62.5MHz to 625MHz
• Crystal input frequency range: 15.625MHz to 25.5MHz
• RMS phase jitter at 156.25MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.41ps (typical) @ 3.3V
frequency can be set using the frequency select pins and a
25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal
for SONET. The low phase noise characteristics of the
ICS843256 make it an ideal clock for these demanding
applications.
• Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
SELECT FUNCTION TABLE
Inputs
Function
FB_SEL N_SEL1 N_SEL0 M Divide N Divide
M/N
25
12.5
6.25
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
25
25
25
25
32
32
32
32
1
2
4
5
1
2
4
8
32
16
8
4
Q0
PIN ASSIGNMENT
BLOCK DIAGRAM
nQ0
VCCO
VCCO
1
24
23
22
21
20
19
18
17
16
15
14
13
Q3
Pullup
PLL_BYPASS
2
3
4
5
6
7
8
9
nQ3
Q4
nQ4
Q5
nQ5
N_SEL1
VEE
Q1
nQ2
Q2
nQ1
Q1
nQ0
Q0
1
nQ1
Q2
N
XTAL_IN
Output
Divider
PLL
OSC
0
XTAL_OUT
PLL_BYPASS
VCCA
VEE
nQ2
Q3
10
11
12
N_SEL0
XTAL_OUT
XTAL_IN
VCC
FB_SEL
M
Feedback
Divider
nQ3
Q4
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.92mm
body package
Pulldown
FB_SEL
Pullup
G Package
Top View
N_SEL1
nQ4
Q5
Pullup
N_SEL0
nQ5
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
N
u
m
be
r
N
a
m
e
T
y
p
e
Description
1, 2
3, 4
5, 6
7, 8
VCCO
Power
Output supply pins.
nQ2, Q2
nQ1, Q1
nQ0, Q0
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Selects between the PLL and crystal inputs as the input to the dividers.
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
9
PLL_BYPASS
Input
Pullup
10
11
12
VCCA
VCC
Power
Power
Analog supply pin.
Core supply pin.
FB_SEL
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
13,
14
15,
18
XTAL_IN,
XTAL_OUT
N_SEL0
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Input
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
N_SEL1
16, 17
19, 20
21, 22
23, 24
VEE
Negative supply pin.
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3. CRYSTAL FUNCTION TABLE
Inputs
Function
VCO (MHz)
XTAL (MHz) FB_SEL N_SEL1 N_SEL0
M
25
25
25
25
25
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
N
1
2
4
5
5
1
2
4
5
1
2
4
5
4
8
8
1
2
4
8
1
2
4
8
1
2
4
8
8
Output (MHz)
500
20
20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
500
500
250
20
500
125
20
500
100
21.25
24
531.25
600
106.25
600
24
600
300
24
600
150
24
600
120
25
625
625
25
625
312.5
156.25
125
25
625
25
625
25.5
637.5
500
159.375
62.5
15.625
18.5625
18.75
18.75
18.75
18.75
19.44
19.44
19.44
19.44
19.53125
19.53125
19.53125
19.53125
20
594
74.25
600
600
600
300
600
150
600
75
622.08
622.08
622.08
622.08
625
622.08
311.04
155.52
77.76
625
625
312.5
156.25
78.125
80
625
625
640
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ 37°C/W (0 mps)
JA
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
190
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Vcc – 0.12
3.135
3.3
3.3
V
mA
mA
ICCA
12
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
2.625
190
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Vcc – 0.12
2.375
3.3
2.5
V
mA
mA
ICCA
12
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL
VCC = VIN = 3.465V
150
µA
IIH
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
CC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
5
µA
µA
µA
FB_SEL
-5
IIL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
-150
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
15.625
25.5
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VCC = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
62.5
625
MHz
156.25MHz, Integration Range:
1.875MHz - 20MHz
156.25MHz, Integration Range:
12kHz - 20MHz
0.41
0.85
ps
tjit(Ø)
RMS Phase Jitter (Random)
ps
tsk(o)
Output Skew; NOTE 1, 2
Output Rise/Fall Time
40
650
53
ps
ps
ꢀ
tR / tF
20ꢀ to 80ꢀ
200
47
FOUT ≤ 312.5MHz
FOUT > 312.5MHz
odc
Output Duty Cycle
45
55
ꢀ
tLOCK
PLL Lock Time
20
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
62.5
625
MHz
156.25MHz, Integration Range:
1.875MHz - 20MHz
156.25MHz, Integration Range:
12kHz - 20MHz
0.41
0.85
ps
tjit(Ø)
RMS Phase Jitter (Random)
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
45
650
54
ps
ps
ꢀ
20ꢀ to 80ꢀ
200
46
tLOCK
20
ms
For NOTES, please see Table 6A above.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.8V 0.04V
2V
2V
2V
2.8V 0.04V
VCC
SCOPE
VCC
VCCO
,
SCOPE
Qx
VCCO
Qx
VCCA
VCCA
LVPECL
LVPECL
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
nQ0:nQ5
Q0:Q5
tPW
nQy
tPERIOD
Qy
tPW
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
80ꢀ
tF
80ꢀ
Phase Noise Mask
VSWING
20ꢀ
Clock
20ꢀ
Outputs
tR
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT RISE/FALL TIME
RMS PHASE JITTER
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843256 provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VCC, VCCA, and VCCO should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, power supply isolation is required.
Figure 1 illustrates how a 10Ω resistor along with a 10μF and a
.01μF bypass capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
LVPECL OUTPUTS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
The ICS843256 has been characterized with 18pF parallel
were determined using an 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
resonant crystals. The capacitor values shown in Figure 2 below
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3 The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminat-
ing 50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to
ground level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
CC
CC
CC
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
Zo = 50 Ohm
Zo = 50 Ohm
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843256.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843256 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·
·
Power (core) = V
* I
= 3.465V * 190mA = 658.35mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power
(3.465V, with all outputs switching) = 658;.35mW + 180mW = 838.35mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.838W * 37°C/W = 101°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7B. THERMAL RESISTANCE θ FOR 24-PIN TSSOP, E-PAD FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37°C/W
31°C/W
30°C/W
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
12
ICS843256BG REV. A MAY 23, 2007
ICS843256
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP, E-PAD
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37°C/W
31°C/W
30°C/W
TRANSISTOR COUNT
The transistor count for ICS843256 is: 3863
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
13
ICS843256BG REV. A MAY 23, 2007
ICS843256
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Nominal
24
SYMBOL
Minimum
Maximum
N
A
--
1.10
0.15
0.95
0.30
0.25
0.20
0.16
7.90
A1
A2
b
0.05
0.85
0.19
0.19
0.09
0.09
7.70
0.90
0.22
b1
c
c1
D
0.127
7.80
E
6.40 BASIC
4.40
E1
e
4.30
0.50
4.50
0.65 BASIC
0.60
L
0.70
5.0
3.2
8°
P
P1
α
0°
aaa
bbb
0.076
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
14
ICS843256BG REV. A MAY 23, 2007
ICS843256
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS843256BG
Marking
Package
Shipping Packaging Temperature
ICS843256BG
ICS843256BG
ICS843256BGLF
ICS843256BGLF
24 Lead TSSOP, E-Pad
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843256BGT
ICS843256BGLF
ICS843256BGLFT
24 Lead TSSOP, E-Pad
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP, E-Pad
24 Lead "Lead-Free" TSSOP, E-Pad
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER
15
ICS843256BG REV. A MAY 23, 2007
ICS843256
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS, FemtoClocks and HiPerClockS
are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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