84325EMT [IDT]
Clock Generator, 250MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24;
| 型号： | 84325EMT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 250MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84325
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84325 is a Crystal-to-3.3 VLVPECL Frequency
Synthesizer with Fanout Buffer. The output frequency can be
programmed using frequency select pins. The low phase
noise characteristics of the ICS84325 make it an ideal
clocksource for Fibre Channel 1, Fibre Channel 2, Infiniband
and Gigabit Ethernet applications.
• 6 differential 3.3V LVPECL outputs
• Crystal oscillator interface
• Output frequency range: 106.25MHz to 250MHz
• Crystal input frequency: 25MHz and 25.5MHz
• Output skew: 60ps (maximum)
• RMS phase jitter at 212.5MHz, using a 25.5MHz crystal
(637KHz to 10MHz): 2.76ps
• Phase noise: Typical at 212.5MHz
Offset
Noise Power
100Hz ................. -92 dBc/Hz
1KHz ................. -112 dBc/Hz
10KHz ................. -120 dBc/Hz
100KHz ................. -122 dBc/Hz
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package available.
FUNCTION TABLE
• Industrial temperature information available upon request
Inputs
XTAL
Output Frequency
F_OUT
MR F_SEL1 F_SEL0
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
LOW
25.5MHz
25.5MHz
25MHz
106.25MHz
212.5MHz
125MHz
25MHz
250MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
24
23
22
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
VCCO
F_SEL0
F_SEL1
XTAL1
6
21 MR
20
19 XTAL2
VEE
18
17 VCCA
16 VCC
Q0:Q5
0
OSC
/
Output
Divider
XTAL1
XTAL2
6
/
nQ0:nQ5
1
PLL
9
nQ4
Q5
nQ5
PLL_SEL
VEE
VCCO
10
11
12
15
14
13
Feedback
Divider
ICS84325
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
TopView
F_SEL1
MR
PLL_SEL
F_SEL0
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VCCO
Type
Description
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 24
16
VCC
Core supply pin.
14, 18
VEE
PLL_SEL
VCCA
Negative supply pins.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
15
Input
Pullup
17
Power
Analog supply pin.
19, 20
XTAL2, XTAL1 Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
21
MR
Input Pulldown
22
23
F_SEL1
F_SEL0
Input Pulldown Feedback frequency select pin. LVCMOS / LVTTL interface levels.
Input Pullup Output select pin. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
50°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.465
3.465
210
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
ICCA
27
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR, F_SEL1
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
PLL_SEL, F_SEL0
MR, F_SEL1
V
-5
IIL
Input Low Current
PLL_SEL, F_SEL0
VCC = 3.465V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.8
VCCO - 1.7
1.2
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
25
25.5
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FOUT
Output Frequency
106.25
250
60
800
52
54
57
60
1
MHz
ps
ps
ꢀ
tsk(o)
tR / tF
Output Skew; NOTE 1, 2
Output Rise/Fall Time
20ꢀ to 80ꢀ
fOUT = 106.25MHz
fOUT = 125MHz
fOUT = 212.5MHz
fOUT = 250MHz
300
48
46
43
ꢀ
odc
Output Duty Cycle
ꢀ
40
ꢀ
tLOCK
PLL Lock Time
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TYPICAL PHASE NOISE
0
Fibre Channel 1
Bandpass Filter
-10
-20
-30
-40
-50
-60
Jitter BW Jitter Filter
Diff. Jitter
Source
Mode
Process Result
Noise only
70
-
Freq. carrier
106.250M Hz
-80
Start Freq.
10.000
Stop Freq.
Jitter
-90
-100
-110
-120
-130
40.000M Hz
2.62 ps
Raw phase noise data
-140
-150
-160
-170
-180
-190
Phase noise result by adding
Bandpass Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
0
-10
Fibre Channel 2
Bandpass Filter
-20
-30
-40
-50
Jitter BW
Jitter Filter
Diff. Jitter
Source
Mode
-60
-70
Process Result
Noise only
Freq. carrier
212.500M Hz
-80
Start Freq.
10.000
Stop Freq.
Jitter
2.76
-90
40.000M Hz
ps
-100
Raw phase noise data
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase noise result by adding
Bandpass Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
VCC,
VCCA
Qx
nQx
Qx
LVPECL
VEE
nQy
Qy
nQx
tsk(o)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQ0:nQ5
80ꢀ
tF
80ꢀ
Q0:Q5
Pulse Width
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS84325 provides sepa-
3.3V
VCC
rate power supplies to isolate any high switching
and
.01μF
.01μF
24Ω
noise from the outputs to the internal PLL. VCC, VCCA
VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
VCCA
10 μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Z
o = 50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
CRYSTAL INPUT INTERFACE
The ICS84325 has been characterized with 18pF parallel resonant were chosen to minimize the ppm error. The optimum C1 and C2
crystals.The capacitor values, C1 and C2, shown in Figure 3 below values can be slightly adjusted for different board layouts.
were determined using a 25MHz, 18pF parallel resonant crystal and
XTAL2
C1
22p
X1
18pF Parallel Cry stal
XTAL1
C2
22p
Figure 4. CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an ICS84325. In
therefore the output frequency is 250MHz. It is recommended to
this example, the input is a 25MHz parallel resonant crystal with have one decouple capacitor per power pin. Each decoupling
load capacitor CL=18pF. The frequency fine tuning capacitors capacitor should be located as close as possible to the power
C1 and C2 are 22pF respectively.This example also shows logic
pin.The low pass filter R7, C11 and C16 for clean analog supply
control input handling.The configuration is set at F_SEL[1:0]=11 should also be located as close to the VCCA pin as possible.
VCC
U7
VCC
R4
1K
VCC
Zo = 50
Zo = 50
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
8
7
6
5
4
3
VCC
VEE
PLL_SEL
VCC
VCCA
VEE
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
VCC
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
-
R7
24
VCCA
22p
+
C11
0.1u
C16
10u
C1
R2
50
R1
50
F_SEL1
F_SEL0
X1
25MHz,18pF
R5
1K
2
1
C2
R3
50
VCC
22p
ICS84325
RU2
1K
RU3
1K
VCC=3.3V
F_SEL1
F_SEL0
VCC
(U1,13)
(U1,16)
(U1,24)
C6
0.1u
C5
0.1u
C3
0.1u
e.g. F_SEL[1:0]=11
RD2
SP
RD3
SP
SP = Spare, Not Installed
FIGURE 5A. ICS84325 SCHEMATIC EXAMPLE
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
• The differential 100Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C6
GND
VCC
C1
C5
Signals
VIA
R7
VCCA
C16
C11
X1
C3
C2
50 Ohm Traces
Pin1
U1 ICS84325
FIGURE 5B. PCB BOARD LAYOUT FOR ICS84325
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84325.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84325 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 210mA = 727.7mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 727.7mW + 181mW = 908.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.909W * 43°C/W = 113.9°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω) * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW L
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84325 is: 3500
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CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
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FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
84325EM
Marking
ICS84325EM
ICS84325EM
ICS84325EMLN
ICS84325EMLN
Package
24 Lead SOIC
24 Lead SOIC
Shipping Packaging
Tube
1000 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
84325EMT
84325EMLN
84325EMLNT
24 Lead "Lead-Free" SOIC
24 Lead "Lead-Free" SOIC
1000 Tape & Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc.(IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
84325EM
www.idt.com
REV. C JULY 21, 2010
14
ICS84325
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
REVISION HISTORY SHEET
Description of Change
LVPECL DC Characteristics Table
Rev
Table
T3
Page
3
Date
Changed VOH max. from VCCO - 1.0V to VCCO - 0.8V.
Changed VSWING max. from 1.0V to 1.2V. Corrected Units.
B
10/1/03
10/11/04
7/21/10
T9
T9
14
Ordering Information Table - added Lead-Free part number.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
C
14
16
84325EM
www.idt.com
REV. C JULY 21, 2010
15
ICS84325
CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER WITH FANOUT BUFFER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
84325EM
www.idt.com
REV. C JULY 21, 2010
16
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