84327AMLF [IDT]
Clock Generator, 625MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24;
| 型号： | 84327AMLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 625MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84327 is a Crystal-to-3.3V LVPECL • 6 LVPECLoutputs
,&6
Clock Synthesizer/Fanout Buffer designed for
• Crystal oscillator interface
• Output frequency range: 77.76MHz to 625MHz
HiPerClockS™
SONET, 10 Gigabit Fibre Channel and 10 Giga-
bit Ethernet applications and is a member of the
HiperClockS family of High Performance Clock
• Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
Solutions from ICS. The output frequency can be set using
the frequency select pins and a 19.44MHz crystal for SONET
frequencies, or a 25MHz crystal for 10 Gigabit Ethernet fre-
quencies, or a 25.5MHz crystal for a 10 Gigabit Fibre Chan-
nel. The low phase noise characteristics of the ICS84327 make
it an ideal clock for these demanding applications.
• RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12KHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz .................. -92 dBc/Hz
1KHz ................ -105 dBc/Hz
10KHz ................ -122 dBc/Hz
100KHz ................ -123 dBc/Hz
FUNCTION TABLE
Output
Frequency
Inputs
• Full 3.3V or 3.3V core, 2.5V output supply mode
• 0°C to 70°C ambient operating temperature
F_XTAL
X
MR SEL2
SEL1 SEL0
F_OUT
LOW
1
0
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
1
19.44MHz
19.44MHz
19.44MHz
19.44MHz
25MHz
77.76MHz
155.52MHz
311.04MHz
622.08MHz
78.125MHz
156.25MHz
312.5 MHz
625MHz
• Industrial temperature information available upon request
25MHz
25MHz
25MHz
25.5MHz
159.375MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
VCCO
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
F_SEL2
VCCA
XTAL1
OSC
XTAL2
6
Q0:Q5
0
1
/
Output
Divider
5
6
7
6
/
nQ0:nQ5
PLL
8
9
10
11
12
VCC
nQ4
Q5
nQ5
PLL_SEL
VEE
VCCO
Feedback
Divider
ICS84327
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL2 MR PLL_SEL
F_SEL1
F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84327AM
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REV. A SEPTEMBER 18, 2003
1
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VCCO
Type
Description
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 24
16
VCC
Core supply pin.
14
VEE
Negative supply pin.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
15
PLL_SEL
Input
Pullup
17
18
VCCA
Power
Input
Analog supply pin.
F_SEL2
Pullup
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
19, 20
XTAL2, XTAL1 Input
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low, and the inverted
outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
21
MR
Input Pulldown
22
23
F_SEL1
F_SEL0
Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels.
Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
K
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
K
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REV. A SEPTEMBER 18, 2003
2
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 50°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
140
20
mA
mA
ICCA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
VIH
VIL
Input High Voltage
2
V
CC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR, F_SEL1
V
CC = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
PLL_SEL, F_SEL0
MR, F_SEL1
VCC = VIN = 3.465V
V
CC = 3.465V, VIN = 0V
CC = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_SEL, F_SEL0
V
-150
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 1.0
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
2.375
2.5
V
140
20
mA
mA
ICCA
84327AM
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REV. A SEPTEMBER 18, 2003
3
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Inc.
C
RYSTAL
-
TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
19.44
2±.±
±0
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
NOTE: Characterized using an 18pf parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±±5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
tsk(o)
tR / tF
odc
Output Frequency
77.76
62±
700
1
MHz
ps
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
30
±0
205 to 805
200
ps
5
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 6±.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±±5, VCCO = 2.±V±±5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
tsk(o)
tR / tF
odc
Output Frequency
77.76
62±
700
1
MHz
ps
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
30
±0
205 to 805
200
ps
5
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 6±.
84327AM
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REV. A SEPTEMBER 18, 2003
4
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Inc.
C
RYSTAL
-
TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
TYPICAL PHASE NOISE
0
-10
19.44MHz Input
RMS Phase Noise Jitter
-20
-30
12K to 20MHz = 3.4ps (typical)
-40
622.08MHz
311.04MHz
155.52MHz
77.76MHz
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
0
25MHz Input
RMS Phase Noise Jitter
-10
-20
-30
-40
-50
-60
-70
-80
-90
12K to 20MHz = 3.2ps (typical)
625MHz
312.5MHz
156.25MHz
78.125MHz
100
-
-110
-120
-130
-140
-150
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
84327AM
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REV. A SEPTEMBER 18, 2003
5
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2V
2.8V+0.04V
SCOPE
SCOPE
Qx
VCC
VCCA, VCCO
,
VCC
VCCA
,
Qx
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0:nQ5
nQx
Qx
Q0:Q5
Pulse Width
tPERIOD
nQy
tPW
odc =
Qy
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
80%
VSWING
20%
Clock
20%
Outputs
tF
tR
OUTPUT RISE/FALL TIME
84327AM
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REV. A SEPTEMBER 18, 2003
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PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84327 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA and VCCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a .01µF bypass capacitor should be con-
nected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched impedance
techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 2A and 2B
show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
(VOH + VOL / VCC – 2) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
84327AM
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REV. A SEPTEMBER 18, 2003
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PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V ground level. The R3 in Figure 3B can be eliminated and the
LVPECL driver. These terminations are equivalent to terminat- termination is shown in Figure 3C.
ing 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
F
IGURE 3B. 2.5V LVPECL DRIVER
T
ERMINATION
E
XAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
84327AM
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REV. A SEPTEMBER 18, 2003
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PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
CRYSTAL INPUT INTERFACE
determined using a 25MHz 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
The ICS84327 has been characterized with 18pF parallel reso-
nant crystals. The capacitor values shown in Figure 4 below were
19
XTAL2
C1
18pF
25MHz X1
20
XTAL1
C2
22pF
ICS84327
Figure 4. CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an ICS84327. is 625MHz. It is recommended to have one decouple capaci-
In this example, the input is a 25MHz parallel resonant crystal tor per power pin. Each decoupling capacitor should be lo-
with load capacitor CL=18pF. The frequency fine tuning cated as close as possible to the power pin. The low pass
capacitors C1 and C2 is 22pF and 18pF respectively. This filter R7, C11 and C16 for clean analog supply should also be
example also shows logic control input handling. The configu- located as close to the VCCA pin as possible.
ration is set at F_SEL[2:0]=011, therefore, the output frequency
VCC
U1
VCC
R4
1K
VCC
Zo = 50
Zo = 50
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
8
7
6
5
4
3
VCCO
VEE
PLL_SEL
VCC
VCCA
F_SEL2
XTAL2
XTAL1
MR
F_SEL1
F_SEL0
VCCO
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
-
R7
24
VCCA
22p
+
F_SEL2
C11
0.1u
C16
10u
C1
R2
50
R1
50
F_SEL1
F_SEL0
X1
25MHz,18pF
R5
1K
2
1
C2
R3
50
VCC
18p
ICS84327
RU1
SP
RU2
1K
RU3
1K
VCC=3.3V
F_SEL2
F_SEL1
F_SEL0
VCC
(U1,13)
(U1,16)
(U1,24)
C6
0.1u
C5
0.1u
C3
0.1u
e.g. F_SEL[2:0]=011
RD1
1K
RD2
SP
RD3
SP
SP = Spare, Not Installed
FIGURE 5A. ICS84327 SCHEMATIC EXAMPLE
84327AM
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PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C6
GND
VCC
C1
C5
Signals
VIA
R7
VCCA
C16
C11
X1
C3
C2
50 Ohm Traces
Pin1
U1 ICS84327
FIGURE 5B. PCB BOARD LAYOUT FOR ICS84327
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REV. A SEPTEMBER 18, 2003
10
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84327.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84327 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 485mW + 181mW = 666mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.666W * 43°C/W = 98.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
84327AM
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REV. A SEPTEMBER 18, 2003
11
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
84327AM
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REV. A SEPTEMBER 18, 2003
12
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84327 is: 2804
84327AM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
13
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
Reference Document: JEDEC Publication 95, MS-013, MO-119
84327AM
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REV. A SEPTEMBER 18, 2003
14
PRELIMINARY
ICS84327
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER W/INTEGRATED
FANOUT
BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
24 Lead SOIC
24 Lead SOIC on Tape and Reel
Count
Temperature
0°C to 70°C
0°C to 70°C
ICS84327AM
ICS84327AM
ICS84327AM
30 per tube
1000
ICS84327AMT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84327AM
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REV. A SEPTEMBER 18, 2003
15
相关型号：
84327AMLFT
Clock Generator, 625MHz, PDSO24, 7.50 X 15.33 MM, 2.30 MM HEIGHT, MS-013, MO-119, SOIC-24
IDT
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