8432CY-111T [IDT]
PLL Based Clock Driver, 8432 Series, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 8432CY-111T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8432 Series, 2 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总18页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-111 is a general purpose, dual output
Differential-to-3.3V LVPECL High Frequency Synthesizer.
The ICS8432-111 has a selectable differential CLK, nCLK
pair or LVCMOS/LVTTL TEST_CLK. The TEST_CLK input
accepts LVCMOS or LVTTL input levels and translates them
to 3.3V LVPECL levels. The CLK, nCLK pair can accept most
standard differential input levels.The VCO operates at a
frequency range of 200MHz to 700MHz. The VCO frequency
is programmed in steps equal to the value of the input differ-
ential or single ended reference frequency. Output frequen-
cies up to 700MHz for FOUT and 350MHz for FOUT/2 can be
programmed using the serial or parallel interfaces to the con-
figuration logic. The low phase noise characteristics and the
multiple frequency outputs of the ICS8432-111 makes it an
ideal clock source for Fibre Channel 1 and 2, and Infiniband
applications.
• Dual differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK pair or LVCMOSTEST_CLK
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• TEST_CLK can accept the following input types:
LVCMOS or LVTTL
• Maximum FOUT frequency: 700MHz
Maximum FOUT/2 frequency: 350MHz
• CLK, nCLK or TEST_CLK input frequency: 40MHz
• VCO range: 250MHz to 700MHz
• Parallel or serial interface for programming counter
andVCO frequency multiplier and dividers
• RMS period jitter: 5ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
CLK_SEL
TEST_CLK
0
1
32 31 30 29 28 27 26 25
CLK
nCLK
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
VCCA
ICS8432-111
10 11 12 13 14 15 16
32-Lead LQFP
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
÷1
÷2
÷4
÷8
MR
0
1
VEE
VCO
FOUT
nFOUT
FOUT/2
nFOUT/2
9
÷M
÷2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
7mm x 7mm x 1.4mm package body
M0:M8
N0:N1
Y Package
TopView
8432CY-111
www.idt.com
REV. C OCTOBER 5, 2010
1
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
rial event occurs. As a result, the M and N bits can be hardwired
eration using a 25MHz clock input. Valid PLL loop divider to set the M divider and N output divider to a specific default
values for different input frequencies are defined in the Input state that will automatically occur during power-up.The TEST
output is LOW when operating in the parallel input mode. The
relationship between the VCO frequency, the input frequency
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-111 features a fully integrated PLL and there- and the M divider is defined as follows: fVCO = fIN x M
fore requires no external components for setting the loop band-
width. A differential clock input is used as the input to the The M value and the required values of M0 through M8 are shown
ICS8432-111. This input is fed into the phase detector. A inTable 3B, ProgrammableVCO Frequency FunctionTable.When
the input clock is at 25MHz, the valid M values for which the
25MHz clock input provides a 25MHz phase detector refer-
ence frequency. The VCO of the PLL operates over a range PLL will achieve lock are defined as 10 ≤ M ≤ 28.The frequency
fOUT = fVCO = f x M
of 250MHz to 700MHz. The output of the M divider is also out is defined as follows:
applied to the phase detector.
IN
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
The phase detector and the M divider force the VCO output LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M register are loaded into the M divider and N output divider when
(either too high or too low), the PLL will not achieve lock.The S_LOAD transitions from LOW-to-HIGH.The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
each of the LVPECL output buffers. The divider provides a S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
output of the VCO is scaled by a divider prior to being sent to
50% output duty cycle.
passed directly to the M divider and N output divider on each rising
edge of S_CLOCK. The serial mode can be used to
The programmable features of the ICS8432-111 support two program the M and N bits and test bitsT1 andT0.The internal reg-
input modes to program the PLL M divider and N output divider. istersT0 andT1 determine the state of theTEST output as follows:
The two input operational modes are parallel and serial. Figure1
T1 T0
TEST Output
LOW
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW.The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a se-
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout/2
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
T1
T0 *NULL N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
PARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8432CY-111
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REV. C OCTOBER 5, 2010
2
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
M5
Input
Input
Pullup
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS/LVTTL interface levels.
2, 3, 4,
28, 29,
M6, M7, M8,
M0, M1,
Pulldown
30, 31, 32
M2, M3, M4
Determines output divider value as defined in Table 3C
Function Table. LVCMOS/LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
9
TEST
VCC
Output
Power
Output
10
Core supply pin.
11,
12
FOUT/2,
nFOUT/2
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
13
VCCO
Power
Output
Output supply pin.
14, 15
FOUT, nFOUT
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
are the outputs are enabled. Assertion of MR does not effect loaded
M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between differential clock input or test input as the PLL
22
CLK_SEL
Input
Pullup
reference source. LVCMOS/LVTTL interface levels. Selects CLK,
nCLK inputs when HIGH. Selects TEST_CLK when LOW.
23
24
25
TEST_CLK
CLK
Input
Input
Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Parallel load input. Determines when data present at M8:M0 is loaded
26
27
nP_LOAD
VCO_SEL
Input
Input
Pulldown into M divider, and when data present at N1:N0 sets the N output
divider value. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
8432CY-111
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REV. C OCTOBER 5, 2010
3
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
S_LOAD S_CLOCK S_DATA
Conditions
MR nP_LOAD
M
N
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M
divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to ripple counter as it is
clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Count
250
275
•
10
11
•
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequencies correspond to differential input or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency (MHz)
Inputs
N Divider Value
FOUT
FOUT/2
N1
0
N0
0
Minimum
250
Maximum
700
Minimum
125
Maximum
350
1
2
4
8
0
1
125
350
62.5
175
1
0
62.5
175
31.25
15.625
87.5
1
1
31.25
87.5
43.75
8432CY-111
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REV. C OCTOBER 5, 2010
4
ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
140
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, CLK_SEL,
S_LOAD, S_DATA, S_CLOCK,
nP_LOAD, N0:N1, M0:M8, MR
2
2
VCC + 0.3
V
V
Input
VIH
High Voltage
TEST_CLK
VCC + 0.3
VCO_SEL, CLK_SEL,
S_LOAD, S_DATA, S_CLOCK,
nP_LOAD, N0:N1, M0:M8, MR
-0.3
0.8
V
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
VCC = VIN = 3.465V
150
µA
Input
IIH
High Current
M5, CLK_SEL, VCO_SEL
V
CC = VIN = 3.465V
5
µA
µA
M0-M4, M6-M8, N0, N1,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD, MR
VCC = 3.465V,
IN = 0V
-5
V
Input
IIL
Low Current
V
CC = 3.465V,
IN = 0V
M5, CLK_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
V
Output
VOH
High Voltage
Output
VOL
TEST; NOTE 1
0.5
V
Low Voltage
NOTE 1: Outputs terminated with 50Ω toVCCO/2.See Parameter Information, 3.3V Output LoadTest Circuit.
8432CY-111
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current
CLK
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
nCLK
CLK
V
-5
-150
IIL
Input Low Current
nCLK
VCC = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
10
10
40
40
50
MHz
MHz
MHz
fIN
Input Frequency CLK, nCLK; NOTE 1
S_CLOCK
NOTE 1: For the input frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz
range. Using the minimum input frequency of 10MHz, valid values of M are 25 ≤ M ≤ 70. Using the maximum frequency
of 40MHz, valid values of M are 7 ≤ M ≤ 17.
8432CY-111
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
31.25
Typical
Maximum
Units
MHz
MHz
ps
FOUT
Output Frequency
700
FOUT/2
tjit(cc)
tjit(per)
tsk(o)
Output Frequency
15.625
350
Cycle-to-Cycle Jitter; NOTE 2
Period Jitter, RMS; NOTE 2
Output Skew; NOTE 1, 2
Output Rise/Fall Time
40
fOUT > 100
20% to 80%
5
ps
60
ps
tR / tF
200
700
ps
M, N to nP_LOAD
5
ns
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
ns
5
ns
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
tPW
Output Duty Cycle
Output Pulse Width
PLL Lock Time
fOUT/2; fOUT, N > 1
47
53
%
tPeriod/2 - 150
tPeriod/2 + 150
1
ps
tLOCK
ms
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
,
Qx
VCCA, VCCO
nCLK
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
CLK
-1.3V 0.165V
VEE
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nFOUT
FOUT
nFOUT,
nFOUT/2
FOUT,
FOUT/2
➤
➤
➤
nFOUT/2
tcycle n
tcycle n+1
➤
FOUT/2
tsk(o)
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
VOH
80%
tF
80%
tR
VREF
VSWING
Clock
Outputs
20%
20%
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT RISE/FALL TIME
nFOUT,
nFOUT/2
FOUT,
FOUT/2
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
8432CY-111
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-111 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. Vcc, VccA, and VccO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VccA pin.
3.3V
Vcc
.01μF
.01μF
10Ω
VccA
10μF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8432CY-111
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
Z
o = 50Ω
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
8432CY-111
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals.BothVSWING andVOH must meet the component to confirm the driver termination requirements. For
VPP and VCMR input requirements. Figures 5A to 5E show
example in Figure 5A, the input termination applies for LVHSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another ven-
common driver types.The input interfaces suggested here are dor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 5A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 5B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 5C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
C2
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 5E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
8432CY-111
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-111.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-111 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 60mW = 545.1mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = junction-to-ambient thermal resistance
Pd_total =Total device power dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.545W * 42.1°C/W = 93°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
8432CY-111
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO _MAX
OH_MAX
L
CCO
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8432CY-111
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-111 is: 3765
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV. C OCTOBER 5, 2010
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
8432CY-111
8432CY-111T
8432CY-111LF
8432CY-111LFT
ICS8432C-111
ICS8432C-111
ICS8432C111L
ICS8432C111L
32 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
32 Lead LQFP
1000 tape & reel
tray
32 lead Lead Free LQFP
32 lead Lead Free LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated DeviceTechnology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T4A
5
12
Power Supply table - adjusted the IEE limit from 120mA max. to 140mA max.
Adjusted Power Dissipation to comply with IEE.
B
3/3/04
1
2
6
Features Section - added lead-free bullet.
Corrected Figure 1, Paralle & Serial Load Operations Diagram
LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to
T4D
T10
C
C
VCCO - 0.9V
4/12/07
10/5/10
12 - 13 Power Considerations - corrected power dissipation to reflect VOH max in Table
4D.
Ordering Information Table - added lead-free part number and note.
Updated datasheet's header/footer with IDT from ICS.
Ordering Information Table - removed ICS prefix from Part/Order Number
column. Added LF marking and corrected non-LF marking.
Added Contact Page.
16
18
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ICS8432-111
700MHZ/350MHZ
DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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