8432CY-11 [IDT]
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32;
| 型号： | 8432CY-11 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC-HD, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总20页 (文件大小：923K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8432-11
700MHz/350MHz, Crystal-to-3.3V LVPECL
Frequency Synthesizer
DATA SHEET
General Description
Features
The ICS8432-11 is a general purpose, dual output Crystal-to-3.3V
Differential LVPECL High Frequency Synthesizer. The ICS8432-11
has a selectable TEST_CLK or crystal inputs. The TEST_CLK input
accepts LVCMOS or LVTTL levels and translates them to 3.3V
LVPECL levels. The VCO operates at a frequency range of 200MHz
to 700MHz. The VCO frequency is programmed in steps equal to the
value of the input reference or crystal frequency. Output frequencies
up to 700MHz for FOUT and 350MHz for FOUT/2 can be
programmed using the serial or parallel interfaces to the
configuration logic.
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface or LVCMOS/LVTTL
TEST_CLK
• TEST_CLK can accept the following input levels: LVCMOS or
LVTTL
• Maximum FOUT frequency: 700MHz
• Maximum FOUT/2 frequency: 350MHz
• VCO range: 200MHz to 700MHz
• Parallel interface for programming counter and VCO frequency
multiplier and dividers
• RMS period jitter: 25ps (maximum)
• Cycle-to-cycle jitter: 65ps (maximum)
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
Pullup
VCO_SEL
Pullup
XTAL_SEL
Pulldown
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL_IN
1
2
3
4
5
6
7
8
M5
XTAL_IN
24
23
22
21
20
1
OSC
M6
M7
XTAL_OUT
TEST_CLK
XTAL_SEL
VCCA
M8
N0
S_LOAD
PLL
N1
nc
Phase Detector
S_DATA
S_CLOCK
MR
19
18
17
Pulldown
MR
0
FOUT
nFOUT
VCO
VEE
÷N
9
10 11 12 13 14 15 16
1
÷M
FOUT/2
nFOUT/2
÷2
Pulldown
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
Pulldown
Pulldown
Pulldown
TEST
Configuration Interface Logic
ICS8432-11
32 Lead LQFP
7mm x 7mm x 1.4mm package body
M5 Pullup; M[0:4, 6:8] Pulldown
Pulldown
M0:M8
N0:N1
Y Package
Top View
ICS8432CY-11 REVISION A DECEMBER 1, 2010
1
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The relationship between the VCO frequency, the input frequency
and the M divider is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock are defined as 8 ≤
M ≤ 28. The frequency out is defined as follows:
The ICS8432-11 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
25MHz clock input provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 200MHz to
700MHz. The output of the M divider is also applied to the phase
detector.
fOUT = fVCO = fXTAL x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note, that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-11 support two input
modes to program the PLL M divider and N output divider. The two
input operational modes are parallel and serial. Figure1 shows the
timing diagram for each mode. In parallel mode, the nP_LOAD input
is initially LOW. The data on inputs M0 through M8 and N0 and N1 is
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hardwired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
T1
0
T0
0
TEST Output
LOW
0
1
S_DATA, Shift Register Input
Output of M Divider
CMOS FOUT/2
1
0
1
1
SERIAL LOADING
S_CLOCK
T1 T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
S_DATA
S_LOAD
t
t
S
H
t
nP_LOAD
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
S
S_LOAD
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
ICS8432CY-11 REVISION A DECEMBER 1, 2010
2
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
9
TEST
VCC
Output
Power
Output
10
Core supply pin.
Half frequency differential output for the synthesizer.
LVPECL interface levels.
11, 12
FOUT/2, nFOUT/2
13
VCCO
Power
Output
Output supply pin.
14, 15
Differential output for the synthesizer. LVPECL interface levels.
FOUT, nFOUT
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs FOUTx to go low and the inverted outputs
17
MR
Input
Pulldown nFOUTx to go high. When Logic LOW, the internal dividers and the
outputs are enabled. Assertion of MR does not affect loaded M, N, and T
values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on
Pulldown
18
19
S_CLOCK
S_DATA
Input
Input
the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test clock inputs as the PLL reference source.
22
XTAL_SEL
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
23
TEST_CLK
Input
Input
Pulldown Single-ended test clock input. LVCMOS/LVTTL interface levels.
24,
25
XTAL_IN
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Parallel load input. Determines when data present at M8:M0 is loaded
Pulldown into M divider, and when data present at N1:N0 sets the N output divider
value. LVCMOS/LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode. When LOW,
Pullup
synthesizer is in bypass mode, when HIGH synthesizer is in PLL mode.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
3
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs
MR
nP_LOAD
M
N
S_LOAD
S_CLOCK
S_DATA Conditions
H
X
X
X
X
X
X
X
Reset. Forces true outputs LOW.
Data on M and N inputs passed directly to the M divider.
TEST output forced LOW.
L
L
L
L
↑
H
Data
Data
X
Data
Data
X
X
L
L
X
X
↑
Data is latched into input registers and remains loaded until
next LOW transition or until a serial event occurs.
X
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Data
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
↑
↓
L
L
L
X
↑
Data
Data
X
Contents of the shift register are passed to the M divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L =
H = HIGH
X = Don’t care = static DC level
LOW
↑ =
↓ =
Rising edge transition
Falling edge transition
DC = LOW or HIGH
Table 3B. Programmable VCO Frequency Function Table
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
225
250
275
•
8
9
0
0
0
0
0
1
0
0
1
10
11
•
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal frequency of 25MHz.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
4
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 3C. Programmable Output Divider Function Table
Inputs
Output Frequency (MHz)
FOUT
FOUT/2
N1
0
N0
0
N Divider Value
Minimum
200
Maximum
700
Minimum
125
Maximum
350
1
2
4
8
0
1
100
350
62.5
175
1
0
50
175
31.25
15.625
87.5
1
1
25
87.5
43.75
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
XTAL_IN
0V to VCC
Other Inputs
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
65.7°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.465
VCC
3.465
177
V
V
VCCA
VCCO
IEE
VCC – 0.17
3.135
3.3
3.3
V
mA
mA
ICCA
17
ICS8432CY-11 REVISION A DECEMBER 1, 2010
5
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
VIH
VIL
Input High Voltage
Input Low Voltage
MR, S_CLOCK,
2
V
V
-0.3
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD, M[0:4],
M[6:8], N0, N1
VCC = VIN = 3.465V
VCC = VIN = 3.465V
VCC = 3.465V, VIN = 0V
150
5
µA
µA
µA
Input
High Current
IIH
M5, XTAL_SEL, VCO_SEL
MR, S_CLOCK,
TEST_CLK, S_DATA,
S_LOAD, nP_LOAD, M[0:4],
M[6:8], N0, N1
-5
Input
Low Current
IIL
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
VCC = 3.465V, VIN = 0V
VCCO = 3.3V 5%
-150
2.6
µA
V
Output
High Voltage
VOH
VOL
Output
Low Voltage
TEST; NOTE 1
VCCO = 3.3V 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Measurement Information section. 3.3V Output Load Test Circuit diagram.
Table 4C. LVPECL DC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO – 1.4
VCCO– 2.0
0.6
Typical
Maximum
VCCO – 0.9
VCCO – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
Table 5. Input Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
MHz
TEST_CLK; NOTE 1
XTAL; NOTE 1
S_CLOCK
12
12
25
25
50
Input
fIN
Frequency
NOTE 1: For the input crystal frequency range, the M value must be set for the VCO to operate within the 200MHz to 700MHz range. Using
the minimum input frequency of 12MHz, valid values of M are 17 ≤ M ≤ 58. Using the maximum input frequency of 25MHz, valid values of M
are 8 ≤ M ≤ 28.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
6
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Table 6. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Fundamental
Frequency
12
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
AC Electrical Characteristics
Table 7. AC Characteristics, VCC = VCCO = 3.3V 5%, VEE = 0V, TA = 0°C to 70°C
Symbol
fOUT
Parameter
Test Conditions
Minimum
25
Typical
Maximum
700
Units
MHz
MHz
ps
Output Frequency
fOUT/2
tjit(cc)
tjit(per)
tsk(o)
tR / tF
Output Frequency
12.5
350
Cycle-to-Cycle Jitter; NOTE 1, 2
Period Jitter, RMS; NOTE 1, 2, 3
Output Skew; NOTE 2, 4
Output Rise/Fall Time
M, N to nP_LOAD
FOUT, N = 1
65
8.8
25
ps
45
ps
20% to 80% @ 50MHz
300
5
700
ps
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
ns
5
ns
5
ns
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
ns
5
ns
odc
Output Duty Cycle
PLL Lock Time
FOUT/2, FOUT, N > 1
46
54
10
%
tLOCK
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Jitter performance using XTAL input.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: If using the RMS Period Jitter to calculate peak-to-peak jitter, then use the typical RMS Period Jitter specification x the RMS jitter. For
example, for a bit error of 10E-12, the peak-to-peak jitter would be 8.8 x 14 = 123.2ps.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
7
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Parameter Measurement Information
2V
VOH
2V
VREF
SCOPE
V
V
CC,
Qx
VOL
1σ contains 68.26% of all measurements
CCO
V
CCA
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
LVPECL
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
nQx
Histogram
Reference Point
(Trigger Edge)
VEE
Mean Period
(First edge after trigger)
-
-1.3V 0.165V
3.3/3.3V LVPECL Output Load AC Test Circuit
Period Jitter
nFOUT
FOUT
nFOUT,
nFOUT/2
80%
80%
tR
VSWING
20%
nFOUT/2
FOUT,
FOUT/2
20%
FOUT/2
tF
tsk(o)
Output Skew
Output Rise/Fall Time
nFOUT,
nFOUT/2
nFOUT
FOUT
FOUT,
FOUT/2
tPW
tPERIOD
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
tPW
1000 Cycles
odc =
x 100%
tPERIOD
Cycle-to-Cycle Jitter
Output Duty Cycle/Pulse Width/Period
ICS8432CY-11 REVISION A DECEMBER 1, 2010
8
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Applications Information
Storage Area Networks
A variety of technologies are used for interconnection of the elements
within a SAN. The tables below list the common application
frequencies as well as the ICS8432-11 configurations used to
generate the appropriate frequency.
Table 8. Common SANs Application Frequencies
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Clock Rate
1.25GHz
Reference Frequency to SERDES (MHz)
Crystal Frequency (MHz)
125, 250, 156.25
106.25, 53.125
125, 250
25, 19.53125
FC1, 1.0625GHz
2.5GHz
25
25
Infiniband
Table 9. Configuration Details for SANs Applications
Crystal
Frequency
(MHz)
ICS8432-11
Output Frequency
to SERDES (MHz)
ICS8432-11 M & N Settings
Interconnect
Technology
M8
M7
M6
M5
M4
M3
M2
M1
M0
N1
N0
25
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
0
1
1
1
1
1
0
0
1
0
0
1
0
0
1
Gigabit Ethernet
25
156.25
156.25
53.125
106.25
125
19.53125
25
Fibre Channel 1
Infiniband
25
25
25
250
ICS8432CY-11 REVISION A DECEMBER 1, 2010
9
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8432-11 provides
separate power supplies to isolate any high frequency switching
noise from the outputs to the internal PLL. VCC, VCCA and VCCO
should be individually connected to the power supply plane through
vias, and 0.01µF bypass capacitors should be used for each pin.
Figure 2 illustrates this for a generic VCC pin and also shows that
VCCA requires that an additional 10Ω resistor along with a 10µF
bypass capacitor be connected to the VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
Figure 2. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
Crystal Inputs
TEST Output
The unused TEST output can be left floating. There should be no
trace attached.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
10
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8432-11 has been characterized with 18pF parallel resonant
crystals. The capacitor values, C1 and C2, shown in Figure 3 below
were determined using an 18pF parallel resonant crystal and were
chosen to minimize the ppm error. These same capacitor values will
tune any 18pF parallel resonant crystal over the frequency range and
other parameters specified in this data sheet. The optimum C1 and
C2 values can be slightly adjusted for different board layouts.
XTAL_IN
C1
22pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
22pF
Figure 3. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS8432CY-11 REVISION A DECEMBER 1, 2010
11
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
3.3V
Z
o = 50Ω
3.3V
+
_
Z
o = 50Ω
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
R1
50Ω
R2
50Ω
Zo = 50Ω
R1
84Ω
R2
84Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
ICS8432CY-11 REVISION A DECEMBER 1, 2010
12
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Layout Guideline
Figure 6A shows an example of ICS8432-11 application schematic.
In this example, the device is operated at VCC = VCCO = 3.3V. The
device is driven by a crystal input source. The 18pF parallel resonant
25MHz crystal is used. The C1 and C2 = 22pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy. For the
LVPECL output drivers, only two termination examples are show in
this schematic. Additional termination approaches are shown in the
LVPECL Termination Application Note.
C1
25MHzX1
18pF
22pF
U1
VCC
C2
22pF
M5
M5
M5
M5
M5
M5
M5
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
R7
10
M5
M6
M7
M8
N0
N1
nc
XTAL_IN
TEST_CLK
XTAL_SEL
VCCA
TEST_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
S_LOAD
S_DATA
S_CLOCK
MR
C11
C16
0.01u
10u
VEE
VCC=3.3V
VCCO=3.3V
VCC
R1
R3
125
125
Zo = 50 Ohm
TL1
+
-
C14
C15
0.01u
0.01u
Zo = 50 Ohm
TL2
Logic Control Input Examples
R2
84
R4
84
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VCC
VCC
RU1
1K
RU2
Not Install
Zo = 50 Ohm
FOUT/2
+
-
To Logic
Input
To Logic
Input
pins
Zo = 50 Ohm
nFOUT/2
pins
RD1
RD2
1K
Not Install
R10
50
R11
50
R12
50
Optional
Y-Termination
Figure 6A. ICS8432-11 Schematic of Recommended Layout
ICS8432CY-11 REVISION A DECEMBER 1, 2010
13
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
The following component footprints are used in this layout example.
All the resistors and capacitors are size 0603.
• The differential 50Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
Power and Grounding
Place the decoupling capacitors C14 and C15, as close as possible
to the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
• Keep the clock trace on the same layer. When ever possible,
avoid any vias on the clock traces. Placement of vias on the
traces can affect the trace characteristic impedance and hence
degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
• Make sure no other signal traces are routed between the
clock trace pair.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VCCA pin as possible.
• The matching termination resistors should be located as close to
the receiver input pins as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the clock
signal is less tolerant to poor signal integrity than other signals. Any
ringing on the rising or falling edge or excessive ring back can cause
system failure. The shape of the trace and the trace delay might be
restricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
Crystal
The crystal X1 should be located as close as possible to the pins 24
(XTAL_IN) and 25 (XTAL_OUT). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
C15
C14
TL1
R2
R1
TL1, TL2 are 50 Ohm traces and
equal length
Figure 6B. PCB Board Layout for ICS8432-11
ICS8432CY-11 REVISION A DECEMBER 1, 2010
14
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8432-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 177mA = 613.3mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 613.3mW + 60mW = 673.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 65.7°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.673W * 65.7°C/W = 114.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 10. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
65.7°C/W
55.9°C/W
52.4°C/W
ICS8432CY-11 REVISION A DECEMBER 1, 2010
15
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCCO – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS8432CY-11 REVISION A DECEMBER 1, 2010
16
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Reliability Information
Table 11. θJA vs. Air Flow Table for a 32 Lead LQFP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
65.7°C/W
55.9°C/W
52.4°C/W
Transistor Count
The transistor count for ICS8432-11 is: 3765
ICS8432CY-11 REVISION A DECEMBER 1, 2010
17
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 12. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
D1 & E1
D2 & E2
e
L
0.45
0°
0.75
7°
θ
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS8432CY-11 REVISION A DECEMBER 1, 2010
18
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Ordering Information
Table 13. Ordering Information
Part/Order Number
8432CY-11
8432CY-11T
8432CY-11LF
8432CY-11LFT
Marking
Package
32 Lead LQFP
32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8432CY-11
ICS8432CY-11
ICS8432CY11L
ICS8432CY11L
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS8432CY-11 REVISION A DECEMBER 1, 2010
19
©2010 Integrated Device Technology, Inc.
ICS8432-11 Data Sheet
700MHz/350MHz, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明