844246BGIT [IDT]
Clock Generator;
| 型号： | 844246BGIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总16页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
ICS844246I
GENERAL DESCRIPTION
FEATURES
The ICS844246I is a Crystal-to-LVDS Clock
• Six LVDS outputs
ICS
HiPerClockS™
Synthesizer/Fanout Buffer designed for Fibre
Channel and Gigabit Ethernet applications and is
a member of the HiperClockS™ family of High
Performance Clock Solutions from IDT. The output
• Crystal oscillator interface
• Output frequency range: 53.125MHz to 333.3333MHz
• Crystal input frequency range: 25MHz to 33.333MHz
frequency can be set using the frequency select pins and a
25MHz crystal for Ethernet frequencies, or a 26.5625MHz
crystal for a Fibre Channel. The low phase noise character-
istics of the ICS844246I make it an ideal clock for these
• RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.39ps (typical)
• Full 3.3V or 3.3V core, 2.5V output supply mode
• -40°C to 85°C ambient operating temperature
demanding applications.
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
SELECT FUNCTION TABLE
Inputs
Function
FB_SEL N_SEL1 N_SEL0 M Divide N Divide
M/N
10
5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
20
20
20
20
24
24
24
24
2
4
5
4
8
2.5
8
3
4
6
6
4
12
2
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
VDDO
1
24
23
22
Q3
2
3
VDDO
nQ2
nQ3
Q4
nQ0
Pullup
PLL_BYPASS
4
Q2
nQ1
Q1
nQ0
nQ4
Q5
nQ5
N_SEL1
GND
21
20
19
18
17
16
15
14
13
5
6
7
8
Q1
1
nQ1
Q0
Output
Divider
XTAL_IN
9
PLL_BYPASS
VDDA
GND
OSC
PLL
Q2
0
10
11
12
N_SEL0
XTAL_OUT
XTAL_IN
XTAL_OUT
VDD
FB_SEL
nQ2
Q3
Feedback
Divider
ICS844246I
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.90mm
body package
nQ3
Pulldown
FB_SEL
Q4
G Package
Top View
Pullup
nQ4
N_SEL1
Pullup
N_SEL0
Q5
nQ5
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
VDDO
Type
Description
Power
Output
Output
Output
Output supply pins.
3, 4
nQ2, Q2
nQ1, Q1
nQ0, Q0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
5, 6
7, 8
Selects between the PLL and crystal inputs as the input to the dividers.
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
9
PLL_BYPASS
Input
Pullup
10
11
12
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
FB_SEL
Input Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels.
13,
14
15,
18
XTAL_IN,
XTAL_OUT
N_SEL0
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Input
Pullup
Output frequency select pin. LVCMOS/LVTTL interface levels.
N_SEL1
16, 17
19, 20
21, 22
23, 24
GND
Power supply ground.
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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PRELIMINARY
CRYSTAL FUNCTION TABLE
Inputs
Function
VCO (MHz)
XTAL (MHz) FB_SEL N_SEL1 N_SEL0
M
20
20
20
20
24
24
24
24
20
24
24
24
24
20
20
20
20
20
20
20
20
20
20
20
20
N
2
Output (MHz)
250
25
25
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
500
500
4
125
25
500
5
100
25
500
8
62.5
25
600
3
200
25
600
4
150
25
600
6
100
25
600
12
5
50
26.5625
26.5625
26.5625
26.5625
26.5625
30
531.25
637.5
637.5
637.5
637.5
600
106.25
212.5
159.375
106.25
53.125
300
3
4
6
12
2
30
600
4
150
30
600
5
120
30
600
8
75
31.25
31.25
31.25
31.25
33.3333
33.3333
33.3333
33.3333
625
2
312.5
156.25
125
625
4
625
5
625
8
78.125
333.3333
166.6667
133.3333
83.3333
666.6667
666.6667
666.6667
666.6667
2
4
5
8
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θ
24 Lead TSSOP, EPad
JA
32.1°C/W (0 mps)
-65°C to 150°C
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.06
3.135
3.3
3.3
3.465
V
120
6
mA
mA
mA
IDDA
IDDO
135
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.06
2.375
3.3
2.5
2.625
V
120
6
mA
mA
mA
IDDA
IDDO
120
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
FB_SEL
VDD = VIN = 3.465V
150
µA
IIH
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
5
µA
µA
µA
FB_SEL
-5
IIL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
-150
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
387
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.29
50
Δ VOS
VOS Magnitude Change
mV
NOTE: Please refer to Parameter Measurement Information for output information.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
379
Maximum Units
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
mV
mV
V
Δ VOD
VOS
40
1.24
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
25
33.333
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pf parallel resonant crystal.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.39
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
355
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
53.125
333.33
MHz
125MHz, Integration Range:
1.875MHz - 20MHz
tjit(Ø)
RMS Phase Jitter (Random)
0.38
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
TBD
380
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
tLOCK
1
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
TYPICAL PHASE NOISE AT 125MHZ @ 3.3V
0
-10
-20
Gb Ethernet Filter
-30
-40
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.39ps
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
Raw Phase Noise Data
-150
-160
-170
-180
-190
Phase Noise Result by adding
Gb Ethernet Filter to raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
+ +
Qx
SCOPE
VDDA
Qx
VDD
VDDO
,
–
VDDO
3.3V 5ꢀ
LVDS
VDDA
POWER SUPPLY
POWER
SUPPLY
+
Float GND –
LVDS
Float GND
nQx
nQx
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0:nQ5
nQx
Qx
Q0:Q5
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
out
80ꢀ
tF
80ꢀ
➤
DC Input
LVDS
VSWING
20ꢀ
Clock
20ꢀ
Outputs
out
VOS/Δ VOS
tR
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
VDD
➤
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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ICS844246BGI REV. A NOVEMBER 14, 2007
Reference Document: JEDEC Publication 95, MO-153
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
3.3V
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
VDD
.01μF
.01μF
10Ω
mance, power supply isolation is required. The ICS844246I pro-
vides separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDA, and VDDO should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Fig-
ure 1 illustrates this for a generic V pin and also shows that
VDDA requires that an additional10Ω CrCesistor along with a 10µF
bypass capacitor be connected to the VDDA pin.
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS Outputs
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
CRYSTAL INPUT INTERFACE
below were determined using an 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
The ICS844246 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the
power rail and to reduce noise. This configuration requires that
the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50Ω applications, R1 and R2 can be 100Ω.
This can also be accomplished by removing R1 and making R2
50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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Reference Document: JEDEC Publication 95, MO-153
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
SOLDER
EXPOSED HEAT SLUG
PIN
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
GROUND PLANE
PIN PAD
THERMAL VIA
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844246I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844246I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
DD
•
•
Power (core) = V
* (I
+ I
) = 3.465V * (120mA + 6mA) = 436.59mW
DDA_MAX
MAX
DD_MAX
DD_MAX
Power (outputs) = V
* I
= 3.465V * 135mA = 467.78mW
DDO_MAX
MAX
DDO_MAX
Total Power
= 436.59mW + 467.78mW = 904.37mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ * Pd_total + TA
JA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.904W * 32.1°C/W = 114°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 24-LEAD TSSOP, E-PAD, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
24.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
12
ICS844246BGI REV. A NOVEMBER 14, 2007
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP, E-PAD
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
24.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
TRANSISTOR COUNT
The transistor count for ICS844246I is: 3887
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
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ICS844246BGI REV. A NOVEMBER 14, 2007
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP, E-PAD
TABLE 9. PACKAGE DIMENSIONS
Millimeters
Nominal
SYMBOL
Minimum
Maximum
N
A
24
--
1.10
0.15
0.95
0.30
0.25
0.20
0.16
7.90
A1
A2
b
0.05
0.85
0.19
0.19
0.09
0.09
7.70
0.90
0.22
b1
c
c1
D
0.127
7.80
E
6.40 BASIC
4.40
E1
e
4.30
0.50
4.50
0.65 BASIC
0.60
L
0.70
5.0
3.2
8°
P
P1
α
0°
aaa
bbb
0.076
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
14
ICS844246BGI REV. A NOVEMBER 14, 2007
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS844246BGI
Marking
Package
Shipping Packaging
tube
Temperature
ICS844246BGI
ICS844246BGI
ICS844246BGIL
ICS844246BGIL
24 Lead TSSOP, E-Pad
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS844246BGIT
ICS844246BGILF
ICS844246BGILFT
24 Lead TSSOP, E-Pad
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP, E-Pad
24 Lead "Lead-Free" TSSOP, E-Pad
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
15
ICS844246BGI REV. A NOVEMBER 14, 2007
ICS844246I
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
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Integrated Device Technology
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435 Orchard Road
Europe
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Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
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844246BGLFT
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