8520DYI-02T [IDT]
Clock Driver, 8520 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 MM HEIGHT, MS-026ABC-HD, TQFP-48;
| 型号： | 8520DYI-02T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 8520 Series, 16 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1 MM HEIGHT, MS-026ABC-HD, TQFP-48 驱动 逻辑集成电路 |
| 文件： | 总14页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8520I-02 is a low skew, high performance • Sixteen differential LVHSTL compatible outputs
1-to-16 Differential-to-LVHSTL Fanout Buffer.The ICS8520I-
02 has 1 differential clock input pair. The CLK, nCLK pair
can accept most standard differential input levels.
each with the ability to drive 50Ω to ground
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8520I-02 ideal for
nterfacing to today’s most advanced microprocessor and
static RAMs.
• Maximum output frequency: 500MHz
• Translates single ended input levels to LVHSTL
levels with resistor bias nCLK input
• VOH: 1.3V (maximum)
• 40% of VOH ≤ Vcrossover ≤ 60% of VOH
• Output skew: 110ps (maximum)
• Part-to-Part skew: 450ps (maximum)
• 3.3V core, 1.8V output operating supply voltages
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
Q0
Q15
CLK
VDDO
nQ0
Q0
VDDO
Q11
nQ11
Q10
nQ10
GND
Q9
1
36
35
34
33
32
31
30
29
28
27
26
25
nQ0
nQ15
2
Q1
nQ1
Q14
nQ14
3
4
nQ1
Q1
5
Q2
nQ2
Q13
nQ13
6
ICS8520I-02
GND
nQ2
Q2
7
Q3
nQ3
Q12
nQ12
nQ9
Q8
8
9
Q11
nQ11
Q4
nQ4
nQ3
Q3
nQ8
VDDO
VDD
10
11
12
Q10
nQ10
VDDO
Q5
nQ5
13 14 15 16 17 18 19 20 21 22 23 24
Q9
nQ9
Q6
nQ6
Q8
nQ8
Q7
nQ7
48-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm body package
Y Package
Top View
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 14, 24,
25, 35, 38, 48
VDDO
Power
Output supply pins.
2, 3
4, 5
Q11, nQ11
Q10, nQ10
GND
Output
Output
Power
Output
Output
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply ground.
6, 19, 30, 43
7, 8
Q9, nQ9
Q8, nQ8
VDD
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Power supply pins.
9, 10
12, 13
15, 16
17, 18
20, 21
22, 23
26, 27
28, 29
31, 32
33, 34
36
Q7, nQ7
Q6, nQ6
Q5, nQ5
Q4, nQ4
Q3, nQ3
Q2, nQ2
Q1, nQ1
Q0, nQ0
CLK
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface level
Differential output pair. LVHSTL interface level
Pulldown Non inverting differential clock input.
37
nCLK
Input
Pullup
Inverting differential clock input.
39, 40
41, 42
44, 45
46, 47
Q15, nQ15
Q14, nQ14
Q13, nQ13
Q12, nQ12
Output
Output
Output
Output
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
Differential output pair. LVHSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK
nCLK
Q0:Q15
LOW
nQ0:nQ15
0
1
HIGH
LOW
HIGH
LOW
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information Section, "Wiring the Differential input to accept single ended levels".
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
27.6°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
VDDO
IDD
Power Supply Voltage
3.135
3.3
3.465
2.0
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
1.6
1.8
190
10
mA
µA
IDDO
TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
VIN = 0V, VDD = 3.465V
VIN = 0V, VDD = 3.465V
Minimum
Typical
Maximum Units
CLK
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nCLK
CLK
-5
IIL
Input Low Current
nCLK
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Voltage Range;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
0.9
1.3
V
Output Low Voltage;
NOTE 1
VOL
VOX
0
0.4
V
V
Output Crossover Voltage
40% x (VOH–VOL) + VOL
60% x (VOH–VOL) + VOL
NOTE 1: Outputs terminated with 50Ω to ground.
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
500
1.6
Units
MHz
ns
fMAX
Output Frequency
tPD
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
1.1
1.35
tsk(o)
tsk(pp)
110
450
900
600
52
ps
Part-to-Part Skew; NOTE 3, 4
ps
ƒ ≤ 300MHz
ƒ> 300MHz
200
200
48
ps
tR/tF
Output Rise/Fall Time
ps
IJ 133MHz
%
odc
Output Duty Cycle
133 < ƒ ≤ 300MHz
ƒ> 300MHz
46
54
%
45
55
%
NOTE 1: Measured from the differential input crossing point to the differential ouput crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V 5%
1.8V 0.2V
VDD
SCOPE
VDD
Qx
VDDO
nCLK
CLK
VPP
VCMR
Cross Points
HSTL
GND
nQx
GND
0V
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
Qx
PART 1
nQx
Qy
nQy
PART 2
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
CLK
80%
80%
tR
VSWING
20%
Clock
Outputs
nQ0:nQ15
20%
tF
Q0:Q15
tPD
OUTPUT RISE/FALL TIME
nQ0:nQ15
PROPAGATION DELAY
Q0:Q15
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
APPLICATION INFORMATION
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLKx /nCLKx accepts LVDS, LVPECL, LVHSTL, SSTL, consult with the vendor of the driver component to confirm
HCSL and other differential signals. Both VSWING and VOH the driver termination requirements. For example in Figure
must meet the VPP and VCMR input requirements. Figures 1A 1A, the input termination applies for LVHSTL drivers. If you
to 1E show interface examples for the CLKx/ are using an LVHSTL driver fromanother vendor, use their
nCLKx input driven by the most common driver types. The termination recommendation.
input interfaces suggested here are examples only. Please
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 1A. CLK/nCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 1B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 1C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 1D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 1E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
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ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8520I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8520I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 190mA = 658.4mW
Power (outputs)MAX = 32.6mW/Loaded Output pair
If all outputs are loaded, the total power is 16 * 32.6mW = 521.6mW
Total Power_MAX (3.465V, with all outputs switching) = 658.4mW + 521.6mW = 1180mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 22.6°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.18W * 22.6°C/W = 111.7°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 48-PIN TQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
27.6°C/W
22.6°C/W
20.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVHSTL output driver circuit and termination are shown in Figure 2.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 2. LVHSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DDO_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DDO_MAX
OL_MAX
Pd_H = (0.9V/50Ω) * (2V - 0.9V) = 19.8mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW
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LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LEAD TQFP, E-PAD
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC StandardTest Boards
27.6°C/W
22.6°C/W
20.7°C/W
TRANSISTOR COUNT
The transistor count for ICS8520I-02 is: 1563
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REV.B NOVEMBER 30, 2010
ICS8520I-02
LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD TQFP, E-PAD
-HD VERSION
HEAT SLUG DOWN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABC - HD
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
48
--
A
--
1.20
0.15
1.05
0.27
0.20
A1
0.05
0.95
0.17
0.09
--
A2
1.00
0.22
b
c
D
9.00 BASIC
7.00 BASIC
5.50 BASIC
9.00 BASIC
7.00 BASIC
5.50 BASIC
0.5 BASIC
0.60
D1
D2
E
E1
E2
e
L
θ
0.45
0°
0.75
7°
ccc
--
--
0.08
7.00
D3 & E3
2.00
Reference Document: JEDEC Publication 95, MS-026
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ICS8520I-02
LOW SKEW, 1-TO-16
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TABLE 9. ORDERING INFORMATION
Part/Order Number
8520DYI-02
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8520DYI-02
ICS8520DYI-02
ICS8520DI02L
ICS8520DI02L
48 Lead TQFP, E-Pad
8520DYI-02T
48 Lead TQFP, E-Pad
1000 tape & reel
tray
8520DYI-02LF
8520DYI-02LFT
48 Lead "Lead-Free" TQFP, E-Pad
48 Lead TQFP, E-Pad
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS8520I-02
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DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T2
2
10
1
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Corrected Package Dimensions and Package Outline.
Added lead-free bullet.
B
11/19/04
7
9
12
Added Recommendations for Unused Input and Output Pins.
Corrected Power Considerations, Power Dissipation calculation.
Ordering Information Table - added lead-free part number and note.
Updated layout of datasheet.
B
B
11/16/05
11/30/10
T9
T9
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column. Added LF marking.
Added Contact Page.
12
14
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We’ve Got Your Timing Solution.
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San Jose, CA 95138
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Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
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