853111AV-01LF [IDT]
Low Skew Clock Driver, 853111 Series, 9 True Output(s), 0 Inverted Output(s), PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-018, LCC-28;
| 型号： | 853111AV-01LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853111 Series, 9 True Output(s), 0 Inverted Output(s), PQCC28, 11.60 X 11.40 MM, 4.10 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MS-018, LCC-28 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS853111-01 is a low skew, high perfor- • 9 differential 3.3V LVPECL / ECL outputs
ICS
HiPerClockS™
mance 1-to-9 Differential-to-3.3V LVPECL/ECL
• 1 differential LVPECL input pair
Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from IDT. The PCLK, nPCLK
• PLCK, nPLCK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
pair can accept LVPECL, CML and SSTL differential input
levels.The ICS853111-01 is characterized to operate from
a 3.3V power supply. Guaranteed output and part-to-part
skew characteristics make the ICS853111-01 ideal for
those clock distribution applications demanding well
defined performance and repeatability.
• Maximum output frequency: >2GHz (typical)
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.03ps (typical)
• Output skew: 35ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 675ps (maximum)
• LVPECL mode operating voltage supply range:
VCC = 3V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PCLK
nPCLK
Q1
25 24 23 22 21 20 19
nQ1
VEE
nc
26
27
28
Q3
18
17
16
Q2
nQ2
nQ3
Q4
PCLK
Q3
nQ3
ICS853111-01
VCC
nPCLK
VBB
1
2
3
VCCO
nQ4
Q5
15
14
13
12
Q4
nQ4
VBB
Q5
nQ5
nQ5
nc
4
5
6
7
8
9
10 11
Q6
nQ6
Q7
nQ7
28-Lead PLCC
11.6mm x 11.4mm x 4.1mm package body
Q8
nQ8
V Package
TopView
853111AV-01
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Input
Core supply pin.
Pullup/
Pulldown1
2
nPCLK
Inverting differential LVPECL clock input. Bias to VCC/2 w/no input.
3
4, 27
5, 6
VBB
Output
Unused
Output
Output
Power
Bias voltage.
nc
No connect.
nQ8, Q8
nQ7, Q7
VCCO
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
7, 9
8, 15, 22
10, 11
12, 13
14, 16
17, 18
19, 20
21, 23
24, 25
26
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
Output
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pin.
nQ1, Q1 Output
nQ0, Q0
VEE
Output
Power
Input
28
PCLK
Pulldown Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
1
RPULLUP
50
75
50
KΩ
RPULLDOWN
Input Pulldown Resistor
Input Pulldown Resistor
KΩ
KΩ
1
RPULLDOWN
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (LVECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
Negative SupplyVoltage,VEE
Inputs, VI (LVPECL mode)
Inputs, VI (LVECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
V
BB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature, TSTG -65°C to 150°C
PackageThermal Impedance, θJA 37.8°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 3A. LVPECL POWER SUPPLY DC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V
Symbol Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum Units
VCC
VCCO
IEE
Core Supply Voltage
3.8
3.8
75
V
V
Output Supply Voltage
Power Supply Current
3.0
3.3
mA
Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Typ
Max
Min
Max
2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365
1.405 1.545 1.68 1.425 1.52 1.615 1.44 1.535 1.63
V
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
2.075
1.43
1.86
150
2.36 2.075
1.765 1.43
2.36 2.075
1.765 1.43
2.36
1.765
1.98
VIL
1.98
1.86
150
1.98
1.86
150
VBB
VPP
800
1200
800
1200
800
1200
Input High Voltage
Common Mode Range; NOTE 3, 4
1.2
3.3
1.2
3.3
1.2
3.3
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
Input
-150
-150
µA
IIL
PCLK, nPCLK
Low Current
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
TABLE 3C. ECL POWER SUPPLY DC CHARACTERISTICS, VCC = 0V; VEE = -3V TO -3.8V
Symbol Parameter
Test Conditions
Minimum
Typical
-3.3
Maximum Units
VEE
IEE
Supply Voltage
Power Supply Current
-3.0
-3.8
V
55
mA
Table 3D. ECL DC Characteristics, VCC = 0V; VEE = -3V to -3.8V
-40°C
25°C
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
Typ Max
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
Typ Max
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.32
1200
-1.005
-1.78
-0.93
-1.685
-0.94
-1.535
-1.32
1200
-0.97
-0.935
-1.67
-0.94
-1.535
-1.32
1200
V
V
V
V
V
V
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
-1.765
VIL
VBB
VPP
800
800
800
Input High Voltage
Common Mode Range; NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
IIH
Input
150
150
150
µA
PCLK, nPCLK
High Current
Input
-150
-150
-150
µA
IIL
PCLK, nPCLK
Low Current
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4. AC CHARACTERISTICS, VCC = 3V TO 3.8V; VEE = 0V OR VCC = 0V; VEE = -3V TO -3.8V
-40°C
Min Typ
25°C
Max Min Typ
85°C
Symbol Parameter
Units
Max Min Typ
Max
fMAX
tpLH
Output Frequency
>2
>2
>2
GHz
ps
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
350 500
650
750
385 525
675
760
410 350
700
785
tpHL
450 600
20
480 620
20
515 650
20
ps
tsk(o)
Output Skew; NOTE 2, 4
35
35
35
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
200
200
200
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tjit
0.03
0.03
0.03
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
90
200
315
100 203
310
95 210
300
All parameters measured at f ≤ 1GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853111AV-01
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REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
Qx
nPCLK
PCLK
LVPECL
VPP
VCMR
Cross Points
nQx
VEE
-1.3V 0.3V
V
EE
DIFFERENTIAL INPUT LEVEL
OUTPUT LOAD ACTEST CIRCUIT
nQx
PART 1
Qx
nQx
Qx
nQy
PART 2
Qy
nQy
tsk(pp)
Qy
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nPCLK
PCLK
80%
tF
80%
tR
VSWING
Clock
20%
20%
Outputs
nQ0:nQ8
Q0:Q8
tPD
OUTPUT RISE/FALLT IME
PROPAGATION DELAY
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
negative input. The C1 capacitor should be located as close
as possible to the input pin.
Figure 1 shows an example of the differential input that can
be wired to accept single ended levels.The reference voltage
level VBB generated from the device is connected to the
VCC
C1
0.1u
CLK_IN
PCLK
VBB
nPCLK
FIGURE 1. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 2A and 2B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 3A to 3F show interface the vendor of the driver component to confirm the driver ter-
mination requirements.
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
R2
50
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
R1
100
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
C1
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
VBB
PCLK
C2
nPCLK
nPCLK
HiPerClockS
Input
PCLK/nPCLK
LVPECL
R5
100 - 200
R6
100 - 200
R1
50
R2
50
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
R4
120
120
C1
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
VBB
C2
nPCLK
Zo = 50 Ohm
nPCLK
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 3F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
853111AV-01
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ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
SCHEMATIC EXAMPLE
This application note provides general design guide using example of the ICS853111-01 LVPECL clock buffer. In this
ICS853111-01 LVPECL buffer. Figure 4 shows a schematic example, the input is driven by an LVPECL driver.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
VCC
C6 (Option)
0.1u
R3
50
VCC
Zo = 50 Ohm
Zo = 50 Ohm
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
R4
1K
3.3V LVPECL
R9
50
R10
50
U1
C8 (Option)
0.1u
R11
50
ICS853111
VCC
Zo = 50
+
-
VCC=3.3V
Zo = 50
(U1-9)
(U1-16)
(U1-25) (U1-32) (U1-1)
VCC
R8
50
R7
50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C7 (Option)
0.1u
R13
50
FIGURE 4. EXAMPLE ICS853111-01 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
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LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 75mA = 285mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 9 * 30.94mW = 278.5mW
Total Power_MAX (3.8V, with all outputs switching) = 285mW + 278.5mW = 563.5mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W perTable 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.564W * 31.1°C/W = 102°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION
θ by Velocity (Linear Feet per Minute)
JA
0
200
31.1°C/W
500
28.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 5. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.67V
OL_MAX
CCO_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853111AV-01
11
REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 28 LEAD PLCC
θ byVelocity (Linear Feet per Minute)
JA
0
200
31.1°C/W
500
28.3°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111-01 is: 265
Pin compatible with MC100LVE111
853111AV-01
12
REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
28
4.19
2.29
4.57
3.05
A1
A2
b
1.57
2.11
0.33
0.53
c
0.19
0.32
D
12.32
11.43
4.85
12.57
11.58
5.56
D1
D2
E
12.32
11.43
4.85
12.57
11.58
5.56
E1
E2
Reference Document: JEDEC Publication 95, MS-018
853111AV-01
13
REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS853111AV-01
ICS853111AV-01T
ICS853111AV-01LF
ICS853111AV-01LFT
ICS853111AV-01
ICS853111AV-01
ICS853111AV01L
ICS853111AV01L
28 Lead PLCC
Tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
28 Lead PLCC
500 Tape & Reel
Tube
28 Lead "Lead-Free" PLCC
28 Lead "Lead-Free" PLCC
500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the pat number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by
IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
853111AV-01
14
REV.A NOVEMBER 14, 2007
ICS853111-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
1
5
Description of Change
Features Section - added Lead-Free bullet.
Added Additive Phase jitter section.
Date
4/25/05
11/14/07
A
T8
14
Ordering Information Table - Added Lead-free marking
853111AV-01
15
REV.A NOVEMBER 14, 2007
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