853111AY-02LFT [IDT]
Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026, TQFP-32;
| 型号： | 853111AY-02LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026, TQFP-32 驱动 逻辑集成电路 |
| 文件： | 总18页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS853111-02 is a low skew, high per- • Ten differential 2.5V/3.3V LVPECL / ECL outputs
ICS
HiPerClockS™
formance 1-to-10 Differential-to-2.5V/3.3V
• Two selectable differential input pairs
LVPECL/ECL Fanout Buffer and a member
of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
ICS853111-02 is characterized to operate from either
a 2.5V or a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS853111-
02 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
• Maximum output frequency: 3.2GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Output skew: 25ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 680ps (typical)
• Jitter, RMS: < 0.03ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PCLK0
nPCLK0
0
1
PCLK1
nPCLK1
Q1
nQ1
24 23 22 21 20 19 18 17
VCCO
nQ2
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q7
Q2
nQ2
nQ7
Q8
CLK_SEL
VBB
Q3
nQ3
nQ1
Q1
ICS853111-02
nQ8
Q9
Q4
nQ4
nQ0
Q0
nQ9
Q5
nQ5
VCCO
VCCO
1
2
3
4
5
6
7
8
Q6
nQ6
Q7
nQ7
Q8
nQ8
32-LeadTQFP
7mm x 7mm x 1.0mm package body
Y Package
TopView
Q9
nQ9
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853111AY-02
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REV.A JANUARY 10, 2006
1
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Core supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
2
CLK_SEL Input
Pulldown
Pulldown
3
4
PCLK0
Input
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK0
Input Pullup/Pulldown
5
6
VBB
Output
Bias voltage.
PCLK1
Input
Pulldown
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
7
nPCLK1
Input Pullup/Pulldown
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VEE
Power
Power
Negative supply pin.
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN Input Pulldown Resistor
75
kΩ
Pullup/Pulldown Resistors
50
kΩ
RVCC/
2
TABLE 3A. CLOCK INPUT FUNCTION TABLE
TABLE 3B. CONTROL INPUT
FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Inputs
PCLKx nPCLKx Q0:Q9 nQ0:Q9
CLK_SEL Selected Source
0
1
1
0
LOW
HIGH
LOW
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
0
1
PCLK0, nPCLK0
PCLK1, nPCLK1
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
1
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
Biased;
NOTE 1
Biased;
NOTE 1
0
1
Single Ended to Differential
Single Ended to Differential
Inverting
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
853111AY-02
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REV.A JANUARY 10, 2006
2
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VCC
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
4.6V (LVPECL mode, VEE = 0)
-4.6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
VBB Sink/Source, IBB
0.5mA
OperatingTemperature Range, TA -40°C to +85°C
StorageTemperature,TSTG -65°C to 150°C
PackageThermal Impedance, θJA 49.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
3.8
85
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
Typ Max Min
85°C
Typ
Symbol Parameter
Units
Min Typ Max
Min
2.225
1.425
2.075
1.43
Max
VOH
VOL
VIH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
2.175 2.275
1.405 1.545
2.075
2.38
1.68
2.36
1.765
1.98
1200
2.295
1.52
2.37
1.615
2.36
2.295
1.44
2.075
1.43
1.86
150
2.33
2.365
1.63
V
V
V
V
V
V
1.535
2.36
VIL
1.43
1.765
1.98
1.765
1.98
VBB
VPP
1.86
1.86
150
1.2
800
150
800
1200
800
1200
Input High Voltage
Common Mode Range; NOTE 3, 4
VCMR
IIH
3.3
1.2
3.3
1.2
3.3
V
PCLK0, PCLK1
Input High Current
150
150
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
IIL
-150
-150
-150
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111AY-02
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REV.A JANUARY 10, 2006
3
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
85°C
Typ
Symbol Parameter
Units
Min Typ Max
Min Typ Max Min
Max
1.565
0.83
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Peak-to-Peak Input Voltage
1.375 1.475
0.605 0.745
1.275
1.58
0.88
1.425 1.495
1.57
0.815
1.56
1.495
0.64
1.275
0.63
150
1.53
V
V
V
V
V
0.625
1.275
0.63
0.72
800
0.735
1.56
-0.8
0.63
0.965
1200
0.965
1200
0.965
1200
VPP
150
1.2
800
150
800
Input High Voltage
Common Mode Range; NOTE 2, 3
VCMR
IIH
2.5
1.2
2.5
1.2
2.5
V
PCLK0, PCLK1
Input High Current
150
150
150
µA
nPCLK0, nPCLK1
PCLK0, PCLK1
Input Low Current
IIL
-150
-150
-150
µA
nPCLK0, nPCLK1
Input and output parameters vary 1:1 with VCC. VEE can vary +0.125V to -1.3V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V
-40°C
Typ Max
25°C
Typ Max
85°C
Typ Max
Symbol Parameter
Units
Min
-1.125
-1.895
-1.225
-1.87
Min
-1.075
-1.875
-1.225
-1.87
Min
-1.005
-1.86
-1.025
-1.755
-0.92
-1.62
-0.94
-1.535
-1.005
-1.78
-0.93
-1.685
-0.94
-0.97
-0.935
-1.67
V
V
V
V
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
-1.765
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
-1.225
-1.87
-0.94
-1.535
-1.535
Output Voltage Reference;
NOTE 2
-1.486
150
-1.386
1200
-1.486
150
-1.386
1200
-1.486
150
-1.386
1200
V
V
VBB
VPP
800
800
800
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range;
NOTE 3, 4
VEE+1.2V
0
VEE+1.2V
0
VEE+1.2V
0
V
VCMR
Input
PCLK0, PCLK1
150
150
150
µA
µA
IIH
IIL
High Current nPCLK0, nPCLK1
Input PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-150
-150
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
853111AY-02
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REV.A JANUARY 10, 2006
4
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V
-40°C 25°C
Min Typ Max Min Typ
85°C
Max Min Typ
Symbol Parameter
Units
Max
3.2
fMAX
Output Frequency
3.2
750
37
3.2
790
37
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
600 680
650 725
690 790
890
37
tsk(o)
tsk(pp)
25
85
25
85
25
85
ps
Part-to-Part Skew; NOTE 3, 4
225
225
225
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
0.03
0.03
ps
ps
tR/tF
Output Rise/Fall Time
20% to 80%
60
200
325
100 200
280
130 200
270
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853111AY-02
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REV.A JANUARY 10, 2006
5
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Additive Phase Jitter at
155.52MHz = 0.03ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
853111AY-02
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REV.A JANUARY 10, 2006
6
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
,
Qx
VCCO
nCLK0, nCLK1
VPP
LVPECL
VEE
VCMR
Cross Points
CLK0, CLK1
nQx
VEE
-0.375V to -1.8V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
PART 1
Qx
nQx
Qx
nQy
nQy
PART 2
Qy
Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0,
nCLK1
80%
tF
80%
CLK0,
CLK1
VSWING
20%
nQ0:nQ9
Clock
20%
Outputs
tR
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
853111AY-02
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REV.A JANUARY 10, 2006
7
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
Figure 2A shows an example of the differential input that
can be wired to accept single ended LVCMOS levels. The
reference voltage level VBB generated from the device is
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
VCC
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that
can be wired to accept single ended LVPECL levels. The
reference voltage level VBB generated from the device is
connected to the negative input. The C1 capacitor should
be located as close as possible to the input pin.
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
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853111AY-02
REV.A JANUARY 10, 2006
8
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 3A to 3E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 3A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
CLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 3E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853111AY-02
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REV.A JANUARY 10, 2006
9
ICS853111-02
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVPECL OUTPUT
PCLK/nPCLK INPUT:
All unused LVPECL outputs can be left floating. We
For applications not requiring the use of a differential input,
both the PCLK and nPCLK pins can be left floating. Though recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
not required, but for additional protection, a 1kΩ resistor can
be tied from PCLK to ground.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi- ance techniques should be used to maximize operating
nation for LVPECL outputs. The two different layouts men- frequency and minimize signal distortion. Figures 4A and
tioned are recommended only as guidelines.
4B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and
clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUTT ERMINATION
FIGURE 4B. LVPECL OUTPUTTERMINATION
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Integrated
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for close to ground level. The R3 in Figure 5B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 5C.
minating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVERT ERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECLTERMINATION EXAMPLE
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Integrated
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SCHEMATIC EXAMPLE
This application note provides general design guide using ample, the input is driven by an LVPECL driver.CLK_SEL is set
ICS853111-02 LVPECL buffer. Figure 6 shows a schematic ex- at logic high to select PCLK0/nPCLK0 input.
ample of the ICS853111-02 LVPECL clock buffer. In this ex-
Zo = 50
+
Zo = 50
-
R2
50
R1
50
VCC
C6 (Option)
0.1u
R3
50
VCC
Zo = 50 Ohm
Zo = 50 Ohm
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
R4
1K
3.3V LVPECL
R9
50
R10
50
U1
C8 (Option)
0.1u
R11
50
ICS853111
VCC
Zo = 50
+
-
VCC=3.3V
Zo = 50
(U1-9)
(U1-16)
(U1-25) (U1-32) (U1-1)
VCC
R8
50
R7
50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C7 (Option)
0.1u
R13
50
FIGURE 6. EXAMPLE ICS853111-02 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to solder as shown in Figure 7.For further information, please re-
the P.C. board.The expose metal pad is ground pad connected fer to the Application Note on Surface Mount Assembly of
to ground plane through thermal via. The exposed pad on the Amkor’sThermally /Electrically Enhance Leadframe Base Pack-
device to the exposed metal pad on the PCB is contacted through age, AmkorTechnology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
FIGURE 7. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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Integrated
Circuit
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 85mA = 323mW
Power (outputs)MAX = 30.94mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power_MAX (3.8V, with all outputs switching) = 323mW + 309.4mW = 632.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8°C/W perTable 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.632W * 43.8°C/W = 112.7°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN TQFP, E-PAD, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
57.8°C/W
43.8°C/W
500
52.1°C/W
41.3°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
69.3°C/W
49.5°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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Integrated
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3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
RL
50
VCCO - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.935V
OH_MAX
CCO_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.67V
CCO_MAX
OL_MAX
)
= 1.67V
OL_MAX
(V
- V
CCO_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO _MAX
OH_MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
- V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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Integrated
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Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
θ byVelocity (Linear Feet per Minute)
JA
0
200
57.8°C/W
43.8°C/W
500
52.1°C/W
41.3°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
69.3°C/W
49.5°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111-02 is: 1340
Pin compatible with MC100EP111 and MC100LVEP111
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Integrated
Circuit
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TQFP PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION
HEAT SLUG DOWN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABA-HD
SYMBOL
MINIMUM
NOMINAL
32
MAXIMUM
N
A
--
--
1.20
0.15
1.05
0.40
0.20
A1
A2
b
0.05
0.95
0.30
0.09
0.10
1.0
0.35
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
4.00 BASIC
9.00 BASIC
7.00 BASIC
5.60 Ref.
4.00 BASIC
0.80 BASIC
0.60
D1
D2
D3
E
E1
E2
E3
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853111AY-02
Marking
Package
Shipping Packaging Temperature
ICS853111A02
ICS853111A02
ICS853111A02L
ICS853111A02L
32 lead, E-Pad TQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853111AY-02T
ICS853111AY-02LF
ICS853111AY-02LFT
32 lead, E-Pad TQFP
1000 tape & reel
tray
32 lead "Lead-Free," E-Pad TQFP
32 lead "Lead-Free," E-Pad TQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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Integrated
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Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
T9
Page
10
17
Description of Change
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free marking.
Date
A
1/10/06
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