853111AYT [IDT]
Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 853111AYT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总19页 (文件大小：2389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-
LVPECL/ECL FANOUT BUFFER
ICS853111A
GENERAL DESCRIPTION
FEATURES
The ICS853111A is a low skew, high perfor-
• Ten differential LVPECL outputs
ICS
HiPerClockS™
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
• Two selectable differential LVPECL PCLK/nPCLK clock inputs
ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS853111A
• PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
is characterized to operate from either a 2.5V, 3.3V or a
5V power supply. Guaranteed output and part-to-part skew
characteristics make the ICS853111A ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nPCLK input
• Additive phase jitter, RMS: <0.3ps (typical)
• Output skew: 23ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 705ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 5.25V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
PCLK0
nPCLK0
0
1
PCLK1
nPCLK1
Q1
nQ1
24 23 22 21 20 19 18 17
VCCO
nQ2
Q2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q7
Q2
nQ2
nQ7
Q8
CLK_SEL
VBB
Q3
nQ3
nQ1
Q1
ICS853111A
nQ8
Q9
Q4
nQ4
nQ0
Q0
nQ9
Q5
nQ5
VCCO
VCCO
1
2
3
4
5
6
7
8
Q6
nQ6
Q7
nQ7
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q8
nQ8
Y Package
Top View
Q9
nQ9
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VCC
Power
Positive supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
2
CLK_SEL Input
Pulldown
Pulldown
3
4
PCLK0
Input
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
nPCLK0
Input Pullup/Pulldown
Output
5
6
VBB
Bias voltage.
PCLK1
Input
Pulldown
Non-inverting differential clock input.
Inverting differential LVPECL clock input.
VCC/2 default when left floating.
7
nPCLK1
Input Pullup/Pulldown
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
VEE
Power
Power
Negative supply pin.
VCCO
Output supply pins.
nQ9, Q9 Output
nQ8, Q8 Output
nQ7, Q7 Output
nQ6, Q6 Output
nQ5, Q5 Output
nQ4, Q4 Output
nQ3, Q3 Output
nQ2, Q2 Output
nQ1, Q1 Output
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
RPULLDOWN Input Pulldown Resistor
75
kΩ
Pullup/Pulldown Resistors
50
kΩ
RVCC/
2
TABLE 3A. CLOCK INPUT FUNCTION TABLE
TABLE 3B. CONTROL INPUT
FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
Inputs
PCLKx nPCLKx Q0:Q9 nQ0:Q9
CLK_SEL Selected Source
0
1
1
0
LOW
HIGH
LOW
Differential to Differential
Differential to Differential
Non Inverting
Non Inverting
0
1
PCLK0, nPCLK0
PCLK1, nPCLK1
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
1
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Single Ended to Differential Non Inverting
Single Ended to Differential Non Inverting
Biased;
NOTE 1
Biased;
NOTE 1
0
1
Single Ended to Differential
Single Ended to Differential
Inverting
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
6V (LVPECL mode, VEE = 0)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Characteris-
tics is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
50mA
Surge Current 100mA
VBB Sink/Source, IBB
0.5mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 37.8°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V; VEE = 0V
Symbol Parameter Test Conditions
Minimum
Typical Maximum Units
VCC
IEE
Positive Supply Voltage
Power Supply Current
2.375
3.3
5.25
85
V
mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
2.38
1.68
2.36
1.765
Min
2.225
1.425
2.075
1.43
Max
2.37
Min
Max
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.175 2.275
1.405 1.545
2.295
2.295
1.44
2.33
2.365
1.63
V
V
V
V
1.52
1.615
2.36
1.535
Input High Voltage, Single-Ended 2.075
2.075
1.43
2.36
Input Low Voltage, Single-Ended
1.43
1.86
150
1.2
1.765
1.765
Output Voltage Reference;
NOTE 2
VBB
1.98
1200
3.3
1.86
150
1.2
1.98
1200
3.3
1.86
150
1.2
1.98
1200
3.3
V
mV
V
VPP
Peak-to-Peak Input Voltage
800
800
800
Input High Voltage Common
Mode Range; NOTE 3, 4
VCMR
Input
PCLK0, PCLK1
IIH
IIL
200
200
200
µA
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
-10
-10
-10
µA
µA
Input
Low Current
nPCLK0, nPCLK1
-200
-200
-200
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
1.58
0.88
1.56
0.965
1200
Min
1.425
0.625
1.275
0.63
Max
1.57
Min
1.495
0.64
1.275
0.63
150
Max
1.565
0.83
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.375 1.475
0.605 0.745
1.495
0.72
1.53
V
V
0.815
1.56
0.735
Input High Voltage, Single-Ended 1.275
-0.83
0.965
1200
V
Input Low Voltage, Single-Ended
Peak-to-Peak Input Voltage
0.63
150
0.965
1200
V
VPP
800
150
800
800
mV
Input High Voltage Common
Mode Range; NOTE 2, 3
VCMR
IIH
1.2
2.5
1.2
2.5
1.2
2.5
V
Input
PCLK0, PCLK1
200
200
200
µA
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
-10
-10
-10
µA
µA
Input
Low Current
IIL
nPCLK0, nPCLK1
-200
-200
-200
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
4.08
3.38
4.06
3.465
Min
3.925
3.125
3.775
3.13
Max
4.07
Min
3.995
3.14
Max
4.065
3.33
VOH
VOL
VIH
VIL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
3.875 3.975
3.105 3.245
3.995
4.03
V
V
V
V
3.22
3.315
4.06
3.235
Input High Voltage, Single-Ended 3.775
3.775
3.13
4.06
Input Low Voltage, Single-Ended
3.13
3.56
150
1.2
3.465
3.465
Output Voltage Reference;
NOTE 2
VBB
3.68
1200
5
3.56
150
1.2
3.68
1200
5
3.56
150
1.2
3.68
1200
5
V
mV
V
VPP
Peak-to-Peak Input Voltage
800
800
800
Input High Voltage Common
Mode Range; NOTE 3, 4
VCMR
Input
PCLK0, PCLK1
IIH
IIL
200
200
200
µA
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
-10
-10
-10
µA
µA
Input
Low Current
nPCLK0, nPCLK1
-200
-200
-200
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 4E. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
-40°C
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
VOH
VOL
VIH
-1.125
-1.025 -0.92
-1.755 -1.62
-0.94
-1.075
-1.005 -0.93
-1.78 -1.685
-0.94
-1.005
-0.97 -0.935
-1.765 -1.67
-0.94
V
V
-1.895
-1.225
-1.87
-1.44
150
-1.875
-1.225
-1.87
-1.44
150
-1.86
-1.225
-1.87
-1.44
150
V
VIL
-1.535
-1.535
-1.535
V
Output Voltage Reference;
NOTE 2
Peak-to-Peak
VBB
VPP
-1.32
-1.32
-1.32
V
800
1200
0
800
1200
0
800
1200
0
mV
Input Voltage
Input High Voltage
Common Mode Range;
NOTE 3, 4
VCMR
VEE+1.2V
VEE+1.2V
VEE+1.2V
V
Input
PCLK[0:1],
IIH
IIL
200
200
200
µA
High Current nPCLK[0:1]
PCLK[0:1]
-10
-10
-10
µA
µA
Input
Low Current
nPCLK[0:1]
-200
-200
-200
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V OR VCC = 2.375V TO 5.25V; VEE = 0V
-40°C
Typ
>3
25°C
Typ
>3
85°C
Typ
>3
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
fMAX
Output Frequency
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
570
670
23
770
35
605
705
23
805
35
665
765
23
875
35
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
85
150
85
150
85
150
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tjit
0.03
0.03
200
0.03
200
ps
ps
tR/tF
Output Rise/Fall Time 20% to 80%
85
200
315
100
285
85
315
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.03ps (typical)
-50
-60
-70
-80
-90
-100
-110
-120
-130
140
-
-150
160
-
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
VCCO
,
Qx
nPCLK0,
nPCLK1
LVPECL
VPP
VCMR
Cross Points
nQx
PCLK0,
PCLK1
VEE
-3.25V to -0.375V
VEE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nQx
Qx
Qx
PART 2
nQy
nQy
Qy
Qy
tsk(o)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nPCLK0,
nPCLK1
80%
80%
PCLK0,
PCLK1
VSWING
20%
Clock
20%
nQ0:nQ9
Outputs
tF
tR
Q0:Q9
tPD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
Figure 2A shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLKx
V_REF
nPCLKx
C1
0.1u
R2
1K
FIGURE 2A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS
Figure 2B shows an example of the differential input that can
be wired to accept single ended LVPECL levels. The reference
negative input. The C1 capacitor should be located as close as
possible to the input pin.
voltage level V generated from the device is connected to the
BB
VDD(or VCC)
CLK_IN
+
VBB
-
C1
0.1uF
FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS
PCLK/nPCLK INPUTS
OUTPUTS
LVPECL OUTPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
designed to drive 50Ω transmission lines. Matched imped-
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
CC
CC
CC
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
250
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination.
Figure 6A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
V
- 2V = 3V at the receiver. Figure 6B shows Thevenin
CC
equivalence of Figure 6A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 6B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
FIGURE 6A. STANDARD 5V LVPECL OUTPUT TERMINATION
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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SCHEMATIC EXAMPLE
This application note provides general design guide using
ICS853111A LVPECL buffer. Figure 7 shows a schematic
example of the ICS853111A LVPECL clock buffer. In this
example, the input is driven by an LVPECL driver. CLK_SEL is
set at logic low to select PCLK0/nPCLK0 input.
Zo = 50
+
Zo = 50
-
R2
50
R1
50
VCC
C6 (Option)
0.1u
R3
50
VCC
Zo = 50 Ohm
Zo = 50 Ohm
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VCC
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
R4
1K
3.3V LVPECL
R9
50
R10
50
U1
C8 (Option)
0.1u
R11
50
ICS853111
VCC
Zo = 50
+
-
VCC=3.3V
Zo = 50
(U1-9)
(U1-16)
(U1-25) (U1-32) (U1-1)
VCC
R8
50
R7
50
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C7 (Option)
0.1u
R13
50
FIGURE 7. EXAMPLE ICS853111A LVPECL CLOCK OUTPUT BUFFER SCHEMATIC
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853111A.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853111A is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 5.25V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 5.25V * 85mA = 446.3mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30.94mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW
Total Power
(3.8V, with all outputs switching) = 446.3mW + 309.4mW = 755.7mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θ * Pd_total + TA
JA
Tj = Junction Temperature
θJA = junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.547W * 42.1°C/W = 93°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 32-PIN LQFP FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.935V
CCO_MAX
OUT
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.67V
CCO_MAX
OUT
OL_MAX
)
(V
- V
= 1.67V
CCO_MAX
OL_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO _MAX
OH_MAX
L
CCO
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 8 θ VS. AIR FLOW TABLE FOR 32 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853111A is: 1340
Pin compatible with MC100EP111 and MC100LVEP111
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
PACKAGE OUTLINE AND DIMENSIONS - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
16
ICS853111AY REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
TABLE 10. ORDERING INFORMATION
Part/Order Number
853111AY
Marking
Package
Shipping Packaging Temperature
ICS853111AY
ICS853111AY
ICS853111AYL
ICS853111AYL
32 Lead LQFP
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
853111AYT
32 Lead LQFP
1000 tape & reel
tray
853111AYLF
853111AYFT
32 Lead "Lead-Free" LQFP
32 Lead ""Lead-Free"" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
11
Corrected Figure 5C.
13 & 14 Power Considerations - corrected Power(outputs)MAX from 30.2mW to 30.94mW,
and revised Junction Temperature and Worse Case Power Dissipation
equations.
A
10/31/03
1
3
4
5
Features section - increased voltage range to 5.25V.
Power Supply table - increased maximum VCC to 5.25V.
T4A
T4D
T5
Added 5V LVPECL DC Characteristics table.
AC Characteristics table - increased VEE range to -5.25V to 2.375V, and VCC
to 2.375V to 5.25V.
B
4/28/04
7
Corrected Output Load AC Test Circuit Diagram, VEE range from" -1.8V to -
0.375V" to "-3.25V to -0.375V".
11
LVPECL clock Input Interface - added another CML driver diagram.
13 & 14 Power Considerations - changed Power(core)max from 3.8V to 5.25V and
recalculated equations.
3
17
3
Absolute Maximum Ratings, corrected Supply Voltage & Negative Supply
Voltage from 4.6V & -4.6V to 6V & -6V.
Ordering Information Table - added lead-free marking to part number.
Updated datasheets.
LVPECL 3.3V DC Characteristics Table - corrected IIH max. from 150µA to
200µA; and IIL min. from -150µA to -200µA.
B
B
5/14/04
7/6/07
T10
T4B
T4C, T4D
T4E
4
LVPECL DC Characteristics Tables - corrected IIH max. from 150µA to 200µA;
and IIL min. from -150µA to -200µA.
ECL DC Characteristics Table - corrected IIH max. from 150µA to 200µA; and IIL
min. from -150µA to -200µA.
C
10/25/07
5
12
Added Termination for 5V LVPECL Output section.
IDT™ / ICS™ 1-TO-10, LVPECL/ECL FANOUT BUFFER
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ICS853111AY REV. C OCTOBER 23, 2008
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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo, ICS and HiPerClocks are
trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are
or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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