853111BYLFT_技术文档

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-

2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ICS853111B

GENERAL DESCRIPTION

FEATURES

The ICS853111B is a low skew, high perfor-

• Ten differential 2.5V/3.3V LVPECL / ECL outputs

• Two selectable differential input pairs

ICS

HiPerClockS™

mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/

ECL Fanout Buffer and a member of the

HiPerClockS™ family of High Performance

Clock Solutions from ICS. The ICS853111B

• PCLKx, nPCLKx pairs can accept the following

differential input levels: LVPECL, LVDS, CML, SSTL

is characterized to operate from either a 2.5V or a 3.3V

power supply. Guaranteed output and part-to-part skew

characteristics make the ICS853111B ideal for those clock

distribution applications demanding well defined perfor-

mance and repeatability.

• Maximum output frequency: >3GHz

• Translates any single ended input signal to 3.3V

LVPECL levels with resistor bias on nPCLK input

• Output skew: 20ps (typical)

• Part-to-part skew: 85ps (typical)

• Propagation delay: 495ps (typical)

• Jitter, RMS: < 0.03ps (typical)

• LVPECL mode operating voltage supply range:

V_CC= 2.375V to 3.8V, V_EE= 0V

• ECL mode operating voltage supply range:

V_CC= 0V, V_EE= -3.8V to -2.375V

• -40°C to 85°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

Q0

nQ0

PCLK0

nPCLK0

0

1

PCLK1

nPCLK1

Q1

nQ1

24 23 22 21 20 19 18 17

VCCO

nQ2

Q2

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

VCCO

Q7

Q2

nQ2

nQ7

Q8

CLK_SEL

V_BB

Q3

nQ3

nQ1

Q1

ICS853111B

nQ8

Q9

Q4

nQ4

nQ0

Q0

nQ9

Q5

nQ5

V^CCO

1

2

3

4

5

6

7

8

Q6

nQ6

Q7

nQ7

32-Lead TQFP, E-PAD

7mm x 7mm x 1.0mm package body

Q8

nQ8

Y Package

Top View

Q9

nQ9

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1

V_CC

Power

Positive supply pin.

Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.

When LOW, selects PCLK0, nPCLK0 inputs.

LVPECL interface levels.

2

CLK_SEL Input

Pulldown

3

4

PCLK0

Input

Non-inverting differential clock input.

Inverting differential LVPECL clock input.

V_CC/2 default when left floating.

nPCLK0

Input Pullup/Pulldown

5

6

V_BB

Output

Bias voltage.

PCLK1

Input

Pulldown

Non-inverting differential clock input.

Inverting differential LVPECL clock input.

V_CC/2 default when left floating.

7

nPCLK1

Input Pullup/Pulldown

8

9, 16, 25, 32

10, 11

12, 13

14, 15

17, 18

19, 20

21, 22

23, 24

26, 27

28, 29

30, 31

V_EE

Power

Negative supply pin.

V_CCO

Output supply pins.

nQ9, Q9 Output

nQ8, Q8 Output

nQ7, Q7 Output

nQ6, Q6 Output

nQ5, Q5 Output

nQ4, Q4 Output

nQ3, Q3 Output

nQ2, Q2 Output

nQ1, Q1 Output

nQ0, Q0 Output

Differential output pair. LVPECL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

R_PULLDOWNInput Pulldown Resistor

75

kΩ

Pullup/Pulldown Resistors

50

kΩ

R_VCC/

2

TABLE 3A. CLOCK INPUT FUNCTION TABLE

TABLE 3B. CONTROL INPUT

FUNCTION TABLE

Inputs

Outputs

Input to Output Mode

Polarity

Inputs

PCLKx nPCLKx Q0:Q9 nQ0:Q9

CLK_SEL Selected Source

0

1

0

LOW

HIGH

LOW

Differential to Differential

Non Inverting

0

1

PCLK0, nPCLK0

PCLK1, nPCLK1

HIGH

Biased;

NOTE 1

Biased;

NOTE 1

0

1

LOW

HIGH

LOW

HIGH

LOW

HIGH

Single Ended to Differential Non Inverting

Biased;

NOTE 1

Biased;

NOTE 1

0

1

Single Ended to Differential

Inverting

NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to

Accept Single Ended Levels".

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V_CC

4.6V (LVPECL mode, V_EE= 0)

-4.6V (ECL mode, V_CC= 0)

-0.5V to V_CC+ 0.5 V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Characteris-

tics is not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect product reliability.

Negative Supply Voltage, V_EE

Inputs, V_I(LVPECL mode)

Inputs, V_I(ECL mode)

0.5V to V_EE- 0.5V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

V_BBSink/Source, I_BB

0.5mA

Operating Temperature Range, T_A-40°C to +85°C

Storage Temperature, T_STG-65°C to 150°C

Package Thermal Impedance, θ_JA49.5°C/W (0 lfpm)

(Junction-to-Ambient)

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= 2.375V TO 3.8V; V_EE= 0V

Symbol Parameter Test Conditions

Minimum Typical Maximum Units

V_CC

I_EE

Positive Supply Voltage

Power Supply Current

2.375

3.3

3.8

V

120

mA

TABLE 4B. LVPECL DC CHARACTERISTICS, V_CC= 3.3V; V_EE= 0V

-40°C

25°C

Typ

85°C

Typ

Symbol Parameter

Units

Min

Typ

Max

Min

Max

Min

Max

V_OH

V_OL

V_IH

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Input High Voltage(Single-Ended)

Input Low Voltage(Single-Ended)

Output Voltage Reference; NOTE 2

Peak-to-Peak Input Voltage

2.175 2.275 2.38 2.225 2.295 2.37

1.405 1.545 1.68 1.425 1.52 1.615

2.295 2.33 2.365

1.44 1.535 1.63

V

2.075

1.43

1.86

150

2.36 2.075

1.765 1.43

2.36

1.765

1.98

2.075

1.43

1.86

150

2.36

1.765

1.98

V

V_IL

V

V_BB

V_PP

1.98

1.86

150

V

800

1200

800

1200

800

1200

mV

Input High Voltage

Common Mode Range; NOTE 3, 4

V_CMR

I_IH

1.2

3.3

1.2

3.3

1.2

3.3

V

Input

PCLK0, PCLK1

200

µA

High Current nPCLK0, nPCLK1

PCLK0, PCLK1

-10

µA

Input

Low Current

I_IL

nPCLK0, nPCLK1

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Single-ended input operation is limited. V_CC≥ 3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as V_IH.

NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

TABLE 4C. LVPECL DC CHARACTERISTICS, V_CC= 2.5V; V_EE= 0V

-40°C

Typ

25°C

Typ

85°C

Typ

Symbol Parameter

Units

Min

Max

1.58

0.88

1.56

0.965

1200

Min

Max

1.57

Min

Max

1.565

0.83

V_OH

V_OL

V_IH

V_IL

Output High Voltage; NOTE 1

1.375 1.475

0.605 0.745

1.275

1.425 1.495

1.495 1.53

0.64 0.735

1.275

V

Output Low Voltage; NOTE 1

Input High Voltage(Single-Ended)

Input Low Voltage(Single-Ended)

Peak-to-Peak Input Voltage

0.625

1.275

0.63

0.72

0.815

1.56

V

0.63

0.965

1200

0.63

0.965

1200

V

V_PP

150

1.2

800

150

800

150

1.2

800

mV

Input High Voltage

Common Mode Range; NOTE 3, 4

V_CMR

I_IH

2.5

1.2

2.5

V

Input

PCLK0, PCLK1

200

µA

High Current nPCLK0, nPCLK1

PCLK0, PCLK1

-10

µA

Input

Low Current

I_IL

nPCLK0, nPCLK1

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Single-ended input operation is limited. V_CC≥ 3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as V_IH.

NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

TABLE 4D. ECL DC CHARACTERISTICS, V_CC= 0V; V_EE= -3.8V TO -2.375V

-40°C

Typ

25°C

Typ

85°C

Typ

Symbol Parameter

Units

Min

-1.125

-1.895

-1.225

-1.87

-1.44

150

Max

-0.92

-1.62

-0.94

-1.535

-1.32

1200

Min

-1.075

-1.875

-1.225

-1.87

-1.44

150

Max

-0.93

-1.685

-0.94

-1.535

-1.32

1200

Min

-1.005

-1.86

-1.225

-1.87

-1.44

150

Max

-0.935

-1.67

-0.94

-1.535

-1.32

1200

V_OH

V_OL

V_IH

Output High Voltage; NOTE 1

-1.025

-1.755

-1.005

-1.78

-0.97

-1.765

V

Output Low Voltage; NOTE 1

Input High Voltage (Single-Ended)

Input Low Voltage (Single-Ended)

Output Voltage Reference; NOTE 2

Peak-to-Peak Input Voltage

V

V_IL

V

V_BB

V_PP

V

800

mV

Input High Voltage

Common Mode Range; NOTE 3, 4

V_CMR

I_IH

V_EE+1.2V

0

V_EE+1.2V

0

V_EE+1.2V

0

V

Input

PCLK0, PCLK1

200

µA

High Current nPCLK0, nPCLK1

PCLK0, PCLK1

-10

µA

Input

Low Current

I_IL

nPCLK0, nPCLK1

-200

Input and output parameters vary 1:1 with V_CC. V_EEcan vary +0.925V to -0.5V.

NOTE 1: Outputs terminated with 50Ω to V_CCO- 2V.

NOTE 2: Single-ended input operation is limited. V_CC≥ 3V in LVPECL mode.

NOTE 3: Common mode voltage is defined as V_IH.

NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1

is V_CC+ 0.3V.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

TABLE 5. AC CHARACTERISTICS, V_CC= 0V; V_EE= -3.8V TO -2.375V OR V_CC= 2.375 TO 3.8V; V_EE= 0V

-40°C

Min Typ

25°C

Max Min Typ

85°C

Max Min Typ

Symbol Parameter

Units

Max

f_MAX

Output Frequency

>3

375 475

20

>3

395 495

20

>3

425 530

20

GHz

ps

t_PD

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

575

32

595

32

635

32

tsk(o)

tsk(pp)

ps

Part-to-Part Skew; NOTE 3, 4

85

150

85

150

85

150

ps

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter section

tjit

0.03

ps

t_R/t_F

Output Rise/Fall Time

20% to 80%

75

150

220

80

150

215

78

150

215

ps

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet

specifications after thermal equilibrium has been reached under these conditons.

NOTE: All parameters are measured ≤ 1GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

ADDITIVE PHASE JITTER

band to the power in the fundamental. When the required offset

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications.Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz

is specified, the phase noise is called a dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

0

-10

-20

-30

-40

Input/Output Additive

Phase Jitter at 155.52MHz

= 0.03ps (typical)

-50

-60

-70

-80

-90

-100

-110

-120

-130

140

-

-150

160

-

-170

-180

-190

1k

10k

100k

1M

10M

100M

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often the

noise floor of the equipment is higher than the noise floor of the

device. This is illustrated above. The device meets the noise floor

of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

PARAMETER MEASUREMENT INFORMATION

2V

V_CC

SCOPE

V_CC

V_CCO

,

Qx

nPCLK0,

nPCLK1

LVPECL

V_PP

V_CMR

Cross Points

nQx

PCLK0,

PCLK1

V_EE

-1.8V to -0.375V

V_EE

OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

PART 1

nQx

Qx

PART 2

nQy

Qy

tsk(o)

OUTPUT SKEW

PART-TO-PART SKEW

nQ0:nQ9

80%

nPCLK0,

nPCLK1

80%

PCLK0,

PCLK1

V_SWING

20%

nQ0:nQ9

Q0:Q9

t_F

t_R

Q0:Q9

t_PD

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

Figure 1A shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ V /2 is

generated by the bias resistors R1, R2 and C1. This bias ^Cc^Circuit

should be located as close as possible to the input pin. The ratio

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

CC

and R2/R1 = 0.609.

V_CC

R1

1K

Single Ended Clock Input

PCLKx

V_REF

nPCLKx

C1

0.1u

R2

1K

FIGURE 1A. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS

Figure 1B shows an example of the differential input that can

be wired to accept single ended LVPECL levels. The reference

negative input. The C1 capacitor should be located as close as

possible to the input pin.

voltage level V generated from the device is connected to the

BB

V

CC

C1

0.1uF

CLK_IN

PCLK

VBB

nPCLK

FIGURE 1B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

LVPECL CLOCK INPUT INTERFACE

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

differential signals. Both V_SWINGand V_OHmust meet the V_PPand

V_CMRinput requirements. Figures 2A to 2F show interface

examples for the HiPerClockS PCLK/nPCLK input driven by

the most common driver types. The input interfaces suggested

here are examples only. If the driver is from another vendor,

use their termination recommendation. Please consult with the

vendor of the driver component to confirm the driver termination

requirements.

3.3V

Zo = 50 Ohm

R1

50

R2

50

CML

Zo = 50 Ohm

PCLK

R1

100

nPCLK

Zo = 50 Ohm

nPCLK

HiPerClockS

PCLK/nPCLK

HiPerClockS

PCLK/nPCLK

CML Built-In Pullup

FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A CML DRIVER

FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A BUILT-IN PULLUP CML DRIVER

3.3V

R3

R4

125

C1

3.3V LVPECL

Zo = 50 Ohm

PCLK

VBB

PCLK

C2

nPCLK

PCLK/nPCLK

nPCLK

HiPerClockS

Input

LVPECL

R5

100 - 200

R6

100 - 200

R1

50

R2

50

R1

84

R2

84

FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVPECL DRIVER

FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVPECL DRIVER WITH AC COUPLE

2.5V

3.3V

2.5V

3.3V

R3

R4

Zo = 50 Ohm

120

C1

LVDS

SSTL

Zo = 60 Ohm

PCLK

R5

100

VBB

C2

nPCLK

Zo = 50 Ohm

nPCLK

PCLK/nPCLK

HiPerClockS

PCLK/nPCLK

R1

1K

R2

1K

R1

120

R2

120

FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY AN SSTL DRIVER

FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN

BY A 3.3V LVDS DRIVER

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS

PCLK/nPCLK INPUTS

OUTPUTS

LVPECL OUTPUTS

For applications not requiring the use of a differential input, both

the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from PCLK to ground.

All unused LVPECL outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

ance techniques should be used to maximize operating fre-

quency and minimize signal distortion. Figures 3A and 3B

show two different layouts which are recommended only as

guidelines. Other suitable clock layouts may exist and it

would be recommended that the board designers simulate

to guarantee compatibility across all printed circuit and clock

component process variations.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, ter-

minating resistors (DC current path to ground) or current

sources must be used for functionality. These outputs are

designed to drive 50Ω transmission lines. Matched imped-

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

1

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

TERMINATION FOR 2.5V LVPECL OUTPUT

50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground

level. The R3 in Figure 4B can be eliminated and the termination

is shown in Figure 4C.

CC

Figure 4A and Figure 4B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating

2.5V

VCCO=2.5V

R1

250

R3

250

Zo = 50 Ohm

+

-

Zo = 50 Ohm

-

2,5V LVPECL

Driver

2,5V LVPECL

Driv er

R1

50

R2

50

R2

62.5

R4

62.5

R3

18

FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE

FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE

2.5V

VCCO=2.5V

Zo = 50 Ohm

+

Zo = 50 Ohm

-

2,5V LVPECL

Driver

R1

50

R2

50

FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

SCHEMATIC EXAMPLE

This application note provides general design guide using

ICS853111B LVPECL buffer.Figure 6 shows a schematic example

of the ICS853111B LVPECL clock buffer. In this example, the

input is driven by an LVPECL driver. CLK_SEL is set at logic high

to select PCLK0/nPCLK0 input.

Zo = 50

+

-

Zo = 50

R2

50

R1

50

VCC

C6 (Option)

0.1u

R3

50

VCC

Zo = 50 Ohm

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VCC

Q3

nQ3

Q4

nQ4

Q5

nQ5

Q6

nQ6

CLK_SEL

PCLK0

nPCLK0

VBB

PCLK1

nPCLK1

VEE

R4

1K

3.3V LVPECL

R9

50

R10

50

U1

C8 (Option)

0.1u

R11

50

ICS853111

VCC

Zo = 50

+

-

VCC=3.3V

Zo = 50

(U1-9)

(U1-16)

(U1-25) (U1-32) (U1-1)

VCC

R8

50

R7

50

C1

0.1uF

C2

0.1uF

C3

0.1uF

C4

0.1uF

C5

0.1uF

C7 (Option)

0.1u

R13

50

FIGURE 5. EXAMPLE ICS853111B LVPECL CLOCK OUTPUT BUFFER SCHEMATIC

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

EPADTHERMAL RELEASE PATH

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as shown in Figure 6. The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

are application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended

to determine the minimum number needed. Maximum thermal

and electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as

many vias connected to ground as possible. It is also

recommended that the via diameter should be 12 to 13mils (0.30

to 0.33mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process

which may result in voids in solder between the exposed pad/

slug and the thermal land. Precautions should be taken to

eliminate any solder voids between the exposed heat slug and

the land pattern. Note: These recommendations are to be used

as a guideline only. For further information, refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor

Technology.

While the land pattern on the PCB provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias.

The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)

SOLDER

EXPOSED HEAT SLUG

LAND PATTERN

(GROUND PAD)

PIN PAD

GROUND PLANE

PIN PAD

THERMAL VIA

FIGURE 6. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS853111B.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853111B is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 3.8V, which gives worst case results.

CC

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core) = V

* I

= 3.8V * 120mA = 456mW

EE_MAX

MAX

CC_MAX

Power (outputs) = 30.94mW/Loaded Output pair

MAX

If all outputs are loaded, the total power is 10 * 30.94mW = 309.4mW

Total Power

(3.8V, with all outputs switching) = 456mW + 309.4mW = 765.4mW

_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

TM

device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θ * Pd_total + T_A

JA

Tj = Junction Temperature

θ_JA= junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.8°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.765W * 43.8°C/W = 118.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ FOR 32-PIN TQFP, E-PAD FORCED CONVECTION

JA

θ by Velocity (Linear Feet per Minute)

JA

0

200

57.8°C/W

43.8°C/W

500

52.1°C/W

41.3°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

69.3°C/W

49.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 7.

V_CCO

Q1

V_OUT

R L

50

V_CCO- 2V

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage of V – 2V.

CCO

•

For logic high, V = V

= V

– 0.935V

CCO_MAX

OUT

OH_MAX

)

= 0.935V

OH_MAX

(V

– V

CC_MAX

For logic low, V = V

= V

– 1.67V

CCO_MAX

OUT

OL_MAX

)

= 1.67V

OL_MAX

(V

– V

CCO_MAX

))

Pd_H = [(V

– (V

– 2V))/R ] * (V

– V

) = [(2V – (V

– V

/R ] * (V

– V

) =

OH_MAX

CCO_MAX

OH_MAX

_MAX

OH_MAX

CCO _MAX

OH_MAX

L

CCO

L

[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW

))

Pd_L = [(V

– (V

– 2V))/R ] * (V

– V

) = [(2V – (V

/R ] * (V

– V

) =

OL_MAX

CCO_MAX

OL_MAX

_MAX

CCO

OL_MAX

CCO_MAX

OL_MAX

L

[(2V – 1.67V)/50Ω] * 1.67V = 11.02mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

RELIABILITY INFORMATION

TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD

JA

θ by Velocity (Linear Feet per Minute)

JA

0

200

57.8°C/W

43.8°C/W

500

52.1°C/W

41.3°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

69.3°C/W

49.5°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS853111B is: 1340

Pin compatible with MC100EP111 and MC100LVEP111

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

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LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD

-HD VERSION

HEAT SLUG DOWN

TABLE 8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

32

--

1.20

0.15

1.05

0.40

0.20

A1

0.05

0.95

0.30

0.09

--

A2

1.0

b

0.35

c

--

9.00 BASIC

7.00 BASIC

5.60 Ref.

3.5

D, E

D1, E1

D2, E2

D3, E3

e

3.0

4.0

0.80 BASIC

0.60

L

0.45

0.75

θ

--

0°

7°

ccc

--

0.10

Reference Document:JEDEC Publication 95, MS-026

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

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ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

TABLE 9. ORDERING INFORMATION

Part/Order Number

853111BY

Marking

Package

Shipping Packaging

tray

Temperature

-40°C to 85°C

ICS853111BY

ICS853111BYLF

32 lead TQFP, E-PAD

853111BYT

32 lead TQFP, E-PAD

1000 tape & reel

tray

853111BYLF

853111BYLFT

"Lead Free" 32 lead TQFP, E-PAD

1000 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and

industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT

reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

18

ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

REVISION HISTORY SHEET

Rev

Table

Page

Description of Change

Date

9

Corrected Figure 3C.

A

11/13/03

Added "Lead Free" Part/Order Number rows.

Features Section - added Lead-Free bullet.

17

1

T8

T9

16

17

Package Dimensions - corrected dimensions D2/E2 to read 3.5mm from 5.60.

A

B

6/16/05

9/5/07

Ordering Information Table - corrected Lead-Free marking and added

Lead-Free note.

LVPECL DC Characteristics Table - corrected V_IHmax. (@ 85°)

1.56V from -0.83V.

T4C

4

10

16

Added Recommendations for Unused Input and Output Pins.

T8

Package Dimensions - added dimensions D3/E3.

3.3V LVPECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

2.5V LVPECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

ECL DC Characteristics - changed I_IHmax. from 150µA to 200µA.

Changed I_ILmin. from -150µA to -200µA.

Updated EPAD Thermal Release Path.

T4B

3

4

T4C

T4D

C

2/12/08

13

2

T1

Pin Description Table - corrected interface levels from LVCMOS/LVTTL to

LVPECL.

1/13/09

IDT^™/ ICS^™1-TO-10, LVPECL/ECL FANOUT BUFFER

19

ICS853111BY REV. C JANUARY 13, 2009

ICS853111B

LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

For Tech Support

Corporate Headquarters

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138

800-345-7015 (inside USA)

+408-284-8200 (outside USA)

Fax: 408-284-2775

netcom@idt.com

+480-763-2056

www.IDT.com/go/contact IDT

United States

800-345-7015 (inside USA)

+408-284-8200 (outside USA)

of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be

trademarks or registered trademarks used to identify products or services of their respective owners.

Printed in USA


型号：	853111BYLFT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew Clock Driver, 853111 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, TQFP-32 驱动逻辑集成电路
文件：	总20页 (文件大小：526K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

853111BYLFT [IDT]

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