85311AMILF [IDT]

Low Skew, 1-to-2 , Different ial-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer;


型号：	85311AMILF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Low Skew, 1-to-2 , Different ial-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer 驱动光电二极管逻辑集成电路
文件：	总17页 (文件大小：315K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Low Skew , 1-to-2, Differential-to-2.5V, 3.3V

LVPECL/ ECL Fanout Buffer

85311I

Datasheet

General Description

Features

The 85311I is a low skew, high performance 1-to-2

• Two differential 2.5V/3.3V LVPECL / ECL outputs

• One CLK, nCLK input pair

Differential-to-2.5V/3.3V ECL/LVPECL Fanout Buffer. The CLK,

nCLK pair can accept most standard differential input levels.The

85311I is characterized to operate from either a 2.5V or a 3.3V

power supply. Guaranteed output and part-to-part skew

• CLK, nCLK pair can accept the following differential input levels:

LVDS, LVPECL, LVHSTL, SSTL, HCSL

• Maximum output frequency: 1GHz

characteristics make the 85311I ideal for those clock distribution

applications demanding well defined performance and repeatability.

• Translates any single ended input signal to 3.3V LVPECL levels

with resistor bias on nCLK input

• Output skew: 20ps (maximum)

• Part-to-part skew: 350ps (maximum)

• Propagation delay: 2.1ns (maximum)

• Additive phase jitter, RMS: 0.14ps (typical), 3.3V

• LVPECL mode operating voltage supply range: 

V_CC= 2.375V to 3.465V, V_EE= 0V

• ECL mode operating voltage supply range:

V_CC= 0V, V_EE= -2.375V to -3.465V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

nQ0

VCC

Pulldown

Pullup

CLK

nCLK

V^EE

nCLK

nQ1

85311I

8-Lead SOIC

3.90mm x 4.903mm x 1.37mm package body

M Package

Top View

Revision B, February 18, 2016

85311I Datasheet

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions

Number

Name

Q0, nQ0

Q1, nQ1

V_EE

Type

Description

1, 2

3, 4

Output

Power

Input

Differential output pair. LVPECL interface levels.

Negative supply pin.

nCLK

CLK

Pullup

Inverting differential clock input.

Input

Pulldown Non-inverting differential clock input.

Positive supply pin.

V_CC

Power

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

Input Pullup Resistor

R_PULLUP

k

R_PULLDOWNInput Pulldown Resistor

k

Revision B, February 18, 2016

85311I Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond 

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for 

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

4.6V

-0.5V to V_CC+ 0.5V

Outputs, I_{O }



Continuos Current

Surge Current

50mA

100mA

Storage Temperature, T_STG

-65C to 150C

Package Thermal Impedance, _JA

103C/W (0 lfpm)

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, V_CC= 3.3V 5% or 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol

V_CC

Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

2.625

Units

Positive Supply Voltage

Power Supply Current

2.375

2.5

I_EE

Table 3B. Differential DC Characteristics, V_CC= 3.3V 5% or 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

µA

nCLK

CLK

V_CC= V_IN= 3.465V or 2.625V

I_IHInput High Current

_CC= V_IN= 3.465V or 2.625V

150

µA

nCLK

CLK

V_CC= 3.465V or 2.625V, V_IN= 0V

-150

-5

µA

I_IL

Input Low Current

µA

Peak-to-Peak Input Voltage;

NOTE 1

V_PP

0.15

1.3

Common Mode Input Voltage; 

NOTE 1, 2

V_CMR

V_EE+ 0.5

V_CC– 0.85

NOTE 1: V_ILshould not be less than -0.3V.

NOTE 2: Common mode voltage is defined as V_IH.

Revision B, February 18, 2016

85311I Datasheet

Table 3C. LVPECL DC Characteristics, V_CC= 3.3V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

V_CC– 1.4

V_CC– 2.0

0.65

Typical

Maximum

Units

V_OH

Output High Current; NOTE 1

V_CC– 0.9

V_CC– 1.7

1.0

V_OL

Output Low Current; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50 to V_CC– 2V.

Table 3D. LVPECL DC Characteristics, V_CC= 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

V_CC– 1.4

V_CC– 2.0

0.4

Typical

Maximum

V_CC– 0.9

V_CC– 1.5

1.0

Units

V_OH

Output High Current; NOTE 1

V_OL

Output Low Current; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50 to V_CC– 2V.

AC Electrical Characteristics

Table 4A. AC Characteristics, V_CC= 3.3V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

f_MAXMaximum Output Frequency

t_PD

Test Conditions

Minimum

Typical

Maximum

Units

GHz

Propagation Delay; NOTE 1

ƒ  1GHz

0.9

2.1

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

156.25MHz, Integration Range

(12kHz – 20MHz)

tjit

0.14

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 2, 4

Part-to-Part Skew; NOTE 3, 4

Output Rise/Fall Time

Output Duty Cycle

350

700

20% to 80% @ 50MHz

300

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

All parameters are measured 500MHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Revision B, February 18, 2016

85311I Datasheet

Table 4B. AC Characteristics, V_CC= 2.5V 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

f_MAXMaximum Output Frequency

t_PD

Test Conditions

Minimum

Typical

Maximum

Units

GHz

Propagation Delay; NOTE 1

ƒ  1GHz

0.9

2.1

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

156.25MHz, Integration Range

(12kHz – 20MHz)

tjit

0.135

tsk(o)

tsk(pp)

t_R/ t_F

odc

Output Skew; NOTE 2, 4

Part-to-Part Skew; NOTE 3, 4

Output Rise/Fall Time

Output Duty Cycle

250

700

20% to 80% @ 50MHz

250

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has

been reached under these conditions.

All parameters are measured 500MHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross

points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Revision B, February 18, 2016

85311I Datasheet

Additive Phase Jitter (3.3V)

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 156.25MHz

12kHz to 20MHz = 0.14ps (typical)

Offset Frequency (Hz)

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

Revision B, February 18, 2016

85311I Datasheet

Parameter Measurement Information

SCOPE

V_CC

nQx

V_EE

-1.3V 0.165V

-0.5V 0.125V

3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit

2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit

nQx

nCLK

nQy

Cross Points

CMR

CLK

Differential Input Level

Output Skew

Part 1

nQx

nCLK

CLK

Part 2

nQy

nQ[0:1]

Q[0:1]

t_PD

tsk(pp)

Part-to-Part Skew

Propagation Delay

Revision B, February 18, 2016

85311I Datasheet

Parameter Measurement Information, continued

nQ[0:1]

Q[0:1]

nQ[0:1]

Q[0:1]

Output Duty Cycle/Pulse Width/Period

Output Rise/Fall Time

Applications Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V_CC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock swing

is only 2.5V and V_CC= 3.3V, V_REF should be 1.25V and R2/R1 =

V_CC

Single Ended Clock Input

0.609.

CLK

V_REF

nCLK

0.1u

Figure 1. Single-Ended Signal Driving Differential Input

Revision B, February 18, 2016

85311I Datasheet

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both V_SWINGand V_OHmust meet the V_PP

and V_CMRinput requirements. Figures 2A to 2F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 2A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

LVHSTL

IDT

LVHSTL Driver

Input

50Ω

Figure 2A. CLK/nCLK Input Driven by an 

IDT Open Emitter LVHSTL Driver

Figure 2B. CLK/nCLK Input Driven by a 

3.3V LVPECL Driver

Figure 2C. CLK/nCLK Input Driven by a 

3.3V LVPECL Driver

Figure 2D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

3.3V

2.5V

3.3V

2.5V

120Ω

*R3

*R4

CLK

Zo = 60Ω

CLK

nCLK

Differential

Input

nCLK

HCSL

Differential

Input

SSTL

120Ω

Figure 2E. CLK/nCLK Input Driven by a 

3.3V HCSL Driver

Figure 2F. CLK/nCLK Input Driven by a 

2.5V SSTL Driver

Revision B, February 18, 2016

85311I Datasheet

Recommendations for Unused Output Pins

Outputs:

LVPECL Outputs

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

3.3V

125

3.3V

Z_o= 50

Input

Z_o= 50

84

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

Revision B, February 18, 2016

85311I Datasheet

Termination for 2.5V LVPECL Outputs

Figure 4A and Figure 4B show examples of termination for 2.5V

LVPECL driver. These terminations areequivalent to terminating 50

to V_CC– 2V. For V_CC= 2.5V, the V_CC– 2V is very close to ground

level. The R3 in Figure 4B can be eliminated and the termination is

shown in Figure 4C.

2.5V

V_CC= 2.5V

2.5V

V_CC= 2.5V

50Ω

250Ω

50Ω

–

2.5V LVPECL Driver

50Ω

2.5V LVPECL Driver

62.5Ω

18Ω

Figure 4A. 2.5V LVPECL Driver Termination Example

Figure 4B. 2.5V LVPECL Driver Termination Example

2.5V

V_CC= 2.5V

50Ω

–

2.5V LVPECL Driver

50Ω

Figure 4C. 2.5V LVPECL Driver Termination Example

Revision B, February 18, 2016

85311I Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 85311I. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 85311I is the sum of the core power plus the power dissipated in the load(s). 

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 25mA = 86.6mW

Power (outputs)_MAX= 30mW/Loaded Output pair

If all outputs are loaded, the total power is 2 * 30mW = 60mW

Total Power__MAX(3.3V, with all outputs switching) = 86.6mW + 60mW = 146.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature for devices is 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 103°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.147W * 103°C/W = 100.1°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 5. Thermal Resistance _JAfor 8 Lead SOIC, Forced Convection

_JAvs. Air Flow

Linear Feet per Minute

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

103°C/W

94°C/W

89°C/W

Revision B, February 18, 2016

85311I Datasheet

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in Figure 5.

V_CC

V_OUT

V_CC- 2V

Figure 5. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of

V_CC– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CC_MAX}– 0.9V

(V_{CC_MAX}– V_{OH_MAX}) = 0.9V

For logic low, V_OUT= V_{OL_MAX}= V_{CC_MAX}– 1.7V

(V_{CC_MAX}– V_{OL_MAX}) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX –}(V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) = [(2V – (V_{CC_MAX}– V_{OH_MAX}))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) =

[(2V – 0.9V)/50] * 0.9V = 19.8mW

Pd_L = [(V_{OL_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) = [(2V – (V_{CC_MAX}– V_{OL_MAX}))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) =

[(2V – 1.7V)/50] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

Revision B, February 18, 2016

85311I Datasheet

Reliability Information

Table 6. _JAvs. Air Flow Table for a 8 Lead SOIC

_JAby Velocity

Linear Feet per Minute

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

103°C/W

94°C/W

89°C/W

Transistor Count

The transistor count for 85311I is: 225

Package Outline and Package Dimensions

Package Outline - M Suffix for 8 Lead SOIC

Table 7. Package Dimensions

All Dimensions in Millimeters

Symbol

Minimum

Maximum

1.35

0.10

0.33

0.19

4.80

3.80

1.75

0.25

0.51

0.25

5.00

4.00

1.27 Basic

5.80

0.25

0.40

0°

6.20

0.50

1.27

8°



Reference Document: JEDEC Publication 95, MS-012

Revision B, February 18, 2016

85311I Datasheet

Ordering Information

Table 8. Ordering Information

Part/Order Number

85311AMILF

Marking

Package

Shipping Packaging

Tube

Temperature

-40C to 85C

85311AIL

“Lead-Free” 8 Lead SOIC

85311AMILFT

Tape & Reel

Revision B, February 18, 2016

85311I Datasheet

Revision History Sheet

Rev

Table

Page

Description of Change

Date

General Description - deleted HiperClockS logo.

Ordering Information Table - deleted table note.

Deleted HiperClockS references throughout the datasheet.

Updated datasheet header/footer.

2/16/16

Revision B, February 18, 2016

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www.IDT.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether

express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or

other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as

those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any

circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

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85311AMILF [IDT]

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