853S6111AYILF_技术文档

Low Voltage, 1-to-10, Differential-to- 2.5V,

3.3V LVPECL/ECL Fanout Buffer

ICS853S6111I

DATA SHEET

Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)

General Description

Features

The ICS853S6111I is a low skew 1-to-10 Differential Fanout Buffer,

designed with clock distribution in mind, accepting two clock sources

into an input MUX. The MUX is controlled by a CLK_SEL pin. This

makes the ICS853S6111I very versatile, in that, it can operate as

both a differential clock buffer as well as a signal-level translator and

fanout buffer.

• Ten differential LVPECL/ECL outputs

• Two selectable differential input pairs

• PCLK, nPCLK pair can accept the following

differential input levels: LVPECL, LVDS, SSTL, CML

• CLK, nCLK pair can accept the following

differential input levels: HSTL, LVPECL, LVDS, SSTL, HCSL

The device is designed on a SiGe process and can operate up to

frequencies of 2.7GHz. This ensures negligible jitter introduction to

the timing budget which makes it an ideal choice for distributing high

frequency, high precision clocks across back planes and boards in

communication systems. Internal temperature compensation

guarantees consistent performance across various platforms.

• Maximum input frequency: 2.7GHz

• Output skew: 35ps (maximum)

• Part-to-part skew: 250ps (maximum), f_o> 1.5GHz

• Additive phase jitter, RMS: 0.123ps (typical)

• LVPECL and HSTL mode operating voltage supply range:

V_CC= 2.5V 5ꢀ or 3.3V 5ꢀ, V_EE= 0V

• ECL mode operating voltage supply range:

V_EE= -3.3V 5ꢀ or -2.5V 5ꢀ, V_CC= 0V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

Block Diagram

Pin Assignment

Pulldown

PCLK

0

1

Pullup/Pulldown

Q0

nPCLK

24 23 22 21 20 19 18 17

nQ0

Pulldown

CLK

25

26

27

28

29

30

31

32

VCC

16

15

14

13

12

Pullup/Pulldown

nCLK

Q1

nQ2

Q2

Q7

nQ1

Pulldown

nQ7

Q8

CLK_SEL

V_BB

Q2

nQ1

Q1

nQ2

nQ8

nQ3

nQ0

Q0

Q9

11

10

9

nQ9

VCC

Q4

VCC

1

2

3

4

5

6

7

8

nQ4

Q5

nQ5

Q6

ICS853S6111I

32-Lead TQFP, E-Pad

nQ6

Q7

7mm x 7mm x 1mm package body

Y Package

nQ7

nQ8

Top View

Q9

nQ9

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Table 1. Pin Descriptions

Number

Name

Type

Description

1, 9, 16,

25, 32

V_CC

Power

Positive supply pins.

Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW, selects

PCLK, nPCLK inputs. Single-ended LVPECL interface levels.

2

3

4

CLK_SEL

PCLK

Input

Pulldown

Pulldown Non-inverting differential LVPECL and other differential clock inputs.

Pullup/

nPCLK

Inverting differential LVPECL and other differential clock inputs.

Pulldown

5

6

V_BB

Output

Input

Bias voltage to be connected for single-ended applications.

CLK

Pulldown Non-inverting differential HSTL and other differential clock inputs..

Pullup/

7

nCLK

Input

Inverting differential HSTL and other differential clock inputs.

Pulldown

8

V_EE

Power

Output

Negative supply pin.

10, 11

12, 13

14, 15

17, 18

19, 20

21, 22

23, 24

26, 27

28, 29

30, 31

Differential output pair. LVPECL/ECL interface levels.

nQ9, Q9

nQ8, Q8

nQ7, Q7

nQ6, Q6

nQ5, Q5

nQ4, Q4

nQ3, Q3

nQ2, Q2

nQ1, Q1

nQ0, Q0

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

R_PULLDOWNInput Pulldown Resistor

R_VCC/2Pullup/Pulldown Resistors

Parameter

Test Conditions

Minimum

Typical

75

Maximum

Units

k

50

k

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Function Tables

Table 3A. Clock Input Function Table

Inputs

Outputs

nQ0:nQ9

PCLK or CLK

nPCLK or nCLK

Q0:Q9

LOW

HIGH

LOW

HIGH

LOW

Input to Output Mode

Differential to Differential

Single-Ended to Differential

Polarity

Non-Inverting

Inverting

0

1

HIGH

LOW

HIGH

LOW

HIGH

1

0

Biased; NOTE 1

1

Biased; NOTE 1

0

1

Inverting

NOTE 1: Please refer to the Applications Information section, Wiring the Differential Input to Accept Single-ended Levels.

Table 3B. Control Input Function Table

Inputs

CLK_SEL

0 (default)

1

Selected Source

PCLK, nPCLK is active.

CLK, nCLK is active.

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

Inputs, V_I

3.6V

-0.3V to V_CC+ 0.3V

20mA

Outputs, V_O

Input Current, I_IN

Outputs, I_O

Continuos Current

50mA

Operating Temperature Range, T_A

Package Thermal Impedance, _JA

Storage Temperature, T_STG

-40C to +85C

40.2C/W (0 mps)

-65C to 125C

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

DC Electrical Characteristics

Table 5A. LVPECL (PCLK, nPCLK), HSTL (CLK, nCLK) DC Characteristics, V_CC= 3.3V 5ꢀ or 2.5V 5ꢀ; V_EE= 0V,

T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

V_IN= V_ILor V_IN= V_IH

Minimum

Typical

Maximum

Units

Control Input CLK_SEL

V_IL

V_IH

I_IN

Input Low Voltage

V_CC- 1.810

V_CC- 1.165

V_CC- 1.475

V_CC- 0.880

100

V

Input High Voltage

Input Current; NOTE 1

µA

Clock Input Pair PCLK, nPCLK

V_PP

V_CMR

I_IN

Differential Input Voltage; NOTE 2

0.1

1.0

1.3

V_CC- 0.3

100

V

Differential Cross Point Voltage; NOTE 3

Input Current; NOTE 1

µA

Clock Input Pair CLK, nCLK

V_DIF

V_X

Differential Input Voltage; NOTE 4, 7

0.4

0

1.0

V_CC- 1.1

200

V

Differential Crosspoint Voltage; NOTE 5

Input Current

0.68 - 0.9

I_IN

V_IN= V_x0.2V

I_OH= -30mA

µA

PECL Clock Outputs

V_OHOutput High Voltage; NOTE 6

V_CC- 1.2

V_CC- 1.9

V_CC- 1.005

V_CC- 1.705

V_CC- 0.7

V_CC- 1.5

V

V_CC= 3.3V 5ꢀ,

I_OL= -5mA

V_OL

Output Low Voltage; NOTE 6

V_CC= 2.5V 5ꢀ,

_OL= -5mA

V_CC- 1.9

V_CC- 1.705

V_CC- 1.3

V

I

Supply Current and V_BB

Maximum Quiescent Supply Current

without Output Termination Current

I_EE

V

_EEpin

100

mA

V

V_BB

Output Reference Voltage

I_BB= 200µA

V_CC- 1.4

V_CC- 1.2

NOTE 1: Inputs have internal pullup/pulldown resistors which affect the input current.

NOTE 2: V_PP(DC) is the minimum differential input voltage swing required to maintain device functionality.

NOTE 3: V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMR

(DC) range and the input swing lies within the V_PP(DC) specification.

NOTE 4: V_DIF(DC) is the minimum differential HSTL input voltage swing required for device functionality.

NOTE 5: V_X(DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the V_X

(DC) range and the input swing lies within the V_PP(DC) specification.

NOTE 6: Equivalent to a termination of 50 to V_TTequal to V_CC/2.

NOTE 7: For single-ended applications, the maximum input voltage for PCLK, nPCLK and CLK, nCLK is V_CC+ 0.3V.

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Table 5B. ECL (PCLK, nPCLK), HSTL (CLK, nCLK) DC Characteristics, V_EE= -2.5V 5ꢀ or -3.3V 5ꢀ; V_CC= 0V,

T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Control Input CLK_SEL

V_IL

V_IH

I_IN

Input Low Voltage

-1.810

-1.165

-1.475

-0.880

100

V

Input High Voltage

Input Current; NOTE 1

V_IN= V_ILor V_IN= V_IH

µA

Clock Input Pair PCLK, nPCLK; CLK, nCLK

V_PP

V_CMR

I_IN

Peak-to-Peak Input Voltage; NOTE 2

Common Mode Input Voltage; NOTE 3

Input Current; NOTE 1

0.1

1.3

-0.3

100

V

V_EE+ 1.0

V_IN= V_ILor V_IN= V_IH

I_OH= -30mA

µA

ECL Clock Outputs

V_OHOutput High Voltage; NOTE 4

-1.2

-1.9

-1.005

-1.705

-0.7

-1.5

V

_CC= 3.3V 5ꢀ,

_OL= -5mA

I

V_OL

Output Low Voltage; NOTE 4

V_CC= 2.5V 5ꢀ,

_OL= -5mA

-1.9

-1.705

-1.3

V

I

Supply Current and V_BB

Maximum Quiescent Supply Current

without Output Termination Current

I_EE

V

_EEpin

100

mA

V

V_BB

Output Reference Voltage

I_BB= 200µA

V_CC- 1.4

V_CC- 1.2

NOTE 1: Inputs have internal pullup/pulldown resistors which affect the input current.

NOTE 2: V_PP(DC) is the minimum differential input voltage swing required to maintain device functionality.

NOTE 3: V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMR

(DC) range and the input swing lies within the V_PP(DC) specification.

NOTE 4: Equivalent to a termination of 50 to V_TTequal to V_CC/2.

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

AC Electrical Characteristics

Table 6. AC Characteristics, (HSTL, LVPECL): V_CC= 3.3V 5ꢀ or 2.5V 5ꢀ; V_EE= 0V; or

(ECL): V_EE= -3.3V 5ꢀ or -2.5V 5ꢀ; V_CC= 0V; T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_PP

Differential Input Voltage; NOTE 1

PCLK, nPCLK

0.15

1.3

V

Differential Input Crosspoint

Voltage; NOTE 2

V_CMR

PCLK, nPCLK

V_EE+ 1.0

V_CC- 0.3

V

f_CLK

t_PD

Input Frequency; NOTE 3

2.7

530

1.0

GHz

ps

Propagation Delay; NOTE 4

Differential Input Voltage; NOTE 5

280

0.4

400

V_DIF

CLK, nCLK

V

Differential Input Crosspoint

Voltage; NOTE 6

V_EE+ 0.68

_EE+ 0.9

V_X

V

_EE+ 0.1

V_EE+ 2.1

V

f_o< 300MHz

f_o< 1.5GHz

f_o< 2.7GHz

0.45

0.3

0.72

0.95

35

V

Differential Output Voltage

(peak-to-peak)

V_O(pp)

0.55

V

0.18

0.37

V

tsk(o)

tsk(pp)

tsk(p)

Output Skew; NOTE 7, 8

ps

f_o< 1.5GHz

f_o> 1.5GHz

150

250

75

Part-to-Part Skew; NOTE 7, 9

Output Pulse Skew; NOTE 10

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

Section

PCLK, nPCLK, 155.52MHz @3.3V,

Integration Range: (12kHz - 20MHz)

tjit

0.123

ps

ns

t_R/ t_F

Output Rise/Fall Time

20ꢀ to 80ꢀ

0.05

0.3

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: AC characteristics apply for parallel output termination of 50 to V_TTequal to V_CC/2.

NOTE 1: V_PP(AC) is the minimum differential ECL/LVPECL input voltage swing required to maintain AC characteristics including t_PDand

device-to-device skew.

NOTE 2: V_CMR(AC) is the crosspoint of the differential ECL/LVPECL input signal. Normal AC operation is obtained when the crosspoint is

within the V_CMRrange and the input swing lies within the V_PP(AC) specification. Violation of V_CMR(AC) or V_PP(AC) impacts the device

propagation delay, device and part-to-part skew.

NOTE 3: The ICS853S6111I is fully operational up to 3GHz and is characterized up to 2.7GHz.

NOTE 4: Measured from the differential input crossing point to the differential output crossing point.

NOTE 5: V_DIF(AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including t_PDand

device-to-device skew.

NOTE 6: V_Xis the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the V_Xrange

and the input swing lies within the V_DIFspecification. Violation of V_Xor V_DIFimpacts the device propgation delay, device and part-to-part skew.

NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 8: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 9: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

NOTE 10: Output pulse skew is the absolute value of the difference of the propagation delay times: t_PLH- t_PHL.

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Additive Phase Jitter @ 155.52MHz

12kHz to 20MHz = 0.123ps (typical)

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal

Generator as external input to an Agilent 8133A 3GHz Pulse

Generator".

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information

2V

SCOPE

V_CC

Qx

V_CC

Qx

nQx

V_EE

-1.3V 0.165V

-0.5V 0.125V

3.3V LVPECL Output Load AC Test Circuit

2.5V LVPECL Output Load AC Test Circuit

V

CC

nPCLK

nCLK

V_IN

Cross Points

PCLK

CLK

V_CMR

V_DIF

V

EE

PCLK, nPCLK Differential Input Level

CLK, nCLK Differential Input Level

Part 1

nQx

Qx

Part 2

nQy

Qy

tsk(o)

tsk(pp)

Part-to-Part Skew

Output Skew

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Parameter Measurement Information, continued

nCLK,

nPCLK

nQ[0:9]

Q[0:9]

80ꢀ

t_F

80ꢀ

t_R

V_O(PP)

20ꢀ

CLK, PCLK

20ꢀ

nQ[0:9]

Q[0:9]

t_PD

Propagation Delay

Output Rise/Fall Time

Applications Information

Recommendations for Unused Output Pins

Inputs:

Outputs:

PCLK/nPCLK Inputs

LVPECL Outputs

For applications not requiring the use of a differential input, both the

PCLK and nPCLK pins can be left floating. Though not required, but

for additional protection, a 1k resistor can be tied from PCLK to

ground.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

CLK/nCLK Intputs

For applications not requiring the use of a differential input, both the

CLK and nCLK pins can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK to ground.

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V_REF= V_CC/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the V_REFin the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_CC= 3.3V,

R1 and R2 value should be adjusted to set V_REFat 1.25V. The values

below are for when both the single ended swing and V_CCare at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

Wiring the Differential Input to Accept Single-ended LVPECL Levels

Figure 2 shows an example of the differential input that can be wired

to accept single-ended LVPECL levels. The reference voltage level

V

CC

V_BBgenerated from the device is connected to the negative input.

The C1 capacitor should be located as close as possible to the input

pin.

C1

0.1uF

CLK_IN

PCLK

VBB

nPCLK

Figure 2. Single-Ended LVPECL Signal Driving

Differential Input

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

3.3V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other

differential signals. Both signals must meet the V_PPand V_CMRinput

requirements. Figures 3A to 3F show interface examples for the

PCLK/ nPCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

3.3V

o

= 50Ω

3.3V

PCLK

R1

100Ω

nPCLK

LVPECL

Input

CML Built-In Pullup

LVPECL

Input

CML

Figure 3B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 3A. PCLK/nPCLK Input Driven by a CML Driver

3.3V

R3

R4

125Ω

C1

C2

o

= 50Ω

3.3V LVPECL

o = 50Ω

PCLK

VBB

nPCLK

LVPECL

nPCLK

Input

LVPECL

Input

R5

R6

R1

50Ω

R2

50Ω

LVPECL

100Ω - 200Ω 100Ω - 200Ω

R1

R2

84Ω

Figure 3D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

Figure 3C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

2.5V

3.3V

2.5V

3.3V

o

= 50Ω

PCLK

R1

100Ω

nPCLK

LVPECL

Input

SSTL

LVPECL

Input

LVDS

Figure 3E.PCLK/nPCLK Input Driven by an SSTL Driver

Figure 3F. PCLK/nPCLK Input Driven by a

3.3V LVDS Driver

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ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

2.5V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other

differential signals. Both signals must meet the V_PPand V_CMRinput

requirements. Figures 4A to 4F show interface examples for the

PCLK/ nPCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

3.3V

2.5V

3.3V

o

= 50Ω

3.3V

PCLK

R1

100Ω

nPCLK

LVPECL

Input

nPCLK

CML Built-In Pullup

LVPECL

CML

Input

Figure 4B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 4A. PCLK/nPCLK Input Driven by a CML Driver

2.5V

R3

R4

250Ω

C1

C2

o

= 50Ω

2.5V LVPECL

o = 50Ω

PCLK

VBB

nPCLK

LVPECL

Input

R5

R6

R1

50Ω

R2

50Ω

LVPECL

100Ω - 200Ω 100Ω - 200Ω

R1

R2

62.5Ω

Figure 4D. PCLK/nPCLK Input Driven by a

Figure 4C. PCLK/nPCLK Input Driven by a

2.5V LVPECL Driver

2.5V LVPECL Driver with AC Couple

2.5V

R3

R4

o

= 50Ω

120Ω

o

= 60Ω

PCLK

R1

100Ω

nPCLK

LVPECL

Input

SSTL

LVPECL

Input

LVDS

R1

R2

120Ω

Figure 4E.PCLK/nPCLK Input Driven by an SSTL Driver

Figure 4F. PCLK/nPCLK Input Driven by a

2.5V LVDS Driver

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

12

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and

other differential signals. Both differential signals must meet the V_PP

and V_CMRinput requirements. Figures 5A to 5F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 5A, the input

termination applies for IDT open emitter HSTL drivers. If you are

using an HSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

o

= 50Ω

CLK

o = 50Ω

CLK

nCLK

o = 50Ω

Differential

Input

LVPECL

nCLK

R1

50Ω

R2

50Ω

Differential

Input

HSTL

R1

50Ω

R2

50Ω

IDT

HSTL Driver

R2

50Ω

Figure 5A. CLK/nCLK Input Driven by an IDT Open

Emitter HSTL Driver

Figure 5B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

3.3V

R3

R4

3.3V

125Ω

o = 5 0Ω

o = 50Ω

CLK

R1

100Ω

nCLK

Differential

Input

o = 5 0Ω

LVPECL

Receiver

LVDS

R1

84Ω

R2

84Ω

Figure 5C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 5D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

2.5V

3.3V

2.5V

R3

R4

120Ω

o = 50 Ω

*R3

*R4

33Ω

o

= 60Ω

CLK

o = 50 Ω

nCLK

Differential

Input

Differential

Input

SSTL

HCSL

R1

50Ω

R2

50Ω

R1

120Ω

R2

120Ω

*Optional – R3 and R4 can be 0Ω

Figure 5E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 5F. CLK/nCLK Input Driven by a SSTL Driver

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

13

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

2.5V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and

other differential signals. Both differential signals must meet the V_PP

and V_CMRinput requirements. Figures 6A to 6F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 6A, the input

termination applies for IDT open emitter HSTL drivers. If you are

using an HSTL driver from another vendor, use their termination

recommendation.

2.5V

1.8V

o

= 50

CLK

o = 50Ω

CLK

nCLK

o = 50Ω

Differential

Input

LVPECL

nCLK

R1

50

R2

50

Differential

Input

HSTL

R1

50Ω

R2

50Ω

IDT Open Emitter

HSTL Driver

R3

18

Figure 6A. CLK/nCLK Input Driven by an IDT Open

Emitter HSTL Driver

Figure 6B. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

2.5V

R3

R4

2.5V

250

o

= 50

o = 50

CLK

R1

100

nCLK

Differential

Input

LVPECL

Differential

Input

R1

62.5

R2

62.5

LVDS

Figure 6C. CLK/nCLK Input Driven by a

2.5V LVPECL Driver

Figure 6D. CLK/nCLK Input Driven by a 2.5V LVDS Driver

2.5V

R5

R7

120Ω

o = 50

*R3

*R4

33

o

= 60Ω

CLK

o = 50

nCLK

Differential

Input

Differential

Input

SSTL

HCSL

R1

50

R2

50

R6

120Ω

R8

120Ω

*Optional – R3 and R4 can be 0

Figure 6E. CLK/nCLK Input Driven by a

2.5V HCSL Driver

Figure 6F. CLK/nCLK Input Driven by a SSTL Driver

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

14

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 7A and 7B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

3.3V

R3

125Ω

R4

125Ω

3.3V

_o= 50Ω

+

3.3V

_o= 50Ω

+

_

Input

LVPECL

_o= 50Ω

LVPECL

Input

_o= 50Ω

R1

R2

50Ω

R1

84Ω

R2

84Ω

V_CC- 2V

1

RTT =

*

RTT

o

((V_OH+ V_OL) / (V_CC– 2)) – 2

Figure 7A. 3.3V LVPECL Output Termination

Figure 7B. 3.3V LVPECL Output Termination

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

15

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Termination for 2.5V LVPECL Outputs

Figure 8A and Figure 8B show examples of termination for 2.5V

LVPECL driver.These terminations are equivalent to terminating 50

to V_CC– 2V. For V_CC= 2.5V, the V_CC– 2V is very close to ground

level. The R3 in Figure 9B can be eliminated and the termination is

shown in Figure 9C.

2.5V

V_CC= 2.5V

2.5V

V_CC= 2.5V

50Ω

R1

R3

250Ω

+

50Ω

+

–

2.5V LVPECL Driver

R1

R2

50Ω

2.5V LVPECL Driver

R2

R4

62.5Ω

R3

18Ω

Figure 8A. 2.5V LVPECL Driver Termination Example

Figure 8B. 2.5V LVPECL Driver Termination Example

2.5V

V_CC= 2.5V

50Ω

+

50Ω

–

2.5V LVPECL Driver

R1

R2

50Ω

Figure 8C. 2.5V LVPECL Driver Termination Example

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

16

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 9. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

LAND PATTERN

(GROUND PAD)

PIN PAD

GROUND PLANE

PIN PAD

THERMAL VIA

Figure 9. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

17

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS853S6111I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS853S6111I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 100mA = 346.5mW

Power (outputs)_MAX= 33.2mW/Loaded Output pair

If all outputs are loaded, the total power is 10 * 33.2mW = 332mW

Total Power__MAX(3.465V, with all outputs switching) = 346.5W + 332mW = 678.5W

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature



_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 40.2°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.679 W * 40.2°C/W = 112.3°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance _JAfor 32 Lead TQFP, EPad, Forced Convection



_JAby Velocity

0

Meters per Second

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

40.2°C/W

35.1°C/W

33.9°C/W

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

18

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 10.

V_CC

Q1

V_OUT

RL

V_CC- 2V

Figure 10. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of

V_CC– 2V.

•

For logic high, V_OUT= V_{OH_MAX}= V_{CC_MAX}– 0.7V

(V_{CC_MAX}– V_{OH_MAX}) = 0.7V

For logic low, V_OUT= V_{OL_MAX}= V_{CC_MAX}– 1.5V

(V_{CC_MAX}– V_{OL_MAX}) = 1.5V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) = [(2V – (V_{CC_MAX}– V_{OH_MAX}))/R_L] * (V_{CC_MAX}– V_{OH_MAX}) =

[(2V – 0.7V)/50] * 0.7V = 18.2mW

Pd_L = [(V_{OL_MAX}– (V_{CC_MAX}– 2V))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) = [(2V – (V_{CC_MAX}– V_{OL_MAX}))/R_L] * (V_{CC_MAX}– V_{OL_MAX}) =

[(2V – 1.5V)/50] * 1.5V = 15mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

19

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Reliability Information

Table 8. _JAvs. Air Flow Table for a 32 Lead TQFP, E-Pad



_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

40.2°C/W

35.1°C/W

33.9°C/W

Transistor Count

The transistor count for ICS853S6111I is: 450

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

20

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Package Outline and Package Dimensions

Package Outline - G Suffix for 32 Lead TQFP, E-Pad

-HD VERSION

EXPOSED PAD DOWN

0.20

TAB

-TAB, EXPOSED PART OF CONNECTION BAR OR TIE BAR

Table 9. Package Dimensions 32 Lead TQFP, E-Pad

JEDEC Variation: ABC - HD

All Dimensions in Millimeters

Symbol

Minimum

Nominal

Maximum

N

32

A

1.20

0.15

1.05

0.40

0.20

A1

0.05

0.95

0.30

0.09

0.10

1.00

0.35

A2

b

c

D & E

D1 & E1

D2 & E2

D3 & E3

e

9.00 Basic

7.00 Basic

5.60 Ref.

3.0

4.0

0.80 Basic

0.60

L

0.45

0°

0.75

7°



ccc

0.10

Reference Document: JEDEC Publication 95, MS-026

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

21

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Ordering Information

Table 10. Ordering Information

Part/Order Number

853S6111AYILF

853S6111AYILFT

Marking

ICS3S6111AIL

Package

“Lead-Free” 32 Lead TQFP, E-Pad

Shipping Packaging

Tube

Temperature

-40C to 85C

Tape & Reel

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

22

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

Revision History Sheet

Rev

Table

Page

Description of Change

Product Discontinuance Notice – Last Time Buy Expires on (1/31/2014)

Date

5

1

2/6/2013

ICS853S6111AYI REVISION A FEBRUARY 6, 2013

23

ICS853S6111I Data Sheet

LOW VOLTAGE, 1-TO-10 DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER

We’ve Got Your Timing Solution

6024 Silver Creek Valley Road Sales

Technical Support

netcom@idt.com

800-345-7015 (inside USA)

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Fax: 408-284-2775

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www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-

cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.


型号：	853S6111AYILF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PTQFP-32, Tray 驱动逻辑集成电路
文件：	总24页 (文件大小：431K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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