85401AKLFT [IDT]
Multiplexer, 85401 Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, 3 X 3 MM, 0.95 MM HEIGHT, LEAD FREE, MO-220, VQFN-16;
| 型号： | 85401AKLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multiplexer, 85401 Series, 1-Func, 2 Line Input, 1 Line Output, Complementary Output, 3 X 3 MM, 0.95 MM HEIGHT, LEAD FREE, MO-220, VQFN-16 逻辑集成电路 |
| 文件： | 总16页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ICS85401
Description
Features
The ICS85401 is a high performance 2:1
• 2:1 LVDS MUX
S
IC
Differential-to-LVDS Multiplexer and a member of
the HiPerClockS™family of High Performance Clock
Solutions from ICS. The ICS85401 can also perform
differential translation because the differ-ential
• One LVDS output pair
HiPerClockS™
• Two differential clock inputs can accept: LVPECL, LVDS, CML
• Maximum input/output frequency: 2.5GHz
inputs accept LVPECL, CML as well as LVDS levels.
The ICS85401 is packaged in a small 3mm x 3mm
16 VFQFN package, making it ideal for use on space constrained
boards.
• Translates LVCMOS/LVTTL input signals to LVDS levels by
using a resistor bias network on nCLK0, nCLK1
• Propagation delay: 460ps (maximum)
• Part-to-part skew: 100ps (maximum)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Pulldown
CLK0
0
Pullup/Pulldown
CLK0
Q
Q
16 15 14 13
1
2
3
CLK0
CLK0
CLK1
CLK1
12
11
10
GND
Q
Pulldown
CLK1
Pullup/Pulldown
1
CLK1
Q
4
GND
9
5
6
7
8
Pulldown
CLK_SEL
ICS85401
16-Lead VFQFN
3mm x 3mm x 0.95mm
package body
K Package
Top View
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Table 1. Pin Descriptions
Number
Name
Type
Description
1
CLK0
Input
Input
Pulldown Non-inverting differential clock input.
Pullup/
2
CLK0
CLK1
CLK1
nc
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
3
4
Input
Pulldown Non-inverting differential clock input.
Pullup/
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
5, 7, 16
Unused
No connect.
Clock select input. When HIGH, selects CLK1, CLK1 inputs.
Pulldown When LOW, selects CLK0, CLK0 inputs.
LVCMOS / LVTTL interface levels.
6
CLK_SEL
Input
8, 13
9, 12, 14, 15
10, 11
VDD
GND
Q, Q
Power
Power
Output
Power supply pins.
Power supply ground.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to intenal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
1
RPULLUP
37
37
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Function Tables
Table 3. Control Input Function Table
Input
CLK_OUT
CLK
CLK_SEL
0
1
CLK0, CLK0
CLK1, CLK1
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
51.5°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
40
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.8
Units
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
2
VIL
-0.3
V
IIH
CLK_SEL
CLK_SEL
VDD = VIN = 3.465V
150
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-150
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
150
Units
µA
CLK0, CLK1
CLK0, CLK
VDD = VIN = 3.465V
IIH
Input High Current
VDD = VIN = 3.465V
150
µA
V
DD = 3.465V,
CLK0, CLK1
CLK0, CLK
-150
-150
µA
µA
VIN = 0V
IIL
Input Low Current
VDD = 3.465V,
VIN = 0V
VPP
Peak-to-Peak Voltage
0.15
1.2
0.8
1.2
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VDD
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single-ended applications, the maximum input voltage for CLKx, CLKx is VDD + 0.3V.
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Table 4D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
500
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
350
∆VOD
VOS
50
1.05
1.15
1.25
50
∆VOS
VOS Magnitude Change
mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40°C to 85°C
Parameter
fMAX
Symbol
Test Conditions
Minimum Typical Maximum
Units
Output Frequency
>2.5
GHz
ps
tPD
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
260
360
160
-55
460
100
200
51
tsk(pp)
tR / tF
odc
ps
20% to 80%
125
49
ps
%
MUX_ISOLATION MUX Isolation
All parameters measured at £ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.Typical Phase Noise at 156.25MHz
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Parameter Measurement Information
V
DD
,
SCOPE
CLK0,
CLK1
Qx
V
DD
3.3V 5%
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
LVDS
CLK0,
CLK1
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
CLK0,
CLK1
Qx
Part 1
Qx
CLK0,
CLK1
Q
Qy
Part 1
Q
Qy
tPD
tsk(pp)
Part-to-Part Skew
Propagation Delay
Q
Q
tPW
80%
tF
80%
tPERIOD
VOD
Clock
20%
20%
tPW
Outputs
odc =
x 100%
tR
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
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Parameter Measurement Information, continued
VDD
VDD
out
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
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Differential Clock Input Interface
The CLKx /CLKx accepts LVPECL, LVDS, CML and other
differential signals. The signal must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
HiPerClockS CLKx/CLKx input driven by the most common driver
types. The input interfaces suggested here are examples only. If
the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
R1
50
R2
50
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
Zo = 50Ω
nCLK
HiPerClockS
CML Built-In Pullup
HiPerClockS
CML
Figure 2A. HiPerClockS CLK/CLK Input Driven by an
IDT Open Collector CML Driver
Figure 2B. HiPerClockS CLK/CLK Input
Driven by a Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
125
125
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
Figure 2C. HiPerClockS CLK/CLK Input
Figure 2D. HiPerClockS CLK/CLK Input Driven by
a 3.3V LVPECL Driver with AC Couple
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
Zo = 50Ω
CLK
R1
100
nCLK
Zo = 50Ω
HiPerClockS
LVDS
Figure 2E. HiPerClockS CLK/CLK Input Driven by
a 3.3V LVDS Drive
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2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Recommendations for Unused Input Pins
Inputs:
CLK/CLK Inputs:
For applications not requiring the use of the differential input, both
CLK and CLK can be left floating. Though not required, but for
additional protection, a 1kW resistor can be tied from CLK to
ground.
Application Schematic Example
Figure 3 shows an example of ICS85401 application schematic.
This device can accept different types of input signal. In this
example, the input is driven by a LVDS driver. The decoupling
capacitor should be located as close as possible to the power pin.
3.3V
C1
0.1u
3.3V
Zo = 50
R2
100
Zo = 50
1
2
3
4
12
11
10
9
Zo = 50
CLK0
GND
Q
nCLK0
CLK1
+
LVDS
nQ
R1
nCLK1
GND
Zo = 50
100
-
3.3V
U1
ICS85401
Zo = 50
3.3V
R3
100
R4
1K
C2
Zo = 50
0.1u
LVDS
Figure 3. ICS85401 Application Schematic Example
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Thermal Release Path
The expose metal pad provides heat transfer from the device to the
P.C. board. The expose metal pad is ground pad connected to
ground plane through thermal via. The exposed pad on the device
to the exposed metal pad on the PCB is contacted through solder
as shown in Figure 4. For further information, please refer to the
Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
Figure 4. P.C. Board for Exposed Pad Thermal Release Path Example
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 5 In a 100Ω differential
transmission line environment, LVDS drivers require a matched
load termination of 100Ω across near the receiver input. For a
multiple LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 5. Tyical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85401.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85401 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 40mA = 138.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.139W * 51.5°C/W = 92.2°C. This iswell below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 16 Lead VFQFN, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
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2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 16 Lead VFQFN
θJA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
Transistor Count
The transistor count for ICS85401 is: 132
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Package Outline and Package Dimension
Package Outline - K Suffix for 16 Lead VFQFN
(Ref.)
Seating Plane
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
OR
(Ref.)
E2
2
TopView
D
b
(Ref.)e
N & N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
16
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
4
3.00 Basic
1.00
0.30
1.80
0.50 Basic
L
0.50
Reference Document: JEDEC Publication 95, MO-220
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2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Ordering Information
Table 9. Ordering Information
Part/Order Number
85401AK
85401AKT
85401AKLF
85401AKLFT
Marking
401A
401A
01AL
01AL
Package
16 Lead VFQFN
16 Lead VFQFN
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS MULTIPLEXER
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Revision History Sheet
Rev
A
Table
Page
8
Description of Change
Date
Add Schematic Layout.
8/23/04
11/17/04
2/22/05
A
T8
10
1
Corrected count in Ordering Information Table.
Pin Assignment - corrected label on pin 2.
A
T8
1
Features section - added Lead-Free bullet.
A
A
11
Ordering Information Table - corrected Shipping Packaging from Tray to
Tube, and added Lead-Free part number and note.
3/14/06
3/6/07
7
10
13
Corrected Differential Clock Input Interface.
Added Power Considerations Section.
Ordering Information Table - added Lead-Free marking.
Updated format throughout the datasheet.
T9
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ICS85401
2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER
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