854210CYT [IDT]
Clock Driver, PQFP32;
| 型号： | 854210CYT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PQFP32 |
| 文件： | 总12页 (文件大小：223K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-
TO-LVDS FANOUT BUFFER
ICS854210
GENERAL DESCRIPTION
FEATURES
The ICS854210 is a low skew, high performance
• Two differential LVDS bank outputs
ICS
dual 1-to-5 Differential-to-LVDS Fanout Buffer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from IDT.
The ICS854210 is characterized to operate
• Two differential LVPECL clock input pairs
HiPerClockS™
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
from a 3.3V power supply. Guaranteed output and part-
to-part skew characteristics make the ICS854210 ideal for
those clock distribution applications demanding well
defined performance and repeatability.
• Maximum output frequency: 2GHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
• Output skew: TBD
• Part-to-part skew: TBD
• Propagation delay: 280ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
QA0
nQA0
24 23 22 21 20 19 18 17
PCLKA Pulldown
nPCLKA Pullup/Pulldown
VDDO
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VDDO
QB2
QA1
nQA2
QA2
nQA1
nQB2
QB3
QA2
nQA2
nQA1
QA1
ICS854210
QA3
nQA3
nQB3
QB4
nQA0
QA0
QA4
nQA4
nQB4
VDDO
VDDO
1
2
3
4
5
6
7
8
QB0
nQB0
PCLKB Pulldown
nPCLKB Pullup/Pulldown
QB1
nQB1
32-Lead LQFP
QB2
7mm x 7mm x 1.4mm package body
nQB2
Y Package
Top View
QB3
nQB3
QB4
nQB4
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS FANOUT BUFFER
1
ICS854210CY REV. C MAY 6, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDD
Type
Description
1
2, 5
3
Power
Power supply pin.
nc
Unused
Input
No connect.
PCLKA
Pulldown Non-inverting differential LVPECL clock input.
Pullup/ Inverting differential LVPECL clock input.
Pulldown VDD/2 default when left floating.
4
6
7
nPCLKA
PCLKB
Input
Input
Input
Pulldown Non-inverting differential LVPECL clock input.
Pullup/ Inverting differential LVPECL clock input.
Pulldown VDD/2 default when left floating.
nPCLKB
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
GND
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power supply ground.
VDDO
Output supply pins.
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical
75
Maximum
Units
kΩ
RPULLDOWN Input Pulldown Resistor
RVDD/2
Pullup/Pulldown Resistors
50
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
QA0:QA4,
QB0:QB4
nQA0:nQA4,
nQB0:nQB4
PCLKA or PCLKB nPCLKA or nPCLKB
0
1
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
LOW
HIGH
LOW
LOW
HIGH
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
IDT™ / ICS™ LVDS FANOUT BUFFER
2
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These rat-
ings are stress specifications only. Functional operation of prod-
uct at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Ex-
posure to absolute maximum rating conditions for extended peri-
ods mayaffect product reliability.
Supply Voltage, VDD
Negative Supply Voltage, VEE
Inputs, VI
4.6V
-4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Power Supply Voltage
3.465
3.465
V
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
TBD
TBD
mA
mA
IDDO
TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum
Typical Maximum Units
PCLKA, PCLKB
nPCLKA, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
150
150
µA
µA
µA
µA
mV
mV
V
-150
-10
IIL
Input Low Current
VTH
VTL
Differential Input High Threshold Voltage
Differential Input Low Threshold Voltage
Peak-to-Peak Input Voltage
100
-100
VPP
VCMR
0.15
Common Mode Input Voltage; NOTE 1, 2
GND + 1.2
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB
is VDD + 0.3V.
IDT™ / ICS™ LVDS FANOUT BUFFER
3
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
-40°C
Typ
25°C
Typ
350
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
50
Min
Max
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.25
Δ VOS
VOS Magnitude Change
50
mV
NOTE 1: Refer to Parameter Measurement Information, "3.3V Output Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
-40°C
25°C
85°C
Symbol Parameter
Units
Min Typ
2
Max Min Typ Max Min Typ Max
fMAX
Output Frequency
2
2
GHz
ps
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
260
280
TBD
TBD
180
305
TBD
TBD
190
tsk(o)
tsk(pp)
tR/tF
TBD
TBD
175
ps
Part-to-Part Skew; NOTE 3, 4
ps
Output Rise/Fall Time
20ꢀ to 80ꢀ
ps
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVDS FANOUT BUFFER
4
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
Qx
VDD,
VDDO
3.3V 5ꢀ
POWER SUPPLY
VPP
VCMR
Cross Points
+
Float GND –
LVDS
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
nQx
PART 1
Qx
nQy
PART 2
Qy
nQy
Qy
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
VDD
VDD
out
out
➤
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
VOS/Δ VOS
➤
VOS SETUP
VOD SETUP
nQAx,
nQBx
nPCLKA,
nPCLKB
80ꢀ
80ꢀ
PCLKA,
PCLKB
VOD
20ꢀ
20ꢀ
nQAx,
nQBx
QAx,
QBx
tF
tR
QAx,
QBx
tPD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVDS FANOUT BUFFER
5
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS
PCLK/nPCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
IDT™ / ICS™ LVDS FANOUT BUFFER
6
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
R1
50
R2
50
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
R4
120
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
IDT™ / ICS™ LVDS FANOUT BUFFER
7
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
3.3V
3.3V
LVDS_Driv er
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ LVDS FANOUT BUFFER
8
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32L LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854210 is: 394
IDT™ / ICS™ LVDS FANOUT BUFFER
9
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 32L LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document:JEDEC Publication 95, MS-026
IDT™ / ICS™ LVDS FANOUT BUFFER
10
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS854210CY
Marking
Package
Shipping Packaging
tray
Temperature
ICS854210CY
ICS854210CY
ICS854210CYL
ICS854210CYL
32 lead LQFP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS854210CYT
ICS854210CYLF
ICS854210CYLFT
32 lead LQFP
1000 tape & reel
tray
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS FANOUT BUFFER
11
ICS854210CY REV. C APRIL 7, 2008
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
For Tech Support
netcom@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
+480-763-2056
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明