855S011AGILFT [IDT]
Low Skew Clock Driver, 855S Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8;
| 型号： | 855S011AGILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 855S Series, 2 True Output(s), 0 Inverted Output(s), PDSO8, 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-187, TSSOP-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：700K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-2, Differential-to-CML
Fanout Buffer
ICS855S011I
DATA SHEET
General Description
Features
The ICS855S011I is a low skew, high performance 1-to-2,
Differential-to-CML Fanout Buffer. The ICS855S011I is
characterized to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and part-to-part skew characteristics make the
ICS855S011I ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Two differential CML outputs
• One differential PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2GHz
• Translates any single ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
• Additive phase jitter, RMS: 0.037ps (typical)
• Output skew: 25ps (maximum)
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 375ps (maximum)
• Operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
Pin Assignment
Q0
VCC
Q0
nQ0
Q1
1
2
3
4
8
7
6
5
Pulldown
nQ0
PCLK
PCLK
nPCLK
VEE
Pullup/Pulldown
nPCLK
Q1
nQ1
nQ1
ICS855S011I
8-Lead TSSOP
3.0mm x 3.0mm x 0.95mm package body
G Package
Top View
ICS855S011AGI REVISION A NOVEMBER 22, 2010
1
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Q0, nQ0
Q1, nQ1
VEE
Type
Description
1, 2
3, 4
5
Output
Output
Power
Input
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Negative supply pin.
6
nPCLK
PCLK
Pullup/Pulldown Inverting LVPECL differential clock input. Default to 2/3 VCC when left floating.
7
Input
Pulldown
Non-inverting LVPECL differential clock input.
Power supply pin.
8
VCC
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
75
Maximum
Units
kΩ
RPULLDOWN
RPULLUP
Input Pulldown Resistor
Input Pullup Resistor
37
kΩ
ICS855S011AGI REVISION A NOVEMBER 22, 2010
2
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.5V (CML mode, VEE = 0V)
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
20mA
40mA
Package Thermal Impedance, θJA
145.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
V
2.375
3.3
3.8
52
mA
Table 3B. LVPECL Differential DC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
PCLK,
nPCLK
IIH Input High Current
VCC = VIN = 2.625V or 3.8V
150
µA
V
CC = 2.625V or 3.8V,
VIN = 0V
PCLK
-10
µA
µA
IIL
Input Low Current
VCC = 2.625V or 3.8V,
VIN = 0V
nPCLK
-150
VPP
Peak-to-Peak Voltage
150
1.2
1200
VCC
mV
V
VCMR
Common Mode Input Voltage; NOTE 1
NOTE 1: Common mode input voltage is defined as VIH.
Table 3C. CML DC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 0.020
325
Typical
VCC - 0.010
400
Maximum
Units
V
Output High Voltage; NOTE 1
Output Voltage Swing
VCC
VOUT
mV
Differential Output Voltage
Swing
VDIFF_OUT
ROUT
650
40
800
50
mV
Output Source Impedance
60
Ω
NOTE 1: Outputs terminated with 50Ω to VCC
.
ICS855S011AGI REVISION A NOVEMBER 22, 2010
3
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics, VCC = 2.375V to 3.8V, VEE = 0V, TA = -40°C to 85°C
Symbol
fOUT
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
Output Frequency
Propagation Delay; NOTE 1
2
tPD
175
375
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
156.25MHz @ 3.3V, Integration Range:
12kHz – 20MHz
tjit
0.037
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
25
200
250
53
ps
ps
ps
%
20% to 80%
60
47
NOTE: All parameters characterized at ≤ 1.2GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: Defined as skew between different devices operating at the same supply voltage, same frequency, same temperature and with equal
load conditions. Using the same type of inputs on each device, the output is measured at the differential cross point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS855S011AGI REVISION A NOVEMBER 22, 2010
4
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz
12kHz to 20MHz = 0.037ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, "Rohde & Schwarz SMA100 through
the Hewlett Packard 8133A Generator".
ICS855S011AGI REVISION A NOVEMBER 22, 2010
5
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Parameter Measurement Information
V
DD
0V
SCOPE
Qx
nPCLK
PCLK
GND
V
CC
EE
Power
VPP
VCMR
Cross Points
Supply
CML Driver
V
-2.375V to -3.63V
Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
nQx
Qx
Qx
Part 2
nQy
nQy
Qy
Qy
tsk(pp)
tsk(o)
Output Skew
Part-to-Part Skew
nQ[0:1]
nPCLK
PCLK
80%
80%
VOUT
20%
20%
Q[0:1]
nQ[0:1]
tF
tR
Q[0:1]
tPD
Output Rise/Fall Time
Propagation Delay
ICS855S011AGI REVISION A NOVEMBER 22, 2010
6
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Parameter Measurement Information, continued
nQ[0:1]
Q[0:1]
VDIFF_OUT
VOUT
tPW
tPERIOD
tPW
Differential Voltage Swing = 2 x Single-ended VIN
odc =
x 100%
tPERIOD
Differential Output Voltage Swing
Output Duty Cycle/Pulse Width/Period
ICS855S011AGI REVISION A NOVEMBER 22, 2010
7
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Applications Information
Recommendations for Unused Output Pins
Outputs:
CML Outputs
All unused CML outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS855S011AGI REVISION A NOVEMBER 22, 2010 ©2010 Integrated Device Technology, Inc.
8
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2F show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
Zo = 50Ω
Zo = 50Ω
PCLK
R1
100Ω
PCLK
nPCLK
Zo = 50Ω
nPCLK
LVPECL
CML Built-In Pullup
Input
LVPECL
Input
CML
Figure 2A. PCLK/nPCLK Input
Figure 2B. PCLK/nPCLK Input
Driven by a CML Driver
Driven by a Built-In Pullup CML Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
3.3V
R3
84
R4
84
Zo = 50Ω
Zo = 50Ω
C1
C2
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL
PCLK
PCLK
nPCLK
nPCLK
LVPECL
Input
LVPECL
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84Ω
R2
84Ω
Figure 2C. PCLK/nPCLK Input
Figure 2D. PCLK/nPCLK Input Driven by
Driven by a 3.3V LVPECL Driver
a 3.3V LVPECL Driver with AC Couple
3.3V
2.5V
3.3V
Zo = 50Ω
3.3V
2.5V
R3
120
R4
120
C1
PCLK
Zo = 60Ω
Zo = 60Ω
R5
100Ω
VBB
C2
PCLK
nPCLK
Zo = 50Ω
LVPECL
Input
LVDS
nPCLK
R1
1k
R2
1k
LVPECL
Input
SSTL
R1
120
R2
120
C3
0.1µF
Figure 2E. PCLK/nPCLK Input
Figure 2F. PCLK/nPCLK Input Driven by
a 3.3V LVDS Driver
Driven by an SSTL Driver
ICS855S011AGI REVISION A NOVEMBER 22, 2010
9
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS855S011I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS855S011I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
Power (core)MAX = VCC_MAX * IEE = 3.8V * 52mA = 197.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 145.4°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.198W * 145.4°C/W = 113.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
145.4°C/W
141.3°C/W
139.3°C/W
ICS855S011AGI REVISION A NOVEMBER 22, 2010
10
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Reliability Information
Table 6. θJA vs. Air Flow Table for a 8 Lead TSSOP
θJA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
145.4°C/W
141.3°C/W
139.3°C/W
Transistor Count
The transistor count for ICS855S011I is: 185
This device is pin and function compatible and a suggested replacement for ICS855011.
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
8
1.10
0.15
0.97
0.38
0.23
A1
A2
b
0.79
0.22
0.08
c
D
3.00 Basic
4.90 Basic
3.00 Basic
0.65 Basic
1.95 Basic
E
E1
e
e1
L
0.40
0°
0.80
8°
α
aaa
0.10
A2
Reference Document: JEDEC Publication 95, MO-187
ICS855S011AGI REVISION A NOVEMBER 22, 2010
11
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
Ordering Information
Table 8. Ordering Information
Part/Order Number
855S011AGILF
855S011AGILFT
Marking
1AIL
1AIL
Package
“Lead-Free” 8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS855S011AGI REVISION A NOVEMBER 22, 2010
12
©2010 Integrated Device Technology, Inc.
ICS855S011I Data Sheet
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-CML FANOUT BUFFER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
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