86004BG [IDT]
Low Skew Clock Driver, PDSO16;
| 型号： | 86004BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, PDSO16 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：1612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
ICS86004
FEATURES
GENERAL DESCRIPTION
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
The ICS86004 is a high performance 1:4
ICS
HiPerClockS™
LVCMOS/LVTTL Clock Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS86004 has a
fully integrated PLL and can be configured as zero
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 15.625MHz to 62.5MHz
• Input frequency range: 15.625MHz to 62.5MHz
• VCO range: 250MHz to 500MHz
delay buffer and has an input and output frequency range of
15.625MHz to 62.5MHz. The VCO operates at a frequency
range of 250MHz to 500MHz. The external feedback allows the
device to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the internal
output divider.
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter: 65ps (maximum)
• Output skew: 65ps (maximum)
• Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply
• 0°C to 70° ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
1
2
3
4
5
6
7
8
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
Q0
÷8, ÷16
PLL
0
1
Q1
Q2
Q3
CLK
1:1
FB_IN
ICS86004
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
MR
F_SEL
IDT™ / ICS™ LVCMOS ZERO DELAY CLOCK BUFFER
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ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 3,
13, 15
Name
Q1, Q0,
Q3, Q2
Type
Output
Description
Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels.
2, 7, 14
GND
Power
Power supply ground.
Frequency range select input. See Table 3A and 3B.
LVCMOS/LVTTL interface levels.
4
F_SEL
Input Pulldown
Power
5
6
8
VDD
CLK
VDDA
Core supply pin.
Input Pulldown LVCMOS/LVTTL clock input.
Power
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
9
PLL_SEL Input
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
10
FB_IN
Input Pulldown
11
MR
Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
12, 16
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
VDD, VDDA, VDDO = 3.465V
VDD, VDDA, VDDO = 2.625V
3.3V 5%
23
17
12
pF
pF
Ω
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
5
7
TABLE 3A. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 1
TABLE 3B. CONTROL INPUT FUNCTION TABLE, PLL_SEL = 0
Input/Output
Input
Input
Output
F_SEL
Frequency Range (MHz)
F_SEL
Minimum
31.25
Maximum
62.5
0
1
Ref ÷8
0
1
Ref ÷16
15.625
31.25
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
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ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage% VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs% V
-0.±V to VDD + 0.± V
-0.±V to VDDO + 0.±V
89°C/W (0 lfpm)
-6±°C to 1±0°C
I
Outputs% VO
Package Thermal Impedance% θ
JA
Storage Temperature% T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±±5% TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.13±
3.13±
3.13±
3.3
3.3
3.3
3.46±
VDD
3.46±
98
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
17
8
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±±5% VDDO = 2.±V±±5% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.13±
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.46±
VDD
2.62±
98
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.13±
3.3
2.37±
2.±
V
mA
mA
mA
IDDA
IDDO
17
8
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.±V±±5% TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
2.37±
Typical
2.±
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.62±
VDD
2.62±
88
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.37±
2.±
2.37±
2.±
V
mA
mA
mA
IDDA
IDDO
14
6
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
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ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5% OR 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
Input Low Voltage
Input High Current
VDD = 2.5V
0.7
CLK, MR,
FB_IN, F_SEL
VDD = VIN = 3.465V
150
5
µA
µA
µA
IIH
PLL_SEL
VDD = VIN = 3.465V
CLK, MR,
FB_IN, F_SEL
VDD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_SEL
V
DD = 3.465V, VIN = 0V
-150
2.6
µA
V
VDDO = 3.465V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.625V
1.8
V
VDDO = 3.465V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagrams.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
31.25
62.5
MHz
MHz
fMAX
Output Frequency
F_SEL = 1
15.625
31.25
PLL_SEL = 0V,
Bypass Mode
tpLH
Propagation Delay, Low-to-High; NOTE 1
4.1
6.1
ns
t(Ø)
tsk(o)
tjit(cc)
tL
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
PLL_SEL = 3.3V
PLL_SEL = 0V
-500
500
65
65
1
ps
ps
ps
mS
ns
%
50
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.4
49
1
51
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
4
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
31.25
62.5
MHz
MHz
fMAX
tpLH
Output Frequency
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 2.5V
PLL_SEL = 0V
15.625
31.25
Propagation Delay, Low-to-High; NOTE 1
4.25
-500
6.25
ns
t(Ø)
tsk(o)
tjit(cc)
tL
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
500
65
65
1
ps
ps
ps
mS
ns
%
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.4
48
1
52
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
31.25
62.5
MHz
MHz
fMAX
tpLH
Output Frequency
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
15.625
31.25
Propagation Delay, Low-to-High; NOTE 1
4.5
6.5
ns
t(Ø)
tsk(o)
tjit(cc)
tL
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
PLL_SEL = 2.5V
PLL_SEL = 0V
-500
500
65
70
1
ps
ps
ps
mS
ns
%
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.4
48
1
52
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
5
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
2.05V 5%
1.25V 5%
SCOPE
SCOPE
VDD,
VDDA, VDDO
VDD,
VDDA
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
VDDO
2
-1.65V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
VDDO
2
VDDO
2
VDDO
2
SCOPE
VDD,
VDDA, VDDO
Q0:Q3
➤
➤
Qx
tcycle n+1
tcycle n
➤
➤
LVCMOS
GND
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
-1.25V 5%
2.5VCORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VDD
2
CLK
VDDO
Qx
Qy
2
VDD
2
FB_IN
➤
VDDO
2
➤
t(Ø)
tsk(o)
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT SKEW
STATIC PHASE OFFSET
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
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ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
VDDO
2
VDDO
2
VDDO
2
80%
tF
80%
tR
Q0:Q3
tPW
20%
20%
tPERIOD
Clock
Outputs
tPW
tPERIOD
odc =
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
2
CLK
VDDO
2
Q0:Q3
t
PD
PROPAGATION DELAY
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
7
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS86004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10 µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an ICS86004. It is
recommended to have one decouple capacitor per power pin.
Each decoupling capacitor should be located as close as possible
to the power pin. The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the
VDDA pin as possible.
R1
43
VDD
Zo = 50
Serial Termination
R3
1K
VDD
U1
R2
43
VDD
1
16
15
14
13
12
11
10
9
Zo = 50
Q1
2
VDDO
Q2
GND
Q3
VDDO
MR
GND
3
Q0
4
F_SEL
VDD
CLK
GND
VDDA
Ro
~ 7 Ohm
5
6
7
8
Zo = 50
VDD
FB_IN
PLL_SEL
R8
43
R11 43
LVCMOS
ICS86004
Zo = 50
R7
10
VDD R6
1K
C16
10u
C11
0.01u
VDD
Parallel Termination
(U1-5)
(U1-12)
(U1-16)
VDD
R4
100
C1
0.1uF
C2
0.1uF
C3
0.1uF
Zo = 50
VDD=3.3V
R5
100
FIGURE 2. ICS86004 SCHEMATIC EXAMPLE
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
8
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
RELIABILITY INFORMATION
TABLE 5. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86004 is: 2496
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
9
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PACKAGE OUTLINE - G SUFFIX 16 LEAD TSSOP
TABLE 6. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
10
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS86004BG
Marking
86004BG
86004BG
86004BGL
86004BGL
Package
Shipping Packaging
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
16 Lead TSSOP
ICS86004BGT
16 Lead TSSOP
2500 Tape & Reel
Tube
ICS86004BGLF
ICS86004BGLFT
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered
in certain jurisdictions.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringe-
ment of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
11
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
1
Pin Assignment - corrected package body dimensions from 4.
4mm x 3.0 mm x 0.92mm to 4.4mm x5.0 mm x 0.925mm.
A
3/31/06
12
3
Ordering Information Table - corrected marking from ICS86004BG from
86004BG. Added lead-free marking.
T7
4A
3.3V Power Supply Table - changed VDDA max from 3.465V to VDD
changed IDDO from 79mA max. to 8mA max.
,
4B
4C
3
3
3.3V/2.5V Power Supply Table - changed VDDA max from 3.465V to VDD,
changed IDDO from 79mA max. to 8mA max.
B
6/21/06
2.5V Power Supply Table - changed VDDA max from 3.465V to VDD,
changed IDDO from 79mA max. to 6mA max.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
12
ICS86004 REV B JUNE 21, 2006
ICS86004
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS ZERO DELAY CLOCK BUFFER
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+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA
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PLL Based Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5.0 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
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