87004AG [IDT]
PLL Based Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24;
| 型号： | 87004AG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 87004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总15页 (文件大小：759K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004
DATA SHEET
General Description
Features
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a member of
the HiPerClockS® family of High Performance Clock
Solutions from IDT. The ICS87004 has two selectable
clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
S
IC
HiPerClockS™
• CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
pairs can accept most standard differential input levels. Internal bias
on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs
to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to 250MHz.
The reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
levels on CLK0 and CLK1 inputs
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration with
configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: 50ps (maximum)
• Static phase offset: 50ps 125ps (3.3V 5ꢀ), CLK0/nCLK0
• Full 3.3V or 2.5V output operating supply
• 5V tolerant inputs
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
PLL_SEL
Pin Assignment
Pullup
1
2
24
23
Q1
GND
Q0
VDDO
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
V
SEL0
SEL1
SEL2
SEL3
DDO
3
4
22
21
Q2
GND
Q0
Q1
Q2
Q3
0
1
Pulldown
Pullup/Pulldown
CLK0
nCLK0
0
1
5
6
7
20
19
18
17
Q3
VDDO
MR
Pulldown
Pullup/Pulldown
CLK1
nCLK1
PLL
8
FB_IN
CLK_SEL
9
PLL_SEL
CLK1
nCLK1
V
DD
16
15
14
13
Pulldown
Pulldown
CLK0
nCLK0
GND
10
11
12
CLK_SEL
FB_IN
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
V
DDA
ICS87004
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Pulldown
SEL0
SEL1
SEL2
SEL3
MR
Top View
Pulldown
Pulldown
Pulldown
Pulldown
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 12, 21
GND
Power
Output
Power
Input
Power supply ground.
2, 20,
22, 24
Q0, Q3,
Q2, Q1
Single-ended clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
3, 19, 23
VDDO
Output supply pins.
4, 5,
6, 7
SEL0, SEL1,
SEL2, SEL3
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,
selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.
8
CLK_SEL
Input
Pulldown
9
VDD
Power
Input
Core supply pin.
10
CLK0
Pulldown
Non-inverting differential clock input.
Pullup/
Pulldown
11
13
14
15
nCLK0
VDDA
Input
Power
Input
Input
Inverting differential clock input. VDD/2 default when left floating.
Analog supply pin.
Pullup/
Pulldown
nCLK1
CLK1
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
Pulldown
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
16
17
18
PLL_SEL
FB_IN
MR
Input
Input
Input
Pullup
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
kΩ
pF
RPULLDOWN Input Pulldown Resistor
VDD, VDDO = 3.465V
23
17
12
Power Dissipation
CPD
Capacitance (per output)
VDD, VDDO = 2.625V
pF
ROUT
Output Impedance
5
7
Ω
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. PLL Enable Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
125 - 250
Q[0:3]
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
62.5 - 125
31.25 - 62.5
15.625 - 31.25
125 - 250
62.5 - 125
31.25 - 62.5
125 - 250
62.5 - 125
125 - 250
62.5 - 125
31.25 - 62.5
15.625 - 31.25
31.25 - 62.5
15.625 - 31.25
15.625 - 31.25
x2
x2
x4
x4
x8
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q[0:3]
÷8
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷8
÷8
÷16
÷16
÷16
÷32
÷32
÷64
÷128
÷4
÷4
÷8
÷2
÷4
÷2
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
3.465
100
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
V
3.135
3.3
V
mA
mA
mA
IDDA
IDDO
16
6
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
2.625
96
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.375
2.5
V
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
15
6
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
DD = 3.3V
VDD = 2.5V
DD = 3.3V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
Input Low Voltage
Input High Current
VDD = 2.5V
0.7
SEL[0:3], MR,
FB_IN, CLK_SEL
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
150
5
µA
µA
µA
IIH
PLL_SEL
SEL[0:3], MR,
FB_IN, CLK_SEL
V
DD = 3.465V or 2.625V,
-5
VIN = 0V
IIL
Input Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
PLL_SEL
-150
µA
V
DDO = 3.465V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.625V
VDD = 3.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V 5ꢀ or 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input
High Current
CLK0/nCLK0,
CLK1/nCLK1
IIH
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
150
µA
CLK0, CLK1
-5
µA
µA
V
Input
Low Current
IIL
nCLK0, nCLK1
V
DD = 3.465V or 2.625V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
15.625
250
MHz
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
tPD
5
6.2
ns
Qx ÷ 2
CLK0, nCLK0
CLK1, nCLK1
-75
50
175
175
ps
ps
Static Phase Offset;
NOTE 2, 4
PLL_SEL = 3.3V,
REF ≤ 167MHz, Qx ÷ 1
t(Ø)
f
-190
-65
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
tsk(o)
PLL_SEL = 0V
40
30
50
ps
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
fOUT > 40MHz
45
1
ps
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
40
800
60
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C to 70°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
15.625
250
MHz
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
tPD
5.3
6.9
ns
Qx ÷ 2
CLK0, nCLK0
CLK1, nCLK1
-175
-290
-25
125
125
ps
ps
Static Phase Offset;
NOTE 2, 4
PLL_SEL = 2.5V,
REF ≤ 167MHz, Qx ÷ 1
t(Ø)
f
-115
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
tsk(o)
PLL_SEL = 0V
fOUT > 40MHz
40
35
45
ps
tjit(cc)
tL
Cycle-to-Cycle Jitter; NOTE 4
PLL Lock Time
45
1
ps
ms
ps
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
44
700
56
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
V
V
DD,
DD,
V
DDA,
V
DDA,
V
V
DDO
Qx
DDO
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
V
DD
VDDO
Qx
Qy
2
nCLK[0:1]
VPP
VCMR
Cross Points
VDDO
2
CLK[0:1]
GND
tsk(o)
Differential Input Level
Output Skew
nCLK[0:1]
CLK[0:1]
VOH
VOL
VDDO
2
VDDO
VDDO
2
2
Q[0:3]
VOH
VDDO
VO2L
➤
➤
tcycle n
tcycle n+1
➤
➤
FB_IN
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
t(Ø)
➤
1000 Cycles
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges.
Cycle-to-Cycle Jitter
Static Phase Offset
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
nCLK[0:1]
80ꢀ
tF
80ꢀ
tR
CLK[0:1]
20ꢀ
20ꢀ
Q[0:3]
VDDO
2
Q[0:3]
t
PD
Propagation Delay
Output Rise/Fall Time
VDDO
2
Q[0:3]
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS87004 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin. The 10Ω resistor can also be replaced by
a ferrite bead.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
VDD
R1
1K
Single Ended Clock Input
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50
R2
50
LVHSTL
R1
50
R2
50
IDT
HiPerClockS
LVHSTL Driver
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
ICS87004AG REVISION C DECEMBER 1, 2009
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©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Reliability Information
Table 6. θJA vs. Air Flow Table for a 24 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
Transistor Count
The transistor count for ICS87004 is: 2578
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
24
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS87004AG REVISION C DECEMBER 1, 2009
12
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Ordering Information
Table 8. Ordering Information
Part/Order Number
87004AG
87004AGT
87004AGLF
87004AGLFT
Marking
ICS87004AG
ICS87004AG
ICS87004AGLF
ICS87004AGLF
Package
24 Lead TSSOP
24 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS87004AG REVISION C DECEMBER 1, 2009
13
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Revision History Sheet
Rev
A
Table
T8
Page
13
Description of Change
Date
Ordering Information Table - added Lead-Free marking.
6/16/04
5/17/05
A
T8
13
Ordering Information Table - corrected Lead-Free part number. Added Lead-Free note.
T5A
T5B
6
6
10
3.3V AC Characteristics Table - adjusted tPD parameter from 6ns max. to 6.2ns max.
2.5V AC Characteristics Table - adjusted tPD parameter from 6.7ns max. to 6.9ns max.
Added Recommendations for Unused Input and Output Pins section.
B
10/7/05
T4D
6
7
Differential DC Characteristics Table - updated NOTES 1, 2.
T5A, T5B
AC Characteristics Tables - Static Phase Offset, split CLKx into 2 rows. Specs changed for
CLK1/nCLK1. Added Thermal note.
C
C
10/6/09
12/1/09
11
13
Updated Differential Clock Input Interface section.
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
Converted datasheet format.
T8
1
Features section - corrected output skew from 465ps ot 50ps (maximum)
ICS87004AG REVISION C DECEMBER 1, 2009
14
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
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www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
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IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
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party owners.
Copyright 2009. All rights reserved.
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