87949AYI-01T [IDT]
Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48;
| 型号： | 87949AYI-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 87949 Series, 15 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87949I-01
LOW SKEW
÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
FEATURES
GENERAL DESCRIPTION
The ICS87949I-01 is a low skew, ÷1, ÷2 Clock Generator. • 15 single ended LVCMOS/LVTTL outputs,
The ICS87949I-01 has selectable single ended clock or
LVPECL clock inputs. The single ended clock input accepts
LVCMOS or LVTTL input levels. The PCLK, nPCLK pair can
accept LVPECL, CML, or SSTL input levels. The low
impedance LVCMOS/LVTTL outputs are designed to drive
50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 15 to 30 by utilizing
the ability of the outputs to drive two series terminated lines.
7Ω typical output impedance
• Selectable LVCMOS/LVTTL or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 250ps (maximum)
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the
÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master
reset input, MR/nOE, resets the internal frequency dividers
and also controls the active and high impedance states of
all outputs.
• Part-to-part skew: 1ns (maximum)
• Full 3.3V or mixed 3.3V core/2.5V output supply
• -40°C to 85°C ambient operating temperature
The ICS87949I-01 is characterized at 3.3V core/3.3V output
and 3.3V core/2.5V output. Guaranteed bank, output and
part-to-part skew characteristics make the ICS87949I-01 ideal
for those clock distribution applications demanding well
defined performance and repeatability.
• Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
0
1
CLK0
CLK1
÷1
÷2
0
1
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
MR/nOE
CLK_SEL
VDD
nc
R
PCLK
nPCLK
2
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
GND
QD5
3
0
1
4
CLK0
QA0, QA1
QB0:QB2
QC0:QC3
PCLK_SEL
DIV_SELA
5
CLK1
6
PCLK
ICS87949I-01
7
nPCLK
0
1
8
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
9
10
11
12
DIV_SELB
DIV_SELC
0
1
13 14 15 16 17 18 19 20 21 22 23 24
0
1
QD0:QD5
48-Lead LQFP
7mm x 7mm x 1.4mm package body
DIV_SELD
MR/nOE
Y Package
Top View
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ICS87949I-01
LOW SKEW ÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Active HIGH Master Reset. Active LOW output enable.
When logic HIGH, the internal dividers are reset and
1
MR/nOE
Input
Input
Pulldown the outputs are tri-stated (HiZ). When logic LOW, the
internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1. When
2
CLK_SEL
Pulldown
LOW, selects CLK0. LVCMOS / LVTTL interface levels.
3
4, 5
6
VDD
Power
Input
Input
Input
Input
Positive supply pin.
CLK0, CLK1
PCLK
Pullup
Pulldown Non-inverting differential LVPECL clock input.
Pullup Inverting differential LVPECL clock input.
LVCMOS / LVTTL clock inputs.
7
nPCLK
8
PCLK_SEL
Pulldown PCLK select input. LVCMOS / LVTTL interface levels.
Controls frequency division for Bank A outputs.
Pulldown
9
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
Input
Input
Input
Input
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels.
10
11
12
Pulldown
Controls frequency division for Bank C outputs.
LVCMOS / LVTTL interface levels.
Pulldown
Controls frequency division for Bank D outputs.
LVCMOS / LVTTL interface levels.
Pulldown
13, 14, 18, 22,
26, 27, 31, 35,
39, 43, 44, 48
15, 17, 19
GND
Power
Power supply ground.
QD0, QD1, QD2,
QD3, QD4, QD5
Bank D outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Positive supply pins for Bank D outputs.
Output
Power
21, 23, 25
16, 20, 24,
VDDD
Bank C outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
28, 30, 32, 34 QC3, QC2, QC1, QC0 Output
29, 33
36
VDDC
nc
Power
Unused
Power
Positive supply pins for Bank C outputs.
No connect.
37, 41
VDDB
Positive supply pins for Bank B outputs.
Bank B outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
38, 40, 42
QB2, QB1, QB0
Output
Bank A outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
45, 47
46
QA1, QA0
VDDA
Output
Power
Positive supply pins for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
pF
pF
Ω
RPULLUP
51
51
23
16
7
RPULLDOWN Input Pulldown Resistor
VDD, VDDx = 3.465V
VDD, VDDx = 2.625V
Power Dissipation Capacitance (per output);
NOTE 1
CPD
ROUT
Output Impedance
5
12
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD
.
TABLE 3. FUNCTION TABLE
Inputs
Outputs
MR/nOE
DIV_SELA
DIV_SELB
DIV_SELC DIV_SELD
QA0:QA1
Hi Z
QB0:QB2
Hi Z
QC0:QC3
QD0:QD5
Hi Z
1
0
0
0
0
0
0
0
0
X
0
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
Hi Z
Active
Active
Active
Active
fIN/1
fIN/1
Active
Active
fIN/1
Active
Active
Active
Active
Active
Active
fIN/1
1
fIN/2
X
X
X
X
X
X
Active
Active
Active
Active
Active
Active
1
fIN/2
X
X
X
X
Active
Active
Active
Active
1
fIN/2
X
X
Active
Active
1
fIN/2
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LVCMOS / LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDx
IDD
Positive Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
60
V
Output Supply Voltage; NOTE 1
Power Supply Current
V
mA
mA
IDDx
Output Supply Current; NOTE 2
20
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD
NOTE 2: IDDx denotes IDDA, IDDB, IDDC, IDDD
.
.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
2
VDD + 0.3
V
V
VIH
VIL
IIH
Input High Voltage
CLK0, CLK1
2
VDD + 0.3
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
-0.3
-0.3
0.8
V
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1
1.3
V
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = V = 3.465V
150
5
µA
µA
µA
IN
CLK0, CLK1
VDD = V = 3.465V
IN
DIV_SELA: DIV_SELD,
CLK_SEL, PCLK_SEL, VDD = 3.465V, V = 0V
MR/nOE
-5
IN
IIL
CLK0, CLK1
V
DD = 3.465V, V = 0V
-150
2.6
µA
V
IN
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
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÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Input Frequency
250
5
MHz
ns
ps
ps
ns
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Bank Skew; NOTE 2, 6
2.1
tsk(b)
tsk(o)
tsk(pp)
tR/ tF
odc
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
20ꢀ to 80ꢀ
100
300
1
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
400
40
950
60
5
Measured with outputs in ÷1
f = 10MHz
tEN
Output Enable Time;NOTE 5
Output Disable Time;NOTE 5
ns
ns
tDIS
f = 10MHz
5
All parameters measured at ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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ICS87949I-01
LOW SKEW ÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
60
Units
V
VDD
VDDx
IDD
Positive Supply Voltage
Output Supply Voltage; NOTE 1
Power Supply Current
2.375
2.5
V
mA
mA
IDDx
Output Supply Current; NOTE 2
20
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD
.
NOTE 2: IDDx denotes IDDA, IDDB, IDDC, IDDD
.
TABLE 4E. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
2
VDD + 0.3
V
V
Input
VIH
High Voltage
CLK0, CLK1
2
VDD + 0.3
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
-0.3
-0.3
0.8
V
Input
VIL
Low Voltage
CLK0, CLK1
1.3
V
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = V = 3.465V
150
5
µA
µA
µA
Input
IIH
IN
High Current
CLK0, CLK1
VDD = V = 3.465V
IN
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = 3.465V, V = 0V
-5
Input
IIL
IN
Low Current
CLK0, CLK1
V
DD = 3.465V, V = 0V
-150
1.8
µA
V
IN
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDx/2. See Parameter Measurement Section, 3.3V/2.5V Output Load Test Circuit.
TABLE 4F. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
PCLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
nPCLK
PCLK
V
-5
-150
IIL
Input Low Current
nPCLK
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Input Voltage
0.3
1
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
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LOW SKEW
÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Input Frequency
250
4.6
65
250
1
MHz
ns
ps
ps
ns
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Bank Skew; NOTE 2, 6
2.0
tsk(b)
tsk(o)
tsk(pp)
tR/ tF
odc
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
Measured on rising edge at VDDx/2
20ꢀ to 80ꢀ
Output Skew; NOTE 3, 6
Part-to-Part Skew; NOTE 4, 6
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
400
40
950
60
5
Measured with outputs in ÷1
f = 10MHz
tEN
Output Enable Time;NOTE 5
Output Disable Time;NOTE 5
ns
ns
tDIS
f = 10MHz
5
All parameters measured at ≤ 250MHz unless noted otherwise.
NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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ICS87949I-01
LOW SKEW ÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
2.05V 5ꢀ 1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD
VDDx
VDDx
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 0.15V
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDx
nPCLK
Qx
Qy
2
VPP
VCMR
Cross Points
VDDx
2
PCLK
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART 1
Qx
VDDx
2
80ꢀ
tF
80ꢀ
20ꢀ
20ꢀ
Clock
Outputs
PART 2
Qy
VDDx
tR
2
tsk(pp)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
VDD
2
CLK0, CLK1
nPCLK
PCLK
VDDx
2
QAx, QBx,
QCx, QDx
Pulse Width
tPERIOD
VDDx
2
QAx,QBx,
tPW
tPERIOD
QCx, QDx
➤
odc =
tPD
➤
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
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LVCMOS / LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LVCMOS / LVTTL CLOCK GENERATOR
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 3A to 3D show the vendor of the driver component to confirm the driver
interface examples for the PCLK/nPCLK input driven by the termination requirements.
most common driver types. The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 3A. PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 3B. PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
CLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 3C. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 3D. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 3E. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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LVCMOS / LVTTL CLOCK GENERATOR
SCHEMATIC EXAMPLE
This application note provides general design guide using ample of the ICS87949I-01 LVCMOS clock buffer. In this ex-
ICS87949I-01 LVCMOS buffer. Figure 4 shows a schematic ex- ample, the input is driven by an LVCMOS driver.
R1
43
Zo = 50
VDDO
VDD
VDD
U1
C1
R8
1K
0.1uF
VDD
1
2
3
4
5
6
7
8
9
36
MR/nOE
CLK_SEL
VDD
CLK0
CLK1
nc
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
35
34
33
32
31
30
29
28
27
26
25
RS
Zo = 50
PCLK
nPCLK
LVCMOS CLOCK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
10
11
12
GND
GND
QD5
R5
1K
VDD=3.3V
ICS87949I-01
VDDO=3.3V or 2.5V
Logic Input Pin Examples
Set Logic
Set Logic
Input to
'0'
VDD
VDD
R2
43
Zo = 50
Input to
'1'
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
(U1-16) VDDO (U1-20)
(U1-24)
(U1-29)
(U1-33)
(U1-37)
(U1-41)
(U1-46)
RD1
Not Install
RD2
1K
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
FIGURE 4. EXAMPLE ICS87949I-01 LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949I-01 is: 1545
87949AYI-01
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REV. A AUGUST 10, 2010
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ICS87949I-01
LOW SKEW ÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
87949AYI-01
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REV. A AUGUST 10, 2010
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ICS87949I-01
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÷1, ÷2
LVCMOS / LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
87949AYI-01
Marking
Package
48 Lead LQFP
Shipping Packaging
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87949AYI01
ICS87949AYI01
tray
87949AYI-01T
48 Lead LQFP on Tape and Reel
1000
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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REV. A AUGUST 10, 2010
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ICS87949I-01
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LVCMOS / LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
T8
13
15
8/10/10
87949AYI-01
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REV. A AUGUST 10, 2010
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LVCMOS / LVTTL CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
87949AYI-01
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