879893AYILF [IDT]
Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator;
| 型号： | 879893AYILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-12 (IDCS) LVCMOS/LVTTL Clock Generator DCS 驱动 分布式控制系统 逻辑集成电路 |
| 文件： | 总16页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-12 (IDCS)
879893
Datasheet
LVCMOS/LVTTL Clock Generator
General Description
Features
• Twelve LVCMOS/LVTTL outputs (two banks of six outputs);
The 879893 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two LVCMOS/LVTTL
clock signals from which it generates 12 new LVCMOS/LVTTL
clock outputs. External PLL feedback is used to also provide zero
delay buffer performance.
One QFB feedback clock output
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
• Automatically detects clock failure
• IDCS on-chip intelligent dynamic clock switch
• Maximum output frequency: 200MHz
• Output skew: 50ps (maximum), within bank
• Cycle-to-cycle (FSEL3=0, VDD=3.3V±5%): 150ps (maximum)
• Smooth output phase transition during clock fail-over switch
• Full 3.3V or 2.5V supply modes
The 879893 Intelligent Dynamic Clock Switch (IDCS) circuit
continuously monitors both input CLK signals. Upon detection of a
failure (CLK stuck HIGH or LOW for at least 1 period), the
nALARM for that CLK will be latched (LOW). If that CLK is the
primary clock, the IDCS will switch to the good secondary clock
and phase/frequency alignment will occur with minimal output
phase disturbance.
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For functional replacement part use 87973i
Pin Assignment
Simplified Block Diagram
Pulldown
nOE/MR
FSEL0 FSEL1 FSEL2 QA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷2
÷2
÷2
÷4
÷2
÷16
÷8
÷4
1
0
Pulldown
Pulldown
0
1
CLK0
CLK1
6
REF
36 35 34 33 32 31 30 29 28 27 26 25
QA0:QA5
D
Q
PLL
GND
GND
QB0
QB1
VDD
37
38
39
40
24
23
22
21
VCO RANGE
240MHz - 500MHz
QA0
QA1
VDD
FB
FB
0
1
Pulldown
Pullup
6
REF_SEL
nMAN/A
nALARM_RST
IDCS
D
Q
QB0:QB5
QFB
GND
QA2
QA3
41
42
43
44
45
46
20 GND
÷2
Pullup
QB2
QB3
VDD
19
18
17
16
15
14
13
FSEL0 FSEL1 FSEL2 QB
Pulldown
nPLL_EN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷16
÷8
VDD
GND
QA4
÷6
GND
QB4
QB5
VDD
÷8
D
Q
÷4
÷16
÷8
QA5 47
VDD
÷4
48
Pulldown
Pulldown
1 2 3 4 5 6 7 8 9 10 11 12
FSEL[0:2]
FSEL3
nALARM0
nALARM1
CLK_IND
879893
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Block Diagram
1
0
Pulldown
CLK0
0
1
6
QA0:QA5
REF
D
Q
Pulldown
CLK1
PLL
VCO RANGE
240MHz - 500MHz
Pulldown
FB
FB
DATA
GENERATOR
Pulldown
REF_SEL
6
QB0:QB5
D
Q
IDCS
Pullup
nMAN/A
Pullup
nALARM_RST
Pulldown
nPLL_EN
Pulldown
FSEL[0:3]
QFB
D
Q
nALARM0
nALARM1
CLK_IND
Pulldown
nOE/MR
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879893 Datasheet
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 12, 16,
20, 29, 32,
37, 41, 45
GND
Power
Power supply ground.
2
3
QFB
FB
Output
Input
Clock feedback output. LVCMOS / LVTTL interface levels.
Pulldown Feedback control input. LVCMOS / LVTTL interface levels.
Manual alarm input. Selects automatic switch mode or manual reference
clock. Clock failure detection, and nALARM_RST and CLK_IND output
flags are enabled. When LOW, IDCS is disabled. When HIGH, IDCS is
enabled. IDCS overrides REF_SEL on a clock failure. IDCS operation
requires nPLL_EN = 0. LVCMOS / LVTTL interface levels.
4
nMAN/A
Input
Pullup
5, 13, 17,
21, 25, 36,
40, 44, 48
VDD
Power
Core supply pins.
6, 7
8
CLK0, CLK1
VDDA
Input
Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Analog supply pin.
Power
When LOW, indicates clock failure on CLK0.
LVCMOS / LVTTL interface levels.
9
nALARM0
nALARM1
Output
Output
When LOW, indicates clock failure on CLK1.
LVCMOS / LVTTL interface levels.
10
Indicates currently selected input reference clock. When LOW, CLK0 is the
reference clock. When HIGH, CLK1 is the reference clock.
LVCMOS / LVTTL interface levels.
11
CLK_IND
Output
Output
14, 15, 18,
19, 22, 23
QB5, QB4, QB3,
QB2, QB1, QB0
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface levels.
Active High Master Reset. Active Low Output Enable. When logic LOW,
the internal dividers and the outputs are enabled. When logic HIGH, the
internal dividers are reset and the outputs are in a high-impedance state.
26
nOE/MR
Input
Pulldown
LVCMOS / LVTTL interface levels.
27, 28,
30, 31
FSEL3, FSEL2,
FSEL1, FSEL0
Clock frequency selection and configuration of clock divider modes.
LVCMOS / LVTTL interface levels.
Input
Input
Pulldown
Selects PLL or static test mode. When LOW, PLL is enabled. When HIGH,
Pulldown PLL is bypassed and IDCS is disabled. The VCO output is replaced by the
reference clock signal fREF. LVCMOS / LVTTL interface levels.
33
nPLL_EN
Selects the primary reference clock. When LOW, selects CLK0 as the
Pulldown primary clock source. When HIGH, selects CLK1 as the primary clock
source. LVCMOS / LVTTL interface levels.
34
35
REF_SEL
Input
Resets the alarm flags and selected reference clock.
nALARM_RST
Input
Pullup
LVCMOS / LVTTL interface levels.
38, 39 42,
43, 46, 47
QA0, QA1, QA2,
QA3, QA4, QA5
Output
Single-ended Bank A clock outputs. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2017 Integrated Device Technology, Inc.
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879893 Datasheet
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
9
VDD = 3.465V
pF
CPD
Power Dissipation Capacitance
VDD = 2.625V
9
pF
RPULLUP
Input Pullup Resistor
51
51
14
k
k
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
Function Tables
Table 3. Clock Frequency Function Table
Inputs
Outputs
fREF Range
FSEL0
FSEL1
FSEL2
FSEL3
(MHz)
Ratio
fQAx (MHz)
Ratio
fQBx (MHz)
120 – 200
60 – 100
120 – 200
60 – 100
120 – 200
60 – 100
60 – 125
30 – 75
QFB
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
f
REF * 8
15 – 25
fREF * 8
120 – 200
fREF * 4
fREF * 4
fREF * 2
30 – 50
40 – 66.66
30 – 62.5
60 – 100
15 – 31.25
30 – 62.5
60 – 100
f
REF * 4
120 – 200
120 – 200
60 – 125
f
REF * 3
fREF * 3 ÷ 2
REF * 2
fREF * 3
f
fREF * 2
fREF * 1
fREF * 2
fREF
120 – 200
60 – 100
15 – 31.25
7.5 – 15.62
20 – 62.5
15 – 31.25
60 – 100
30 – 50
f
REF * 2
120 – 200
15 – 31.25
30 – 62.5
60 – 100
fREF
fREF
fREF ÷ 2
fREF
fREF ÷ 2
fREF
fREF
fREF
fREF ÷ 2
©2017 Integrated Device Technology, Inc.
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879893 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
47.9C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
195
Units
V
VDD
VDDA
IDD
Positive Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
mA
mA
IDDA
13
Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
173
Units
V
VDD
VDDA
IDD
Positive Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
mA
IDDA
13
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.465V
Minimum
Typical
Maximum
Units
V
2
VDD + 0.3
VDD + 0.3
V
V
VIH Input High Voltage
VDD = 2.625V
1.7
FSEL[0:3], FB,
nOE/MR, nMAN/A,
nALARM_RST[0:1],
nPLL_EN, REF_SEL
VDD = 3.465V
-0.3
0.8
0.7
V
V
Input
Low Voltage
VIL
FSEL[0:3], FB,
nOE/MR, nMAN/A,
nALARM_RST,
VDD = 2.625V
-0.3
-0.3
nPLL_EN, REF_SEL
CLK0, CLK1
VDD = 3.465V or 2.625V
1.3
5
V
nMAN/A,
nALARM_RST
V
DD = VIN = 3.465V or 2.625V
µA
Input
High Current
IIH
CLK0, CLK1, FB,
nOE/MR, FSEL[0:3],
nPLL_EN, REF_SEL
VDD = VIN = 3.465V or 2.625V
200
µA
µA
µA
nMAN/A,
VDD = 3.465V or 2.625V,
-200
-5
nALARM_RST
VIN = 0V
Input
Low Current
IIL
CLK0, CLK1, FB,
nOE/MR, FSEL[0:3],
nPLL_EN, REF_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
V
DD = 3.465V, IOH = -24mA
2.4
1.8
V
V
V
V
V
VOH
Output High Voltage
VDD = 2.625V, IOH = -15mA
V
DD = 3.465V, IOL = 24mA
VDD = 3.465V, IOL = 12mA
DD = 2.625V, IOL = 15mA
0.55
0.30
0.6
VOL
Output Low Voltage
V
Unless otherwise noted, outputs terminated with 50 to VDD/2.
See Parameter Measurement Information section. Load Test Circuit diagrams.
©2017 Integrated Device Technology, Inc.
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879893 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
7.5
Typical Maximum
Units
MHz
MHz
MHz
ps
fOUT
fREF
BW
Output Frequency
200
100
Input Frequency
15
PLL Closed Loop Bandwidth
0.8 to 4
VDD = 3.3V±5%; FSEL = 111x
VDD = 3.3V±5%
-35
-35
120
130
50
Propagation Delay, (Static Phase
Offset, CLKx to FB); NOTE 1, 2, 3
t(Ø)
ps
within bank
ps
Output Skew;
bank-to-bank
NOTE 1, 2, 3, 4
tsk(o)
135
315
ps
any output to QFB
ps
ps/
cycle
fREF = 62.5MHz, FSEL = 1000
FSEL = XXX0
160
280
425
ps/
cycle
t
Rate of Period Change; NOTE 2
100
200
ps/
cycle
FSEL = XXX1
FSEL3 = 0
FSEL3 = 1
150
190
700
ps
ps
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2, 3
Output Clock Period Deviation when
switching from primary input to
secondary; NOTE 2
fREF = 62.5MHz, FSEL = 1000
-600
-800
tCYCLE
tjit(per)
800
ps
FSEL3 = 0
150
150
ps
ps
Period Jitter; NOTE 2, 3
FSEL3 = 1, measured on QBx
FB = 4;
FSEL [0:2] = 100 or 111 (1)
25
25
35
25
ps
ps
ps
ps
FB = 6;
FSEL [0:2] = 010 (1)
tjit(Ø)
I/O Phase Jitter, (1); NOTE 2, 3
FB = 8; FSEL [0:2] = 001, 011
or 110 (1)
FB = 16;
FSEL [0:2] = 000 or 101 (1)
tR / tF
tPZL, tPZH
tPLZ, tPHZ
tL
Output Rise/Fall Time
20% to 80%
250
45
600
10
ps
ns
ns
ms
%
Output Enable Time; NOTE 2
Output Disable Time; NOTE 2
PLL Lock Time; NOTE 2
Output Duty Cycle
10
10
55
odc
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 2: These parameters are guaranteed by characterization. Not tested in production.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Table 5B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum
7.5
Typical Maximum
Units
MHz
MHz
MHz
ps
fOUT
fREF
BW
Output Frequency
200
100
Input Frequency
15
PLL Closed Loop Bandwidth
0.8 to 4
VDD = 3.3V±5%; FSEL = 111x
VDD = 3.3V±5%
-55
-55
120
130
50
Propagation Delay, (Static Phase
Offset, CLKx to FB); NOTE 1, 2, 3
t(Ø)
ps
within bank
ps
Output Skew;
bank-to-bank
NOTE 1, 2, 3, 4
tsk(o)
135
280
ps
any output to QFB
ps
ps/
cycle
fREF = 62.5MHz, FSEL = 1000
FSEL = XXX0
175
260
350
ps/
cycle
t
Rate of Period Change; NOTE 2
ps/
cycle
FSEL = XXX1
FSEL3 = 0
FSEL3 = 1
180
245
700
ps
ps
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2, 3
Output Clock Period Deviation when
switching from primary input to
secondary; NOTE 2
fREF = 62.5MHz, FSEL = 1000
-600
-800
tCYCLE
tjit(per)
850
ps
FSEL3 = 0
150
150
ps
ps
Period Jitter; NOTE 2, 3
FSEL3 = 1, measured on QBx
FB = 4;
FSEL [0:2] = 100 or 111 (1)
30
40
25
30
ps
ps
ps
ps
FB = 6;
FSEL [0:2] = 010 (1)
tjit(Ø)
I/O Phase Jitter, (1); NOTE 2, 3
FB = 8; FSEL [0:2] = 001, 011
or 110 (1)
FB = 16;
FSEL [0:2] = 000 or 101 (1)
tR / tF
tPZL, tPZH
tPLZ, tPHZ
tL
Output Rise/Fall Time
20% to 80%
250
45
600
10
ps
ns
ns
ms
%
Output Enable Time; NOTE 2
Output Disable Time; NOTE 2
PLL Lock Time; NOTE 2
Output Duty Cycle
10
10
55
odc
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 2: These parameters are guaranteed by characterization. Not tested in production.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Parameter Measurement Information
1.25V±5%
1.65V±5%
SCOPE
SCOPE
V
V
DD,
V
V
DD,
DDA
DDA
Qx
Qx
GND
GND
-1.25V±5%
-1.65V±5%
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
VDD
QA[0:5],
QB[0:5]
Qx
Qy
2
➤
➤
tcycle n
tcycle n+1
➤
➤
VDD
2
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
tsk(o)
Output Skew
Cycle-to-Cycle Jitter
VOH
VOL
VOH
VDD
2
CLK0, CLK1
VREF
VOH
VOL
VDD
VOL
1σ contains 68.26% of all measurements
FB
2
➤
2σ contains 95.4% of all measurements
t(Ø)
➤
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter
t(Ø) mean = Static Phase Offset and I/O Phase Jitter
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges
Input/Output Phase Jitter
Period Jitter
©2017 Integrated Device Technology, Inc.
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879893 Datasheet
Parameter Measurement Information, continued
CLK0, CLK1
80%
80%
tR
FB
QA[0:5],
QB[0:5]
20%
20%
tF
Propagation Delay
Output Rise/Fall Time
VDDO
2
QA[0:5], QB[0:5]
tPW
tPERIOD
tPW
x 100%
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
©2017 Integrated Device Technology, Inc.
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Revision B, January 10, 2017
879893 Datasheet
Application Information
CLOCK REDUNDANCY AND REFERENCE SELECTION
The 879893 accepts two LVCMOS/LVTTL single ended input
clocks, CLK0 and CLK1, for the purpose of redundancy. Only one
of these clocks can be selected at any given time for use as the
reference. The clock that is used by default as the reference is
referred to as the primary clock, while the remaining clock is the
redundant or secondary clock. Input signal REF_SEL determines
which input is to be used as the primary and which is to be used as
the secondary. When REF_SEL is driven HIGH, the primary clock
input is CLK1, otherwise an internal pull down pulls this input LOW
so that the primary clock input is CLK0. The output signal CLK_IND
indicates which clock input is being used as the reference (LOW =
CLK0, HIGH = CLK1), and will initially be at the same level as
REF_SEL.
OUTPUT TRANSITIONING
After a successful manual or IDCS initiated clock switch, the
879893’s internal PLL will begin slewing to phase/frequency
alignment, and will eventually achieve lock with the new input with
minimal phase disturbance at the outputs.
MASTER RESET OPERATION
Applying logic HIGH to the nOE/MR input resets the internal
dividers of the 879893 and disables the outputs QA0:QA5 and
QB0:QB5 in high-impedance state. Logic LOW state at the
nOE/MR input enables the outputs and internal dividers.
RECOMMENDED POWER-UP SEQUENCE
FAILURE DETECTION AND ALARM SIGNALING
1. Hold nOE/MR HIGH, drive nMAN/ALOW, and drive REF_SEL
to the desired value during power up in order to reset internal
dividers, disable the outputs in high-impedance state
(nOE/MR = HIGH), select manual switching mode, and select
the primary input clock.
Within the 879893 device, CLK0 and CLK are continuously
monitored for failures. Afailure on either of these clocks is detected
when one of the clock signals is stuck HIGH or LOW for at least 1
period. Upon detection of a failure, the corresponding alarm signal,
nALARM0 or nALARM1, is latched LOW. A HIGH-to-LOW
transition on input signal nALARM_RST causes the alarm outputs
to be reset HIGH, and the primary clock input is selected as the
reference clock. Otherwise, an internal pull-up holds
nALARM_RST HIGH, and the IDCS flags remain unchanged. If
n_ALARM_RST is asserted when both of the alarm flag outputs
are LOW, CLK0 is selected as the reference input. The device’s
internal PLL is able to maintain phase/frequency alignment, and
lock with the input as long as the input used as the reference clock
does not fail.
2. Once powered up, assuming a stable clock free of failures is
present at the primary input, the PLL will begin
phase/frequency slewing as it attempts to achieve lock with
the input reference clock.
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
4. (Optional) Drive nMAN/A HIGH to enable IDCS mode.
ALTERNATE POWER-UP SEQUENCE
MANUAL CLOCK SWITCHING
If both input clocks are valid before power up, the device may be
powered up in IDCS mode.
When input signal nMAN/A is driven LOW, the primary clock, as
selected by REF_SEL, is always used as the reference, even
when a clock failure is detected at the reference. In order switch
between CLK0 and CLK1 as the primary clock, the level on
REF_SEL must be driven to the appropriate level. When the level
on REF_SEL is changed, the selection of the new primary clock
will take place, and CLK_IND will be updated to indicate which
clock is now supplying reference. This process serves as a manual
safety mechanism to protect the stability of the PLL when a failure
occurs on the reference.
1. During power up, select the desired primary clock input
by REF_SEL and hold nOE/MR at logic HIGH level to reset
the internal dividers and to disable the outputs QA0:QA5 and
QB0:QB5 in high-impedance state. Logic high level at the
nMAN/A input enables the IDCS mode. An internal bias
resistor will pull the nMAN/Ainput to logic high level if nMAN/A
is left open.
2. Once powered up, the PLLwill begin phase/frequency slewing
as it attempts to achieve lock with the input reference clock.
DYNAMIC CLOCK SWITCHING
When input signal nMAN/A is not driven LOW, an internal pull-up
pulls it HIGH so that Intelligent Dynamic Clock Switching (IDCS) is
enabled. If IDCS is enabled, once a failure occurs on the primary
clock, the 879893 device will automatically deselect the primary
clock as the reference and multiplex in the secondary clock, but
only if it is valid and has no failures. When a successful switch from
primary to secondary has been accomplished, CLK_IND will be
updated to indicate the new reference. This process serves as an
automatic safety mechanism to protect the stability of the PLL
when a failure occurs on the reference.
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
©2017 Integrated Device Technology, Inc.
11
Revision B, January 10, 2017
879893 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK Inputs
LVCMOS Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The 879893 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD and VDDA should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
©2017 Integrated Device Technology, Inc.
12
Revision B, January 10, 2017
879893 Datasheet
Schematic Example
Figure 2 shows a schematic example of the 879893. In this
example, the CLK1 input is selected as primary. Both CLK0 and
CLK1 inputs are driven by LVCMOS drivers. For the LVCMOS
outputs, series termination is shown in this example. Additional
LVCMOS termination approached are shown in the LVCMOS
Termination Application Note. In this example, feedback trace is
assumed to be a long trace. The series termination near the QFB
pin is required. If the feedback trace is short, series termination is
not required. If this device is also used as a zero delay buffer, the
application note ZDB Delay Affected by Feedback Trace provides
additional information. For the power pins, it is recommended to
have at least one decoupling capacitor per power pin. The
decoupling capacitors should be physically located near the power
pins.
LVCMOS/LVTTL
LVCMOS/LVTTL
VDDO
LVCMOS/LVTTL
Zo = 50 Ohm
QA5
R15
36
Zo = 50 Ohm
R16 36
VDDO
VDD
VDD
3.3V LVCMOS/LVTTL
Ro=14 Ohm
VDDO
R4
36
Zo = 50 Ohm
U1
VDD
R1
1K
Driver_LVCMOS
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
GND
QFB
FB
nMAN/A
VDD
CLK0
CLK1
VDD_PLL
nALARM0
nALARM1
CLK_IND
GND
VDD
nALARM_RST
REF_SEL
nPLL_EN
GND
nMAN/A
VDD
CLK0
CLK1
F_SEL0
F_SEL1
F_SEL0
F_SEL1
GND
F_SEL2
F_SEL3
nOE/MR
VDD
Ro=14 Ohm
R5
36
R2
1K
Zo = 50 Ohm
F_SEL2
F_SEL3
10
11
12
Driver_LVCMOS
VDD
R8
10
VDDA
ICS879893i
C31
0.1u
C40
10u
VDDO
Zo = 50 Ohm
QB5
R25
36
3.3V LVCMOS/LVTTL
VDD=3.3V
Status indicator
VDDO=3.3V
Hardwire Logic Input Pin Examples
(U1,25)
VDD (U1,36)
LVCMOS
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
C5
0.1u
C6
0.1u
LVCMOS
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
LVCMOS
(U1,5) VDDO (U1,13)
(U1,17)
(U1,21)
(U1,40)
(U1,44)
(U1,48)
RD1
Not Install
RD2
1K
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C7
0.1u
C8
0.1u
C9
0.1u
Figure 2. 879893 Schematic Example
©2017 Integrated Device Technology, Inc.
13
Revision B, January 10, 2017
879893 Datasheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 48 Lead LQFP
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for 879893 is: 4615
©2017 Integrated Device Technology, Inc.
14
Revision B, January 10, 2017
879893 Datasheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 48 Lead LQFP
Table 7. Package Dimensions for 48 Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
48
A
1.60
0.15
1.45
0.27
0.20
A1
0.05
1.35
0.17
0.09
0.10
1.4
A2
b
0.22
c
0.15
D & E
9.00 Basic
7.00 Basic
5.50 Ref.
0.50 Basic
0.60
D1 & E1
D2 & E2
e
L
0.45
0°
0.75
7°
ccc
0.08
Reference Document: JEDEC Publication 95, MS-026
©2017 Integrated Device Technology, Inc.
15
Revision B, January 10, 2017
Ordering Information
Table 8. Ordering Information
Part/Order Number
879893AYILF
879893AYILFT
Marking
ICS879893AIL
ICS879893AIL
Package
“Lead-Free” 48 Lead LQFP
“Lead-Free” 48 Lead LQFP
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
12
Updated Schematic Example text and diagram.
2/10/05
1
Features Section - added lead-free bullet.
11
Added Recommendations for Unused Input and Output Pins and Power Supply Filtering
Techniques Sections.
A
A
7/8/08
T8
T8
15
16
1
Ordering Information Table - added lead-free Part/Order Number, Marking and Note.
Updated datasheet format.
Ordering Information - removed leaded devices.
Updated data sheet format.
7/21/15
Product Discontinuation Notice - Last time buy expires November 2, 2016.
PDN# CQ-15-05.
A
B
11/6/15
1/10/17
Datasheet is obsolete per PDN# CQ-15-05.
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2017 Integrated Device Technology, Inc. All rights reserved.
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