879893BYI [IDT]
Clock Driver;
| 型号： | 879893BYI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总16页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
GENERAL DESCRIPTION
• 12 LVCMOS/LVTTL outputs (2 banks of 6 outputs);
1 QFB feedback clock output
The ICS879893BI is a PLL clock driver design-
ICS
ed specifically for redundant clock tree
designs. The device receives two LVCMOS/
LVTTL clock signals from which it generates 12
new LVCMOS/LVTTL clock outputs. External
PLL feedback is used to also provide zero de-
HiPerClockS™
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
lay buffer performance.
• Automatically detects clock failure
• IDCS on-chip intelligent dynamic clock switch
• Maximum output frequency: 200MHz
The ICS879893BI Intelligent Dynamic Clock Switch (IDCS)
circuit continuously monitors both input CLK signals. Upon
detection of a failure (CLK stuck HIGH or LOW for at least
1 period), the nALARM for that CLK will be latched (LOW).
If that CLK is the primary clock, the IDCS will switch to
the good secondary clock and phase/frequency alignment
will occur with minimal output phase disturbance.
• Output skew: 25ps (typical), within bank
• Cycle-to-cycle (FSEL3=0, VDD=3.3V 5ꢀ): 20ps (typical)
• Smooth output phase transition during clock failover switch
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
SIMPLIFIED BLOCK DIAGRAM
PIN ASSIGNMENT
nOE/MR
FSEL0 FSEL1 FSEL2
0
0
0
÷2
36 35 34 33 32 31 30 29 28 27 26 25
CLK0
CLK1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷2
÷2
÷4
÷2
÷16
÷8
1
0
0
1
37
38
39
40
41
42
43
GND
QA0
QA1
VDD
24
23
22
21
20
19
18
17
16
15
14
13
GND
QB0
QB1
VDD
REF
QA0:QA5
QB0:QB5
D Q
D Q
PLL
VCO Range
240MHz-500MHz
FB
FB
ICS879893BI
48-Pin LQFP
7mm x 7mm x 1.4mm
body package
÷4
GND
QA2
QA3
VDD
GND
QB2
QB3
VDD
REF_SEL
nMAN/A
nALARM_RST
0
1
IDCS
÷
2
44
45
46
Y Package
Top View
FSEL0 FSEL1 FSEL2
0
GND
QA4
QA5
VDD
GND
QB4
QB5
VDD
nPLL_EN
0
0
÷16
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷8
÷6
÷8
÷4
÷16
÷8
47
48
1
QFB
D Q
2 3 4 5 6 7 8 9 10 11 12
÷4
FSEL[0:2]
FSEL3
nALARM0
nALARM1
CLK_IND
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
879893BYI
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REV. A JULY 12, 2005
1
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
BLOCK DIAGRAM
1
0
CLK0
CLK1
0
1
6
QA0:QA5
REF
D
Q
PLL
VCO RANGE
240MHz - 500MHz
FB
FB
DATA
GENERATOR
REF_SEL
nMAN/A
6
QB0:QB5
D
Q
IDCS
nALARM_RST
nPLL_EN
FSEL[0:3]
QFB
D
Q
nALARM0
nALARM1
CLK_IND
nOE/MR
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REV. A JULY 12, 2005
2
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
5, 13, 17, 21, 25,
36, 40, 44, 48
Name
Type
Description
Core supply pins.
VDD
Power
6,
7
CLK0, CLK1
Input Pulldown LVCMOS / LVTTL clock inputs.
2
3
QFB
FB
Output
Clock feeback output. LVCMOS / LVTTL interface levels.
Input Pulldown Feedback control input. LVCMOS / LVTTL interface levels..
Manual alarm input. Selects automatic switch mode or manual
reference clock. Clock failure detection, and nALARM_RST and
CLK_IND output flags are enabled. When LOW, IDCS is disabled.
When HIGH, IDCS is enabled. IDCS overrides REF_SEL on a
clock failure. IDCS operation requires nPLL_EN = 0.
LVCMOS / LVTTL interface levels.
4
nMAN/A
Input
Pullup
8
9
VDDA
Power
Output
Analog supply pin for the PLL.
When LOW, indicates clock failure on CLK0.
LVCMOS / LVTTL interface levels.
nALARM0
When LOW, indicates clock failure on CLK1.
LVCMOS / LVTTL interface levels.
Indicates currently selected input reference clock.
When LOW, CLK0 is the reference clock. When HIGH,
CLK1 is the reference clock. LVCMOS / LVTTL interface levels.
10
11
nALARM1
CLK_IND
Output
Output
14, 15,
18, 19,
22, 23
QB5, QB4
QB3, QB2
QB1, QB0
Output
Bank B outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. Active Low Output Enable.
When logic LOW, the internal dividers and the outputs are
enabled. When logic HIGH, the internal dividers are reset and the
outputs are tri-stated (HiZ). LVCMOS / LVTTL interface levels.
26
nOE/MR
Input Pulldown
Power
1, 12, 16, 20, 29,
32, 37, 41, 45
GND
Supply ground.
27,
28,
30,
31
FSEL3,
FSEL2,
FSEL1,
FSEL0
Clock frequency selection and configuration of clock divider
modes. LVCMOS / LVTTL interface levels.
Input Pulldown
Selects PLL or static test mode. When LOW, PLL is enabled.
When HIGH, PLL is bypassed and IDCS is disabled. The VCO
output is replaced by the reference clock signal fREF.
LVCMOS / LVTTL interface levels.
33
nPLL_EN
REF_SEL
Input Pulldown
Selects the primary reference clock. When LOW, selects CLK0 as
34
35
Input Pulldown the primary clock source. When HIGH, selects CLK1 as the
primary clock source. LVCMOS / LVTTL interface levels.
Resets the alarm flags and selected reference clock.
LVCMOS / LVTTL interface levels.
nALARM_RST Input
QA0, QA1,
QA2, QA3,
QA4, QA5
Pullup
38, 39
42, 43,
46, 47
Output
Bank A outputs. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
879893BYI
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
51
51
9
pF
kΩ
kΩ
pF
pF
Ω
RPULLUP
RPULLDOWN Input Pulldown Resistor
VDD = VDDA = 3.465V
Power Dissipation Capacitance
(per output)
CPD
V
DD = VDDA = 2.625V
9
ROUT
Ouput Impedance
14
TABLE 3. CLOCK FREQUENCY FUNCTION TABLE (nPLL_EN = 0)
Inputs
Outputs
fREF Range
QAx
fQAx (MHz)
QBx
(MHz)
FSEL0 FSEL1 FSEL2 FSEL3
QFB
Ratio
Ratio
fREF * 8
fREF * 4
fREF * 4
fREF * 2
fREF * 3
fREF * 3 ÷ 2
fREF * 2
fREF * 1
fREF * 2
fREF
fQBx (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
120 - 200
60 - 100
120 - 200
60 - 100
120 - 200
60 - 100
60 - 125
30 - 75
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
15 - 25
30 - 50
fREF * 8
120 - 200
120 - 200
120 - 200
60 - 125
fREF * 4
fREF * 3
fREF * 2
fREF * 2
fREF
40 - 66.6
30 - 62.5
60 - 100
15 - 31.25
30 - 62.5
60 - 100
120 - 200
60 - 100
15 - 31.25
7.5 - 15.62
20 - 62.5
15 - 31.25
60 - 100
30 - 50
120 - 200
15 - 31.25
30 - 62.5
60 - 100
fREF
fREF ÷ 2
fREF
fREF
fREF ÷ 2
fREF
fREF
fREF ÷ 2
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
195
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
IDDA
13
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
173
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
IDDA
13
879893BYI
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
nMAN/A,
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
5
µA
µA
µA
µA
nALARM_RST
CLK0, CLK1,
nOE/MR, FB,
FSEL0:FSEL3,
REF_SEL, nPLL_EN
nMAN/A,
nALARM_RST
CLK0, CLK1,
nOE/MR, FB,
FSEL0:FSEL3,
REF_SEL, nPLL_EN
IIH
Input High Current
200
V
200
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
IOH = -24mA
-5
VOH
VOL
Output High Voltage
Output Low Voltage
2.4
V
V
V
I
OL = 24mA
0.55
0.30
IOL = 12mA
Unless otherwise noted, outputs terminated with 50Ω to VDD/2.
See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
1.7
VDD + 0.3
0.7
V
V
Input Low Voltage
-0.3
nMAN/A,
VDD = VIN = 2.625V
5
µA
µA
µA
µA
nALARM_RST
CLK0, CLK1,
nOE/MR, FB,
FSEL0:FSEL3,
REF_SEL, nPLL_EN
nMAN/A,
nALARM_RST
CLK0, CLK1,
nOE/MR, FB,
FSEL0:FSEL3,
REF_SEL, nPLL_EN
IIH
Input High Current
V
DD = VIN = 2.625V
200
VDD = 2.625V, VIN = 0V
200
IIL
Input Low Current
V
DD = 2.625V, VIN = 0V
-5
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -15mA
IOL = 15mA
1.8
V
V
0.6
Unless otherwise noted, outputs terminated with 50Ω to VDD/2.
See Parameter Measurement Information, Output Load Test Circuit.
879893BYI
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
fREF
BW
Output Frequency
7.5
15
200
100
250
MHz
MHz
MHz
MHz
ps
nPLL_EN = 0
nPLL_EN = 1
Input Frequency
DC
PLL Closed Loop Bandwidth
0.8 to 4
25
Propagation Delay
(static phase offset, CLKx to FB);
NOTE 2, 3
VDD = 3.3V 5ꢀ; FSEL = 111x
VDD = 3.3V 5ꢀ
t(Ø)
25
25
ps
ps
ps
ps
within bank
Output Skew;
bank-to-bank
NOTE 2, 3
70
tsk(o)
any output to QFB
130
ps/
cycle
ps/
cycle
ps/
Ref = 62.5MHz, FSEL = 1000
FSEL = XXX0
Rate of Period Change;
NOTE 1
Δt
100
200
FSEL = XXX1
cycle
FSEL3 = 0
FSEL3 = 1
20
25
ps
ps
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
Output Clock Period Deviation
when switching from primary input
to secondary; NOTE 1
REF = 62.5MHz, FSEL = 1000
TBD
ΔtCYCLE
TBD
12
ps
ps
ps
FSEL3 = 0
tjit(per) Period Jitter; NOTE 1, 3
FSEL3 = 1, measured on QBx
15
FB = 4; FSEL[0:2] = 100 or
111 (1σ)
FB = 6; FSEL[0:2] = 010 (1σ)
FB = 8; FSEL[0:]2 = 001, 011
or 110 (1σ)
11
19
13
ps
ps
ps
tjit(Ø)
tR/tF
I/O Phase Jitter (1σ); NOTE 1, 3
FB = 16; FSEL[0:2] = 000 or
101 (1σ)
12
ps
Output Rise/Fall Time
20ꢀ to 80ꢀ
250
600
10
ps
ns
ns
ms
ꢀ
t
t
PZL, tPZH Output Enable Time; NOTE 1
PLZ, tPHZ Output Disable Time; NOTE 1
10
tL
PLL Lock Time; NOTE 1
Output Duty Cycle
10
odc
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
879893BYI
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
fREF
BW
Output Frequency
7.5
15
200
1000
250
MHz
MHz
MHz
MHz
ps
nPLL_EN = 0
nPLL_EN = 1
Input Frequency
DC
PLL Closed Loop Bandwidth
0.8 to 4
10
Propagation Delay
(static phase offset, CLKx to FB);
NOTE 2, 3
V
DD = 2.5V 5ꢀ; FSEL = 111x
VDD = 2.5V 5ꢀ
t(Ø)
10
25
ps
ps
ps
ps
within bank
Output Skew;
bank-to-bank
NOTE 2, 3
70
tsk(o)
any output to QFB
130
ps/
cycle
ps/
cycle
ps/
Ref = 62.5MHz, FSEL = 1000
FSEL = XXX0
TBD
100
175
Rate of Period Change;
NOTE 1
Δt
FSEL = XXX1
cycle
FSEL3 = 0
FSEL3 = 1
20
25
ps
ps
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1, 3
Output Clock Period Deviation
when switching from primary input
to secondary; NOTE 1
REF = 62.5MHz, FSEL = 1000
TBD
ΔtCYCLE
ps
ps
ps
FSEL3 = 0
12
25
tjit(per) Period Jitter; NOTE 1, 3
FSEL3 = 1, measured on QBx
FB = 4; FSEL[0:2] = 100 or
111 (1σ)
FB = 6; FSEL[0:2] = 010 (1σ)
FB = 8; FSEL[0:2] = 001, 011
or 110 (1σ)
11
14
11
ps
ps
ps
tjit(Ø)
tR/tF
I/O Phase Jitter (1σ); NOTE 1, 3
FB = 16; FSEL[0:2] = 000 or
101 (1σ)
14
ps
Output Rise/Fall Time
20ꢀ to 80ꢀ
250
600
10
ps
ns
ns
ms
ꢀ
t
t
PZL, tPZH Output Enable Time; NOTE 1
PLZ, tPHZ Output Disable Time; NOTE 1
10
tL
PLL Lock Time; NOTE 1
Output Duty Cycle
10
odc
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
879893BYI
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REV. A JULY 12, 2005
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
,
VDD
,
VDDA
VDDA
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
QA0:QA5,
QB0:QB5
Qx
2
➤
➤
tcycle n+1
tcycle n
➤
➤
VDD
Qy
2
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
VOH
VREF
VOH
VOL
VDD
2
CLK0,
CLK1
VOH
VOL
VOL
VDD
2
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
FB
➤
t(Ø)
➤
Histogram
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
t(Ø) mean = Static Phase Offset and I/O Phase Jitter
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
PERIOD JITTER
INPUT/OUTPUT PHASE JITTER
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ICS879893BI
Integrated
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LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
VDD
2
80ꢀ
tF
80ꢀ
tR
CLK0,
CLK1
20ꢀ
20ꢀ
Clock
Outputs
VDD
2
FB
t
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDD
2
QAx, QBx
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATIONS INFORMATION
CLOCK REDUNDANCY AND REFERENCE SELECTION
a successful switch from primary to secondary has been ac-
complished, CLK_IND will be updated to indicate the new refer-
ence.This process serves as an automatic safety mechanism
to protect the stability of the PLL when a failure occurs on the
reference.
The ICS879893BI accepts two LVCMOS/LVTTL single ended
input clocks, CLK0 and CLK1, for the purpose of redundancy.
Only one of these clocks can be selected at any given time for
use as the reference. The clock that is used by default as the
reference is referred to as the primary clock, while the remain-
ing clock is the redundant or secondary clock. Input signal
REF_SEL determines which input is to be used as the primary
and which is to be used as the secondary. When REF_SEL is
driven HIGH, the primary clock input is CLK1, otherwise an in-
ternal pull down pulls this input LOW so that the primary clock
input is CLK0.The output signal CLK_IND indicates which clock
input is being used as the reference (LOW = CLK0, HIGH =
CLK1), and will initially be at the same level as REF_SEL.
OUTPUT TRANSITIONING
After a successful manual or IDCS initiated clock switch, the
ICS879893BI’s internal PLL will begin slewing to phase/frequency
alignment, and will eventually achieve lock with the new input
with minimal phase disturbance at the outputs.
MASTER RESET OPERATION
When input signal nOE/MR is driven HIGH, the output clocks,
QA0:QA5, are tri-stated and the ICS879893BI’s internal divid-
ers are reset. Otherwise, nOE/MR is pulled LOW and the output
clocks and internal dividers are enabled.
FAILURE DETECTION AND ALARM SIGNALING
Within the ICS879893BI device, CLK0 and CLK are continuously
monitored for failures. A failure on either of these clocks is de-
tected when one of the clock signals is stuck HIGH or LOW for
at least 1 period. Upon detection of a failure, the corresponding
alarm signal, nALARM0 or nALARM1, is latched LOW.A HIGH-
to-LOW transition on input signal nALARM_RST causes the
alarm outputs to be reset HIGH, and the primary clock input is
selected as the reference clock. Otherwise, an internal pull-up
holds nALARM_RST HIGH, and the IDCS flags remain un-
changed. If n_ALARM_RST is asserted when both of the alarm
flag outputs are LOW, CLK0 is selected as the reference input.
The device’s internal PLL is able to maintain phase/frequency
alignment, and lock with the input as long as the input used as
the reference clock does not fail.
RECOMMENDED POWERUP SEQUENCE
1. Hold nOE/MR HIGH, drive nMAN/A LOW, and drive
REF_SEL to the desired value during power up in order to reset
internal dividers, tristate the outputs, select manual switching
mode, and select the primary input clock.
2. Once powered up, assuming a stable clock free of failures is
present at the primary input, the PLL will begin phase/frequency
slewing as it attempts to achieve lock with the input reference
clock.
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
MANUAL CLOCK SWITCHING
When input signal nMAN/A is driven LOW, the primary clock, as
selected by REF_SEL, is always used as the reference, even
when a clock failure is detected at the reference. In order switch
between CLK0 and CLK1 as the primary clock, the level on
REF_SEL must be driven to the appropriate level.When the level
on REF_SEL is changed, the selection of the new primary clock
will take place, and CLK_IND will be updated to indicate which
clock is now supplying reference. This process serves as a
manual safety mechanism to protect the stability of the PLL when
a failure occurs on the reference.
4. (Optional) Drive nMAN/A HIGH to enable IDCS mode.
ALTERNATE POWERUP SEQUENCE
If both input clocks are valid before power up, the part may be
powered up in ICDS mode.
1. Hold nOE/MR HIGH and drive REF_SEL to the desired value
during power up in order to reset internal dividers, tristate the
outputs, and select the primary input clock. Leave nMAN/A float-
ing, and an internal pull-up at that input will enable IDCS mode.
DYNAMIC CLOCK SWITCHING
2. Once powered up, the PLL will begin phase/frequency slewing
as it attempts to achieve lock with the input reference clock.
When input signal nMAN/A is not driven LOW, an internal pull-
up pulls it HIGH so that Intelligent Dynamic Clock Switching
(IDCS) is enabled. If IDCS is enabled, once a failure occurs on
the primary clock, the ICS879893BI device will automatically de-
select the primary clock as the reference and multiplex in the
secondary clock, but only if it is valid and has no failures.When
3. Transition nALARM_RST HIGH-to-LOW to reset nALARM0
and nALARM1 alarm flag outputs.
879893BYI
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REV. A JULY 12, 2005
11
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating.We recommend
input, both XTAL_IN and XTAL_OUT can be left floating.Though that there is no trace attached.
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
CLK INPUT:
For applications not requiring the use of the test clock, it can be output pair should either be left floating or terminated.
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
TEST CLK INPUT:
For applications not requiring the use of the test clock, it can be output pair should either be left floating or terminated
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
LVDS – Like OUTPUT
but for additional protection, a 1kΩ resister can be tied from CLK All unused LVDS outputs can be left floating.We recommend
to ground.
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
HCSL OUTPUT
the PCLK and nPCLK pins can be left floating. Though not All unused HCSL outputs can be left floating.We recommend
required, but for additional protection, a 1kΩ resister can be tied that there is no trace attached. Both sides of the differential
from PCLK to ground.
output pair should either be left floating or terminated
SELECT PINS:
SSTL OUTPUT
All select pins have internal pull-ups and pull-downs; additional All unused SSTL outputs can be left floating. We recommend
resistance is not required but can be added for additional that there is no trace attached. Both sides of the differential
protection. A 1kΩ resister can be used.
output pair should either be left floating or terminated
879893BYI
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REV. A JULY 12, 2005
12
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
SCHEMATIC EXAMPLE
Figure 1 shows a schematic example of the ICS879893BI. In
this example, the CLK1 input is selected as primary.Both CLK0
and CLK1 inputs are driven by LVCMOS drivers. For the
tion near the QFB pin is required. If the feedback trace is short,
series termination is not required. If this device is also used as a
zero delay buffer, the application note ZDB Delay Affected by
LVCMOS outputs, series termination is shown in this example. Feedback Trace provides additional information. For the power
pins, it is recommended to have at least one decoupling capaci-
tor per power pin.The decoupling capacitors should be physi-
cally located near the power pins
Additional LVCMOS termination approached are shown in the
LVCMOS Termination Application Note. In this example, feed-
back trace is assumed to be a long trace. The series termina-
LVCMOS/LVTTL
LVCMOS/LVTTL
VDDO
LVCMOS/LVTTL
Zo = 50 Ohm
QA5
R15
36
Zo = 50 Ohm
R16 36
VDDO
VDD
VDD
3.3V LVCMOS/LVTTL
Ro=14 Ohm
VDDO
R4
36
Zo = 50 Ohm
U1
VDD
R1
1K
Driver_LVCMOS
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
GND
QFB
FB
nMAN/A
VDD
CLK0
CLK1
VDD_PLL
nALARM0
nALARM1
CLK_IND
GND
VDD
nALARM_RST
REF_SEL
nPLL_EN
GND
nMAN/A
VDD
CLK0
CLK1
F_SEL0
F_SEL1
F_SEL0
F_SEL1
GND
F_SEL2
F_SEL3
nOE/MR
VDD
Ro=14 Ohm
R5
36
R2
1K
Zo = 50 Ohm
F_SEL2
F_SEL3
10
11
12
Driver_LVCMOS
VDD
R8
10
VDDA
ICS879893i
ICS879893BI
C31
0.1u
C40
10u
VDDO
Zo = 50 Ohm
QB5
R25
36
3.3V LVCMOS/LVTTL
VDD=3.3V
Status indicator
VDDO=3.3V
Hardwire Logic Input Pin Examples
(U1,25)
VDD (U1,36)
LVCMOS
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
C5
0.1u
C6
0.1u
LVCMOS
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
LVCMOS
(U1,5) VDDO (U1,13)
(U1,17)
(U1,21)
(U1,40)
(U1,44)
(U1,48)
RD1
Not Install
RD2
1K
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C7
0.1u
C8
0.1u
C9
0.1u
FIGURE 1. ICS879893BI SCHEMATIC EXAMPLE
879893BYI
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REV. A JULY 12, 2005
13
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS879893BI is: 4615
Pin compatible with MPC9893
879893BYI
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REV. A JULY 12, 2005
14
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
879893BYI
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REV. A JULY 12, 2005
15
PRELIMINARY
ICS879893BI
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
ICS879893BYI
ICS879893BYIT
ICS879893BYI
ICS879893BYI
48 Lead LQFP
48 Lead LQFP
1000 tape & reel
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
879893BYI
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REV. A JULY 12, 2005
16
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