87993AYIT [IDT]
PLL Based Clock Driver, 87993 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 87993AYIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 87993 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
GENERAL DESCRIPTION
FEATURES
The ICS87993I is a PLL clock driver designed specifically • 5 differential 3.3V LVPECL outputs
for redundant clock tree designs. The device receives two
differential LVPECL clock signals from which it generates
• Selectable differential clock inputs
5 new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signal frequency and phase
while the other three pairs generate 2x, phase aligned clock
outputs. External PLL feedback is used to also provide zero
delay buffer performance.
• CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 50MHz to 250MHz
• VCO range: 200MHz to 500MHz
The ICS87993I Dynamic Clock Switch (DCS) circuit
continuously monitors both input CLK signals. Upon
detection of a failure (CLK stuck HIGH or LOW for at least 1
period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the DCS will switch to the good
secondary clock and phase/frequency alignment will
occur with minimal output phase disturbance. The typical
phase bump caused by a failed clock is eliminated.
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Cycle-to-cycle jitter (RMS): 20ps (maximum)
• Output skew: 70ps (maximum), within one bank
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package available
PIN ASSIGNMENT
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
nQA1
16
15
14
13
12
11
10
9
VCC
QA1
INP0BAD
INP1BAD
CLK_SELECTED
VEE
ICS87993I
32-Lead QFP (LQFP)
7mm x 7mm x 1.4mm
package body
nQA0
QA0
VCC
VCCA
nEXT_FB
EXT_FB
VEE
Y Package
Top View
MAN_OVERRIDE
PLL_SEL
1
2
3
4
5
6
7
8
BLOCK DIAGRAM
PLL_SEL
CLK_SELECTED
INP1BAD
Dynamic Switch
INP0BAD
Logic
MAN_OVERRIDE
ALARM_RESET
nQB0
QB0
nQB1
QB1
SEL_CLK
nCLK0
CLK0
nCLK1
nQB2
QB2
÷2
÷4
CLK1
nQA0
QA0
PLL
nEXT_FB
EXT_FB
nQA1
QA1
nMR
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
Active LOW Master Reset. When logic LOW, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic HIGH, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
When LOW, resets the input bad flags and aligns CLK_SELECTED
with SEL_CLK. LVCMOS / LVTTL interface levels.
1
nMR
Input
Input
Pullup
2
nALARM_RESET
Pullup
3
4
CLK0
Input Pulldown Non-inverting differential clock input.
nCLK0
Input
Pullup Inverting differential clock input.
Clock select input. When LOW, selects CLK0, nCLK0 inputs. When
HIGH, selects CLK1, nCLK1 inputs. LVCMOS / LVTTL interface levels.
5
SEL_CLK
Input Pulldown
6
7
CLK1
nCLK1
VEE
Input Pulldown Non-inverting differential clock input.
Input
Pullup Inverting differential clock input.
Negative supply pins.
8, 9, 12
10
Power
EXT_FB
nEXT_FB
Input Pulldown Differential external feedback.
11
Input
Pullup
Differential external feedback.
LOW, when CLK0, nCLK0 is selected, HIGH, when CLK1, nCLK1
is selected. LVCMOS / LVTTL interface levels.
13
CLK_SELECTED Output
Indicates detection of a bad input reference clock 1 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asserted.
14
INP1BAD
Output
Indicates detection of a bad input reference clock 0 with respect to the
feedback signal. The output is active HIGH and will remain HIGH until
the alarm reset is asserted.
15
INP0BAD
VCC
Output
Power
16, 17,
24, 29
Core supply pins.
18, 19
20, 21
22, 23
25, 26
27, 28
30
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
VCCA
Output
Output
Output
Output
Output
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
Manual override. When HIGH, disables internal clock switch circuitry.
LVCMOS / LVTTL interface levels.
31
MAN_OVERRIDE Input Pulldown
Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock.When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
32
PLL_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.135
3.135
3.3
3.3
80
3.465
3.465
180
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
15
20
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS Inputs
LVCMOS Inputs
2
3.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
SEL_CLK,
VIN = VCC = 3.465V
5
µA
µA
µA
µA
MAN_OVERRIDE
nALARM_RESET,
PLL_SEL, nMR
SEL_CLK,
MAN_OVERRIDE
nALARM_RESET,
PLL_SEL, nMR
IIH
V
IN = VCC = 3.465V
IN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
120
V
-5
IIL
Input Low Current
-120
2.4
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information Section,
"3.3V Output Load AC Test Circuit diagram".
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, CLK1,
EXT_FB
nCLK0, nCLK1,
nEXT_FB
CLK0, CLK1,
EXT_FB
nCLK0, nCLK1,
nEXT_FB
VIN = VCC = 3.465V
5
µA
µA
µA
µA
IIH
Input High Current
V
IN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
IN = 0V, VCC = 3.465V
120
-5
IIL
Input Low Current
V
-120
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended appliations, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
fVCO
Parameter
Test Conditions
Minimum Typical Maximum
Units
MHz
ꢀ
PLL VCO Lock Range
200
25
500
75
tPWI
CLKx to Q
PLL_SEL = LOW
2.8
3.45
0
4.1
ns
PLL_SEL = HIGH
fVCO ≤ 360MHz
PLL_SEL = HIGH
fVCO ≤ 500MHz
-150
170
200
ps
ps
tPD
Propagation Delay
Output Rise Time
CLKx to EXT_FB;
NOTE 2
-150
200
0
tR / tF
20ꢀ to 80ꢀ @ 50MHz
800
70
ps
ps
ps
Within Bank
All Outputs
Output Skew;
NOTE 3
tsk(o)
100
75MHz Output;
NOTE 1, 4
150MHz Output;
NOTE 1, 4
75MHz Output;
NOTE 1, 5
150MHz Output;
NOTE 1, 5
20
10
50
25
ps/cycle
ps/cycle
ps/cycle
ps/cycle
Rate of change
of Periods
Tested at
typical conditions
ΔPER/CYCLE
200
100
400
200
odc
tjit(cc)
tL
Output Duty Cycle
f ≤ 360MHz
45
55
20
10
ꢀ
ps
Cycle-to-Cycle Jitter (RMS); NOTE 1
PLL Lock Time; NOTE 1
ms
All parameters measured at fMAX unless noted otherwise.
NOTE 1: These parameters are guaranteed by characterization. Not tested in production.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Specification holds for a clock switch between two signals no greater than 400ps out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
NOTE 5: Specification holds for a clock switch between two signals no greater than π out of phase.
Delta period change per cycle is averaged over the clock switch excursion.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PARAMETER MEASUREMENT INFORMATION
2V
VCC
SCOPE
VCC
VCCA
,
Qx
nCLK0,
nCLK1
LVPECL
VEE
VPP
VCMR
Cross Points
CLK0,
CLK1
nQx
VEE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQAx,
nQBx
nQx
Qx
nQAx,
nQBx
➤
➤
➤
tcycle n
tcycle n+1
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQAx,
nQBx
nQAx,
nQBx
80ꢀ
tF
80ꢀ
VSWING
20ꢀ
Pulse Width
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87993I provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 1 illustrates how a 10Ω resistor along with a
10μF and a .01μF bypass capacitor should be connected to
each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals. Both VSWING and VOH must meet
the VPP and VCMR input requirements. Figures 4A to 4D show
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for LVHSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an LVHSTL driver from another
common driver types. The input interfaces suggested here are vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
FIGURE 4B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of the ICS87993I. In this Bank A or Bank B depending on the application. The decoupling
example, the CLK0/nCLK0 input is selected as primary. The in- capacitors should be physically located near the power pin.
put is driven by an LVPECL driver. Feedback can be either from For ICS87993I, the unused outputs can be left floating.
VCC
VCC
VCC
R16
1K
R15
1K
Zo = 50
Zo = 50
+
-
R7
10
VCCA
C11
0.01u
VCC
LVCMOS
C16
10u
R2
50
R1
50
U1
C5 (Option)
R3
50
VCC
0.1u
1
2
3
4
5
6
7
8
24
nMR
nALM_RS
CLK0
nCLK0
CLK_SEL
CLK1
nCLK1
VEE
VCC
QB0
nQB0
QB1
nQB1
QB2
nQB2
VCC
Zo = 50 Ohm
Zo = 50 Ohm
23
22
21
20
19
18
17
CLK_SEL
LVPECL Driv er
R2
1K
R9
50
R10
50
ICS87993I
C7 (Option)
0.1u
R11
50
VCC
LVCMOS
Zo = 50 Ohm
Zo = 50 Ohm
R5
50
R4
50
LVCMOS
LVPECL Driv er
C8 (Option)
0.1u
R6
50
R12
50
R13
50
LVCMOS
C6 (Option)
0.1u
R14
50
(U1-16)
(U1-17)
(U1-24) (U1-29)
VCC
C1
0.1uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
FIGURE 5A. ICS87993I LVPECL SCHEMATIC EXAMPLE
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as close
to the driver pins as possible.
GND
VCC
C4
R7
C16 C11
U1
C3
Pin 1
VCCA
VIA
50 Ohm
Traces
C2
C1
FIGURE 5B. PCB BOARD LAYOUT FOR ICS87993I
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87993I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87993I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180 = 624mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30.2mW = 151mW
Total Power_MAX (3.465V, with all outputs switching) = 624mW + 151mW = 775mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.775W * 42.1°C/W = 117.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CC_MAX
)
= 1.0V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87993I is: 2745
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
87993AYI
ICS87993AYI
ICS87993AYI
ICS87993AILF
ICS87993AILF
32 Lead LQFP
tray
-40°C to 85°C
32 Lead LQFP on Tape and
Reel
87993AYIT
87993AYILF
87993AYILFT
1000
tray
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP on
Tape and Reel
1000
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
4
AC Table - deleted Note 6.
T4
A
1/16/03
7
1
Added "Wiring the Differential Input to Accept Single Ended Levels".
Features Section - changed VCO max. from 360MHz to 500MHz.
T1
T2
2
2
3
Pin Descriptions Table - revised nMR description.
Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF.
Absolute Maximum Ratings - changed VO to IO and included Continuous
Current and Surge Current
B
5/21/03
AC Characteristics Table - changed fVCO from 360MHz to 500MHz.
T4
4
tPD - added test conditions to CLKx to EXT_FB. Added another line with
500MHz test conditions.
odc - added test conditions.
Added Differential Clock Input Interface in the Application Information section.
8
Added Schematic Example.
9 & 10
15
B
C
T8
T8
Ordering Information Table - added Lead-Free part number.
10/21/04
7/26/10
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
15
17
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ICS87993I
1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PLL CLOCK DRIVER W/DYNAMIC CLOCK SWITCH
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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