889474AK [IDT]

Clock Driver, 889474 Series, 2 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.90 MM HEIGHT, MO-220, VFQFN-24;


型号：	889474AK
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Clock Driver, 889474 Series, 2 True Output(s), 0 Inverted Output(s), 4 X 4 MM, 0.90 MM HEIGHT, MO-220, VFQFN-24 驱动逻辑集成电路
文件：	总15页 (文件大小：1457K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

ICS889474

GENERAL DESCRIPTION

FEATURES

The ICS889474 is a high speed 2-to-1 differential

• Two differential LVDS outputs

ICS

HiPerClockS™

multiplexer with integrated 2 output LVDS fanout

buffer and internal termination and is a member of

the HiPerClockS™ family of high performance

clock solutions from IDT. The ICS889474 is

• INx, nINx pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, CML

• 50Ω internal input termination to V_T

• Maximum output frequency: 2GHz (maximum)

• Additive phase jitter, RMS: 0.06ps (typical)

• Output skew: 20ps (maximum)

optimized for high speed and very low output skew, making it

suitable for use in demanding applications such as SONET,

1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The

internally terminated differential input and V^REF_AC pins allow

other differential signal families such as LVPECL, LVDS,

LVHSTL and CML to be easily interfaced to the input with

minimal use of external components. The ICS889474 is

packaged in a small 4mm x 4mm 24-pin VFQFN package

which makes it ideal for use in space-constrained applications.

• Propagation delay: 700ps (maximum)

• 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS-complaint

packages

BLOCK DIAGRAM

PIN ASSIGNMENT

IN0

50Ω

V_T0

24 23 22 21 20 19

50Ω

nIN0

V_{REF_AC0}

IN1

nQ0

VDD

nIN0

GND

MUX

VREF_AC0

50Ω

V_T1

VT0

IN0

V^DD

15 SEL

14 GND

nQ1

nIN1

V_{REF_AC1}

V^DD

10 11 12

SEL

ICS889474

24-Lead VFQFN

4mm x 4mm x 0.925mm package body

K Package

Top View

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 6, 9,

10, 13,

19, 24

V_DD

Power

Positive supply pins.

2, 20

nIN0, nIN1

Input

Inverting differential clock inputs. 50Ω internal input termination to V_T.

V_{REF_AC0,}

V_{REF_AC1}

Output

Reference voltage for AC-coupled applications.

4, 22

5, 23

7, 8

V_T0,V_T1

IN0, IN1

Q0, nQ0

Q1, nQ1

GND

Input

Termination inputs.

Non-inverting differential clock inputs. 50Ω internal input termination to V_T.

Differential output pair. LVDS interface levels.

Power supply ground.

Output

Power

Input

11, 12

14, 17, 18

SEL

Pullup

Input select pin. LVCMOS/LVTTL interface levels.

No connect.

Unused

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

R_PULLUP

Input Pullup Resistor

kΩ

TABLE 3. TRUTH TABLE

Inputs

Outputs

IN0

nIN0

IN1

nIN1

SEL

Q0:Q1

nQ0:nQ1

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Supply Voltage, V_DD

4.6V

Inputs, V

-0.5V to V_DD+ 0.5 V

Outputs, I_O(LVDS)

Continuous Current

Surge Current

10mA

15mA

Input Current, INx, nINx

V_TCurrent, I_VT

50mA

100mA

Input Sink/Source, I_{REF_AC}

Operating Temperature Range, T_A

Storage Temperature, T_STG

0.5mA

-40°C to +85°C

-65°C to 150°C

49.5°C/W (0 mps)

Package Thermal Impedance, θ_JA

(Junction-to-Ambient)

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

V_DD

I_DD

Positive Supply Voltage

Power Supply Current

2.375

2.5

2.625

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical

Maximum Units

V_IH

V_IL

I_IH

Input High Voltage

1.7

V_DD+ 0.3

Input Low Voltage

Input High Current

Input Low Current

0.7

V_DD= V_IN= 2.625V

µA

I_IL

V_DD= 2.625V, V_IN= 0V

-150

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical Maximum Units

R_IN

Input Resistance

IN-to-V_T

IN-to-VT

1.2

110

R_{DIFF_IN}

V_IH

Differential Input Resistance

Input High Voltage

INx, nINx

100

V_DD

V_IL

Input Low Voltage

V_IN– 0.1

V_DD

V_IN

Input Voltage Swing

0.1

Differential

Input Voltage Swing

V_{DIFF_IN}

INx, nINx

0.2

V_{T_IN}

IN-to-V_T

1.28

V_{REF_AC}

Output Reference Voltage

V_DD– 1.4 V_DD– 1.3 V_DD– 1.2

IDT^™/ ICS^™LVDS MULTIPLEXER

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

TABLE 4D. LVDS DC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

340

Typical

400

Maximum Units

V_OUT

Output Voltage Swing

V_{DIFF_OUT}Differential Output Voltage Swing

680

800

V_OCM

Output Common Mode Voltage

1.10

1.35

Δ V_OCM

Change in Common Mode Voltage

-50

TABLE 5. AC CHARACTERISTICS, V_DD= 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol

Parameter

Condition

Minimum Typical Maximum Units

Gpbs

GHz

f_MAX

Output Frequency

Q0:1/nQ0:1

IN-to-Q

400

250

700

600

Propagation Delay,

(Differential)% NOTE 1

t_PD

SEL-to-Q

tsk(o)

Output Skew% NOTE 2, 4

tsk(pp)

Part-to-Part Skew% NOTE 3, 4

200

Buffer Additive Phase Jitter, RMS%

Refer to Additive Phase Jitter Section,

NOTE 5

155.52MHz,

tjit

0.06

12kHz – 20MHz

MUX__ISOLATIONMux Isolation

t_R/t_FOutput Rise/Fall Time

20ꢀ to 80ꢀ

220

NOTE: All parameters are characterized at ≤ 1GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 5: Driving only one input clock.

IDT^™/ ICS^™LVDS MULTIPLEXER

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

ADDITIVE PHASE JITTER

band to the power in the fundamental. When the required offset

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using a

Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise power

present in a 1Hz band at a specified offset from the fundamental

frequency to the power value of the fundamental. This ratio is

expressed in decibels (dBm) or a ratio of the power in the 1Hz

is specified, the phase noise is called a dBc value, which simply

means dBm at a specified offset from the fundamental. By

investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

Additive Phase Jitter @

155.52MHz (12kHz to 20MHz)

= 0.06ps typical

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing specifications, phase noise measurements

has issues relating to the limitations of the equipment. Often the

noise floor of the equipment is higher than the noise floor of the

device. This is illustrated above. The device meets the noise floor

of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

PARAMETER MEASUREMENT INFORMATION

V_DD

SCOPE

V_DD

2.5V 5ꢀ

POWER SUPPLY

nIN[0:1]

IN[0:1]

GND

Float GND –

LVDS

V_IN

V_IH

Cross Points

V_IL

nQx

OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

nQx

PART 1

nQx

nQy

PART 2

tsk(pp)

tsk(o)

PART-TO-PART SKEW

OUTPUT SKEW

nIN0,

nIN1

nQ0, nQ1

80ꢀ

t_F

80ꢀ

t_R

IN0, IN1

V_OD

20ꢀ

nQ0, nQ1

Q0, Q1

t_PD

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

V_DD

out

➤

DC Input

LVDS

V_{DIFF_IN}, V_{DIFF_OUT}

800mV

(typical)

V_IN, V_OUT

V_OS/Δ V_OS

400mV

(typical)

➤

SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING

OFFSET VOLTAGE SETUP

V_DD

➤

out

LVDS

DC Input

100

_OD/Δ V_OD

➤

out

DIFFERENTIAL OUTPUT VOLTAGE SETUP

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

APPLICATION INFORMATION

LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE

The IN /nIN with built-in 50Ω terminations accepts LVDS,

input interfaces suggested here are examples only. If the driver

is from another vendor, use their termination recommendation.

Please consult with the vendor of the driver component to confirm

the driver termination requirements.

LVPECL, CML and other differential signals.The signal must meet

the V and V

input requirements. Figures 1A to 1E show

CMR

interface examples for the HiPerClockS IN/nIN input with built-in

50Ω terminations driven by the most common driver types. The

2.5V

3.3V or 2.5V

2.5V

Zo = 50 Ohm

nIN

Receiver

With

Receiver

With

Built-In

50 Ohm

2.5V LVPECL

LVDS

Built-In

50 Ohm

FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER

BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER

2.5V

Zo = 50 Ohm

nIN

Receiver

With

CML - Built-in 50 Ohm Pull-up

CML - Open Collector

Built-In

50 Ohm

Built-In

50 Ohm

FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

^WITHBUILT-IN 50Ω PULLUP

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

2.5V

Zo = 50 Ohm

nIN

Receiver With Built-In 50Ω

SSTL

FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

OUTPUTS:

LVDS OUTPUTS

INPUTS:

IN/nIN INPUTS

For applications not requiring the use of the differential input,

both IN and nIN can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from IN to ground.

All unused LVDS output pairs can be either left floating or

terminated with 100Ω across. If they are left floating, there should

be no trace attached.

2.5V LVDS DRIVER TERMINATION

transmission line environment. For buffer with multiple LVDS

driver, it is recommended to terminate the unused outputs.

Figure 2 shows a typical termination for LVDS driver in

characteristic impedance of 100Ω differential (50Ω single)

2.5V

LVDS_Driv er

100

100 Ohm Differential Transmission Line

100Ω DifferentialTransmission Line

FIGURE 2. TYPICAL LVDS DRIVER TERMINATION

2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50ΩTERMINATION UNUSED INPUT HANDLING

To prevent oscillation and to reduce noise, it is recommended

to have pull up and pull down connect to true and compliment

of the unused input as shown in Figure 3.

2.5V

680

nIN

Receiver

with

Built-In

50 Ohm

680

FIGURE 3. UNUSED INPUT HANDLING

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

VFQFN EPADTHERMAL RELEASE PATH

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as shown in Figure 4. The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

are application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended

to determine the minimum number needed. Maximum thermal

and electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as

many vias connected to ground as possible. It is also

recommended that the via diameter should be 12 to 13mils (0.30

to 0.33mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process

which may result in voids in solder between the exposed pad/

slug and the thermal land. Precautions should be taken to

eliminate any solder voids between the exposed heat slug and

the land pattern. Note: These recommendations are to be used

as a guideline only. For further information, refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadfame Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias.

The vias act as “heat pipes”. The number of vias (i.e.“heat pipes”)

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS889474.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS889474 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 2.625V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core) = V

* I

= 2.625V * 80mA = 210mW

MAX

DD_MAX

Power Dissipation at built-in terminations: Assume the input is driven by a 2.5V SSTL driver as shown in Figure 1E and

estimated approximately 1.75V drop across IN and nIN.

Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V) / (50Ω + 50Ω) = 30.6mW

Input pair for both inputs is 2 * 30.6mW = 61.2mW

Total Power

(2.625V, with all outputs switching) = 210mW + 61.2mW = 271.2mW

_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θ * Pd_total + T_A

Tj = Junction Temperature

= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air

flow and a multi-layer board, the appropriate value is 49.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.271W * 49.5°C/W = 98.4°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 6. THERMAL RESISTANCE θ FOR 24-PIN VFQFN, FORCED CONVECTION

θ vs. 0 Velocity (Meters per Second)

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

49.5°C/W

43.3°C/W

38.8°C/W

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

RELIABILITY INFORMATION

TABLE 7. θ VS. AIR FLOW TABLE FOR 24 LEAD VFQFN

θ vs. 0 Velocity (Meters per Second)

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

49.5°C/W

43.3°C/W

38.8°C/W

TRANSISTOR COUNT

The transistor count for ICS889474 is: 367

Pin compatible with SY89474U

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ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

PACKAGE OUTLINE - K SUFFIX FOR 24 LEAD VFQFN

NOTE: The following package mechanical drawing is a generic

drawing that applies to any pin count VFQFN package.This draw-

ing is not intended to convey the actual pin count or pin layout of

this device.The pin count and pinout are shown on the front page.

The package dimensions are in Table 8 below.

T^ABLE8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

MINIMUM

MAXIMUM

0.80

1.0

0.05

0.25 Reference

0.18

0.30

0.50 BASIC

N_D

N_E

2.30

2.55

2.30

0.30

2.55

0.50

Reference Document: JEDEC Publication 95, MO-220

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

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2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

TABLE 9. ORDERING INFORMATION

Part/Order Number

889474AK

Marking

89474A

9474AL

Package

Shipping Packaging Temperature

24 Lead VFQFN

tube

-40°C to 85°C

889474AKT

24 Lead VFQFN

2500 tape & reel

tube

889474AKLF

889474AKLFT

24 Lead VFQFN "Lead-Free"

2500 tape & reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and

industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT.

IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

IDT^™/ ICS^™LVDS MULTIPLEXER

ICS889474AK REV. A October 22, 2008

ICS889474

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT AND INTERNAL TERMINATION

Innovate with IDT and accelerate your future networks. Contact:

www.IDT.com

For Sales

800-345-7015

408-284-8200

For Tech Support

netcom@idt.com

480-763-2056

Fax: 408-284-2775

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Integrated Device Technology, Inc.

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San Jose, CA 95138

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Leatherhead, Surrey

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800 345 7015

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England

+408 284 8200 (outside U.S.)

+81 3 3221 9824 (fax)

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registered trademarks used to identify products or services of their respective owners.

Printed in USA

889474AK [IDT]

相关型号：

889474AKLF

889474AKLFT

889474AKT

88948

88948-102

88948-102LF

88948-112

88948-112LF

88948-202

88948-202LF

88948-212

88948-212LF