8P34S2106AHGI [IDT]
Dual 1:6 LVDS Output 1.8V / 2.5V Fanout Buffer;
| 型号： | 8P34S2106AHGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 1:6 LVDS Output 1.8V / 2.5V Fanout Buffer |
| 文件： | 总25页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 1:6 LVDS Output 1.8V / 2.5V
Fanout Buffer
8P34S2106
Datasheet
Description
Features
The 8P34S2106 is a high-performance, low-power, differential
dual 1:6 LVDS output 1.8V/2.5V fanout buffer. The device is
designed for the fanout of high-frequency, very low additive
phase-noise clock and data signals. Two independent buffer
channels are available, each channel has six low skew outputs.
High isolation between channels minimizes noise coupling. AC
characteristics such as propagation delay are matched between
channels.
▪ Dual 1:6 low skew, low additive jitter LVDS fanout buffers
▪ Matched AC characteristics across both channels
▪ High isolation between channels
▪ Low power consumption
▪ Both differential CLKA, nCLKA and CLKB, nCLKB inputs
accept LVDS, LVPECL and single-ended LVCMOS levels
▪ Maximum input clock frequency: 2GHz
▪ Output amplitudes: 350mV, 500mV (selectable)
▪ Output bank skew: 10ps typical
Guaranteed output-to-output and part-to-part skew characteristics
make the 8P34S2106 ideal for those clock distribution
applications demanding well-defined performance and
repeatability. The device is characterized to operate from a
1.8V/2.5V power supply. The integrated bias voltage references
enable easy interfacing of AC-coupled signals to the device
inputs.
▪ Output skew: 20ps typical
▪ Low additive phase jitter, RMS: 45fs typical
(fREF = 156.25MHz, 12kHz – 20MHz)
▪ Full 1.8V and 2.5V supply voltage mode
▪ Device current consumption (IDD):
— 210mA typical: 1.8V
Block Diagram
— 230mA typical: 2.5V
QA0
nQA0
▪ Lead-free (RoHS 6) packaging:
— 40-VFQFN, 6 x 6 x 0.9mm
QA1
VDDA
— 48-WL-CSP, 3.59 x 3.04 x 0.6mm
▪ -40°C to 85°C ambient operating temperature
▪ Supports case temperature up to 105°C
nQA1
51k
QA2
nQA2
CLKA
nCLKA
QA3
nQA3
51k
51k
QA4
nQA4
VDDA
Voltage
Reference A
VREFA
SELAA
51k
QA5
nQA5
QB0
nQB0
QB1
nQB1
VDDB
51k
51k
QB2
nQB2
CLKB
nCLKB
QB3
nQB3
51k
QB4
nQB4
VDDB
Voltage
Reference B
VREFB
SELAB
51k
QB5
nQB5
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8P34S2106 Datasheet
Pin Assignments for 40-VFQFN Package
Figure 1. Pin Assignments for 40-VFQFN, 6 x 6 mm Package – Top View
30 29 28 27 26 25 24 23 22 21
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
VDDQB
QB2
VDDQA
nQA3
QA3
nQB2
QB3
nQA2
QA2
nQB3
QB4
8P34S2106
nQA1
QA1
nQB4
QB5
nQA0
QA0
nQB5
VDDQB
VDDQA
1
2
3
4
5
6
7
8
9
10
Pin Descriptions for 40-VFQFN Package
Table 1. 40-VFQFN Pin Descriptions[a]
Number
Name
Type
Description
1
2
SELAB
CLKB
nCLKB
VREFB
VDDB
Input [PU]
Input [PD]
Control input. Output amplitude select for channel B.
Non-inverting differential clock/data input for channel B.
3
Input [PD/PU] Inverting differential clock/data input for channel B.
4
Output
Power
Power
Output
Bias voltage reference for the CLKB, nCLKB input pairs.
Power supply pin for the core and inputs of channel B.
Power supply pin for the core and inputs of channel A.
Bias voltage reference for the CLKA, nCLKA input pairs.
5
6
VDDA
7
VREFA
nCLKA
CLKA
SELAA
VDDQA
QA0
8
Input [PD/PU] Inverting differential clock/data input for channel A.
9
Input [PD]
Input [PU]
Power
Non-inverting differential clock/data input for channel A.
Control input. Output amplitude select for channel A.
Power supply pin for the channel A outputs QA[0:5]
Differential output pair A0. LVDS interface levels.
Differential output pair A0. LVDS interface levels.
Differential output pair A1. LVDS interface levels.
Differential output pair A1. LVDS interface levels.
10
11
12
13
14
15
Output
nQA0
QA1
Output
Output
nQA1
Output
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8P34S2106 Datasheet
Table 1. 40-VFQFN Pin Descriptions[a] (Cont.)
Number
Name
Type
Description
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
ePad
QA2
nQA2
QA3
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair A2. LVDS interface levels.
Differential output pair A2. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Power supply pin for the channel A outputs QA[0:5]
Power supply ground.
nQA3
VDDQA
GND
QA4
Differential output pair A4. LVDS interface levels.
Differential output pair A4. LVDS interface levels.
Differential output pair A5. LVDS interface levels.
Differential output pair A5. LVDS interface levels.
Differential output pair B0. LVDS interface levels.
Differential output pair B0. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Power supply ground.
nQA4
QA5
nQA5
QB0
nQB0
QB1
nQB1
GND
VDDQB
QB2
Power supply pin for the channel B outputs QB[0:5].
Differential output pair B2. LVDS interface levels.
Differential output pair B2. LVDS interface levels.
Differential output pair B3. LVDS interface levels.
Differential output pair B3. LVDS interface levels.
Differential output pair B4. LVDS interface levels.
Differential output pair B4. LVDS interface levels.
Differential output pair B5. LVDS interface levels.
Differential output pair B5. LVDS interface levels.
Power supply pin for the channel B outputs QB[0:5].
Exposed pad of package. Connect to ground.
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
VDDQB
GND_EPAD
[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.
See Table 6, DC Input Characteristics, for typical values.
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8P34S2106 Datasheet
Pin Assignments for 48-WL-CSP Package
Figure 2. Pin Assignments for 48-WL-CSP, 3.59 x 3.04mm Package – Bottom View
VDDA
QA0
QA1
QA2
QA3
QA4
VDDA
nQA0
nQA1
nQA2
nQA3
nQA4
CLKA
nCLKA
VREFA
SELAA
QA5
GND
GND
GND
GND
GND
VDDA
GND
GND
GND
GND
GND
VDDB
CLKB
nCLKB
VREFB
SELAB
QB0
VDDB
QB5
QB4
QB3
QB2
QB1
VDDB
nQB5
nQB4
nQB3
nQB2
nQB1
A
B
C
D
E
F
nQA5
nQB0
8
7
6
5
4
3
2
1
Pin Descriptions for 48-WL-CSP Package
Table 2. 48-WL-CSP Pin Descriptions
Number
Name
Type[a]
Description
Channel A
A6
B6
CLKA
nCLKA
Input [PD]
Input [PU/PD]
Output
Non-inverting and inverting differential clock/data input for channel A.
C6
VREFA
Bias voltage reference for the CLKA, nCLKA input pairs.
Control input: Output amplitude select for channel A.
Differential output pair A0. LVDS interface levels.
Differential output pair A1. LVDS interface levels.
Differential output pair A2. LVDS interface levels.
Differential output pair A3. LVDS interface levels.
Differential output pair A4. LVDS interface levels.
Differential output pair A5. LVDS interface levels.
D6
SELAA
Input [PU]
Output
B8, B7
C8, C7
D8, D7
E8, E7
F8, F7
E6, F6
A7, A8, F5
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
QA4, nQA4
QA5, nQA5
VDDA
Output
Output
Output
Output
Output
Power
Power supply pins for the core, inputs, and outputs QA[0:5] of channel A. A7,
A8 and F5 are connected.[b]
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8P34S2106 Datasheet
Table 2. 48-WL-CSP Pin Descriptions (Cont.)
Number
Name
Type[a]
Description
Channel B
A3
B3
CLKB
nCLKB
Input [PD]
Input [PU/PD]
Output
Non-inverting and inverting differential clock/data input for channel B.
C3
VREFB
Bias voltage reference for the CLKB, nCLKB input pairs.
Control input: Output amplitude select for channel B.
Differential output pair B0. LVDS interface levels.
Differential output pair B1. LVDS interface levels.
Differential output pair B2. LVDS interface levels.
Differential output pair B3. LVDS interface levels.
Differential output pair B4. LVDS interface levels.
Differential output pair B5. LVDS interface levels.
D3
SELAB
Input [PU]
Output
E3, F3
F2, F1
E2, E1
D2, D1
C2, C1
B2, B1
A1, A2, F4
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
QB4, nQB4
QB5, nQB5
VDDB
Output
Output
Output
Output
Output
Power
Power supply pins for the core, inputs and outputs QB[0:5] of channel B. A1, A2
and F4 are connected.
Ground
A4, A5, B4, B5,
C4, C5, D4, D5,
E4, E5
GND
Power
Power supply ground.
[a] Internal pull-up (PU) and pull-down (PD) resistors are indicated in parentheses.
[b] VDDA is not connected to VDDB
.
Function Tables
Table 3. SELAA Output Amplitude Selection Table
SELAA
QA Output Amplitude (mV)
0
350
500
1 (default)
Table 4. SELAB Output Amplitude Selection Table
SELAB
QB Output Amplitude (mV)
0
350
500
1 (default)
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8P34S2106 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 8P34S2106 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 5. Absolute Maximum Ratings
Item
Rating
[a]
Supply voltage, V
Inputs, VI
4.6V
DDX
-0.5V to 3.6V
Outputs, IO
Continuous current
Surge current
10mA
15mA
Input sink/source, IREF
±2mA
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
ESD - Human Body Model[b]
125°C
-65°C to 150°C
2000V
ESD - Charged Device Model[b]
1500V
[a] VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
[b] According to JEDEC JS-001-2012/JESD22-C101E.
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8P34S2106 Datasheet
DC Electrical Characteristics
Table 6. DC Input Characteristics
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input capacitance
Test Conditions
Minimum
Typical
Maximum
Units
2
pF
k
k
Input pull-down resistor
Input pull-up resistor
51
51
Table 7. Power Supply DC Characteristics, VDDA = VDDB = VDDQA = VDDQB = 1.8V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Power supply voltage
Test Conditions
Minimum
Typical
Maximum
Units
[a]
VDDX
1.71
1.8
1.89
V
QA[0:5], QB[0:5]
outputs terminated
100 between nQx, Qx
500mV amplitude
350mV amplitude
300
210
390
275
mA
mA
Core and output
supply current
[a]
IDDX
[a] VDDX: For the VFQFN package, VDDA and VDDB are the core and input supply pins; VDDQA and VDDQB supply the outputs.
For the WL-CSP package, VDDA and VDDB supply the circuits of the respective channels.
Table 8. Power Supply DC Characteristics, VDDA = VDDB = 2.1V–2.7V, TA = -40°C to 85°C
Symbol
Parameter
Power supply voltage
Test Conditions
Minimum
Typical
Maximum
Units
[a]
VDDX
2.1
2.5
2.7
V
QA[0:5], QB[0:5]
outputs terminated
100 between nQx, Qx
500mV amplitude
350mV amplitude
325
230
405
290
mA
mA
Core and output
supply current
[a]
IDDX
[a] VDDX: For the VFQFN package, VDDA and VDDB are the core and input supply pins; VDDQA and VDDQB supply the outputs.
For the WL-CSP package, VDDA and VDDB supply the circuits of the respective channels.
Table 9. LVCMOS Inputs DC Characteristics, V
= V
= V
= V
= 1.8V ± 5%, T = -40°C to 85°C
DDQB A
DDA
DDB
DDQA
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
[a]
VIH
Input high voltage SELAA, SELAB
0.75 · VDD
-0.3
VDD[a] + 0.3
V
V
[a]
VIL
IIH
IIL
Input low voltage
Input high current SELAA, SELAB
Input low current
SELAA, SELAB
0.25 · VDD
VIN = VDD[a] = 1.89V
10
µA
µA
[a]
SELAA, SELAB VIN = 0V, VDD = 1.89V
-150
[a] VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
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8P34S2106 Datasheet
Table 10. LVCMOS Inputs DC Characteristics, V
= V
= 2.1V–2.7V, T = -40°C to 85°C
DDA
DDB
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
[a]
VIH
Input high voltage SELAA, SELAB
0.75 · VDD
-0.3
VDD[a] + 0.3
V
V
[a]
VIL
IIH
IIL
0.20 * V
Input low voltage
Input high current SELAA, SELAB
Input low current
SELAA, SELAB
DD
VIN = VDD[a] = 1.89V
10
µA
µA
[a]
SELAA, SELAB VIN = 0V, VDD = 1.89V
-150
[a] VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
Table 11. Differential Inputs Characteristics, V
= V
= V
= V
= 1.8V ± 5%, T = -40°C to 85°C
DDQB A
DDA
DDB
DDQA
Symbol
IIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input high current CLKA, nCLKA
CLKB, nCLKB
VIN = VDD[a] = 1.89V
150
µA
[a]
CLKA, CLKB
VIN = 0V, VDD = 1.89V
-10
-150
0.9
µA
µA
V
IIL
Input low current
[a]
nCLKA, nCLKB VIN = 0V, VDD = 1.89V
VREFA, B Reference voltage[b]
IREF = +100µA, VDD[a] = 1.8V
1.30
[a] VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
[b] VREF[A:B] specification is applicable to the AC-coupled input interfaces shown in Figure 6 and Figure 7.
Table 12. Differential Inputs Characteristics, V
= V
= 2.1V–2.7V, T = -40°C to 85°C
DDB A
DDA
Symbol
IIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input high current CLKA, nCLKA
CLKB, nCLKB
VIN = VDD[a] = 1.89V
150
µA
[a]
CLKA, CLKB
VIN = 0V, VDD = 1.89V
-10
-150
1.5
µA
µA
V
IIL
Input low current
[a]
nCLKA, nCLKB VIN = 0V, VDD = 1.89V
IREF = +100µA, VDD[a] = 1.8V
VREFA, B Reference voltage[b]
1.9
[a] VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
[b] VREF[A:B] specification is applicable to the AC-coupled input interfaces shown in Figure 6 and Figure 7.
Table 13. LVDS DC Characteristics, VDDA = VDDB = VDDQA = VDDQB = 1.8V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
VOS
VOD Magnitude Change
VOS Magnitude Change
50
50
mV
mV
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8P34S2106 Datasheet
Table 14. LVDS DC Characteristics, VDDA = VDDB = 2.1V–2.7V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
VOS
VOD Magnitude Change
VOS Magnitude Change
50
50
mV
mV
AC Electrical Characteristics
[a]
Table 15. AC Electrical Characteristics, VDDx = 1.8V ± 5%, 2.1V–2.7V, TA = -40°C to 85°C
Test Conditions
Symbol
fREF
Parameter
Minimum Typical
Maximum
Units
Input frequency
Input edge rate
2
GHz
V/ns
ps
V/t
tPD
1.5
Propagation delay[b], [c] CLKA to any QAx, CLKB to any nQBx
Output skew[d], [e]
100
255
20
10
5
400
40
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
ps
Output bank skew[e], [f]
Pulse skew[g]
Part-to-part skew[e], [h]
25
ps
fREF = 100MHz
25
ps
200
80
ps
Buffer Additive Phase
Jitter, RMS;
500mV amplitude;
refer to Additive Phase
Jitter
f
REF = 156.25MHz;
Integration range: 1kHz – 40MHz
REF = 156.25MHz square wave, VPP = 1V;
60
45
fs
tJIT
f
60
fs
Integration range: 12kHz – 20MHz
N(30M) Clock single-side band
30MHz offset from carrier and noise floor
< -160
-55
dBc/Hz
dB
phase noise
f
QA = 491.52MHz, fQB = 61.44MHz;
Spurious suppression,
measured between neighboring outputs
tJIT, SP
coupling between
channels
fQA = 491.52MHz, fQB = 15.36MHz;
measured between neighboring outputs
-65
dB
10% to 90%, outputs loaded with 100
20% to 80%, outputs loaded with 100
10% to 90%, outputs loaded with 100
20% to 80%, outputs loaded with 100
150
90
400
160
420
190
1.2
ps
ps
ps
ps
V
Output rise/ fall time,
VDDx = 1.8V ±5%
tR / tF
200
110
Output rise/ fall time,
VDDx = 2.1V–2.7V
VPP
Input voltage
amplitude
CLKA,
CLKB
0.15
0.3
VPP_DIFF
Differential
input voltage
amplitude
CLKA,
CLKB
2.4
V
V
VCMR
Common mode
input voltage[i]
1.1
VDD[j] – (VPP/2
)
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8P34S2106 Datasheet
[a]
Table 15. AC Electrical Characteristics, VDDx = 1.8V ± 5%, 2.1V–2.7V, TA = -40°C to 85°C
(Cont.)
Test Conditions
Symbol
Parameter
Minimum Typical
Maximum
Units
SELAA, SELAB = 0,
outputs loaded with 100
247
350
350
500
454
650
mV
Differential
output voltage
VOD
SELAA, SELAB = 1,
mV
outputs loaded with 100
SELAA, SELAB = 0
SELAA, SELAB = 1
SELAA, SELAB = 0
SELAA, SELAB = 1
0.8
0.7
V
V
V
V
Offset voltage,
VDDx = 1.8V ±5%
VOS
1.51
1.41
Offset voltage,
VDDx = 2.1–2.7V
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[b] Measured from the differential input crossing point to the differential output crossing point.
[c] Input VPP = 400mV.
[d] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.
[e] This parameter is defined in accordance with JEDEC Standard 65.
[f] Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
[g] Output pulse skew is the absolute value of the difference of the propagation delay times: tPLH - tPHL .
[h] Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
[i] Common Mode Input Voltage is defined as the cross-point voltage.
[j]
VDDX denotes VDDA, VDDB, VDDQA, and VDDQB for the QFN package. VDDX denotes VDDA and VDDB for the WL-CSP package.
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8P34S2106 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value
of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental.
When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the
fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Figure 3. Additive Phase Jitter. Frequency: 156.25MHz, Integration range: 12kHz to 20MHz = 45fs Typical
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
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8P34S2106 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Outputs
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace
attached.
VREFX
The unused VREFA and VREFB pins can be left floating. We recommend that there is no trace attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 4 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage
swing. For example, if the input clock swing is 1.8V and VDD = 1.8V, R1 and R2 value should be adjusted to set V1 at 0.9V. The values
below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver.
When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than
1V/ns. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of
the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by using a differential signal.
Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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8P34S2106 Datasheet
1.8V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL and other differential signals. The differential input signal must meet both the VPP and VCMR
input requirements. Figure 5 to Figure 7 show interface examples for the CLK /nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver termination requirements.
Figure 5. Differential Input Driven by an LVDS Driver – DC Coupling
Figure 6. Differential Input Driven by an LVDS Driver – AC Coupling
Figure 7. Differential Input Driven by an LVPECL Driver – AC Coupling
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8P34S2106 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS
compliant devices with two types of output structures: current source and voltage source.
The standard termination schematic as shown in Figure 8 can be used with either type of output structure. Figure 9, which can also be
used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with the output.
Figure 8. Standard LVDS Termination
Figure 9. Optional LVDS Termination
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8P34S2106 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 10. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis
and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to
13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the application note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 10. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (Draw ing not to Scale)
SOLDER
SOLDER
PIN
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
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8P34S2106 Datasheet
Case Temperature Considerations for VFQFN Package
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.
The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific
temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to
the PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the
junction-to-board thermal characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not
exceed the maximum allowed junction temperature in Absolute Maximum Ratings.
The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:
TJ = TCB + JB x PD, where
TJ = Junction temperature at steady state condition in (oC).
TCB = Case temperature (Bottom) at steady state condition in (oC).
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board
measured at the top surface of the board.
PD = Power dissipation (W) in desired operating configuration.
TJ
TCB
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from
the IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case
temperature (TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively
the same. An improper connection can lead to increased junction temperature, increased power consumption and decreased electrical
performance. In addition, there could be long-term reliability issues and increased failure rate.
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x PD
Package type
Body size (mm)
ePad size (mm)
Thermal Via
40-VFQFN
6 x 6 x 0.9
4.65 x 4.65
4 x 4 Matrix
1.5oC/W
105oC
JB
TCB
PD
0.71W
VDDx
1.89V
For the variables above, the junction temperature is equal to 106.1oC. Since this is below the maximum junction temperature of 125oC,
there are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced
convection is 115oC, this device can function without the degradation of the specified AC or DC parameters.
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8P34S2106 Datasheet
Case Temperature Considerations for WL-CSP Package
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.
The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific
temperature. For this type of application, it is recommended to use the junction-to-board thermal characterization parameter, JB, to
calculate the junction temperature (TJ) and ensure it does not exceed the maximum allowed junction temperature in Absolute Maximum
Ratings.
The junction-to-board thermal characterization parameter, JB, is calculated as follows:
TJ = TCB + JB PD, where
TJ = Junction temperature at steady state condition in (oC).
TCB = Case temperature (Bottom) at steady state condition in (oC).
JB = Junction-to-board thermal characterization parameter.
PD = Power dissipation (W) in desired operating configuration.
Example calculation for junction temperature (TJ): TJ = TCB JB PD
Package type
Body size (mm)
JB
48-WL-CSP
3.59 x 3.04 x 0.6
5.86oC/W
105oC
TCB
PD_IMAX
VDDx
1.0935W
2.7V
For the variables above, the junction temperature is equal to 111.41oC. Since this is below the maximum junction temperature of 125oC,
there are no long term reliability concerns. In addition, since the junction temperature at which the device was characterized using forced
convection is 115oC, this device can function without the degradation of the specified AC or DC parameters.
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8P34S2106 Datasheet
Pow er Considerations
This section provides information on power dissipation and junction temperature for the 8P34S2106.
Equations and example calculations are also provided.
1. Power Dissipation.
The following is the power dissipation for VDD = 1.8V + 5% = 1.89V, which gives worst case results.
Maximum current at 85°C: VDD_MAX = 1.89V: IDD_MAX = 390mA
Maximum current at 85°C, VDD_MAX = 2.7V: IDD_MAX = 405mA
Power_MAX = VDD_MAX * IDD_MAX = 1.89V * 390mA = 737.1mW
Power_MAX = VDD_MAX * IDD_MAX = 2.7V * 405mA = 1,093.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that
the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 24.6°C/W per Table 16.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.7371W * 24.6°C/W = 103.2°C. This is below the limit of 125°C. (40-VFQFN package, VDDx = 1.89V)
85°C + 1.0935W * 24.6°C/W = 112°C. This is below the limit of 125°C. (40-VFQFN package, VDDx = 2.7V)
85°C + 0.7371W * 32.32°C/W = 108.9°C. This is below the limit of 125°C. (48-WL-CSP package, VDDx = 1.89V)
85°C + 1.0935W * 32.32°C/W = 120.4°C. This is below the limit of 125°C. (48-WL-CSP package, VDDx = 2.7V)
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Table 16. Thermal Resistance JA, Forced Convection
JA (°C/W) vs. Air Flow (m/s)
Meters per Second
0
1
2
40-VFQFN Multi-Layer PCB, JEDEC Standard Test Boards
48-WL-CSP Multi-Layer PCB, JEDEC Standard Test Boards
24.6
21.2
19.6
32.32
28.35
26.05
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8P34S2106 Datasheet
Package Draw ings
Figure 11. 40-VFQFN Package Outline and Dimensions (Sheet 1)
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8P34S2106 Datasheet
Figure 12. 40-VFQFN Package Outline and Dimensions (Sheet 2)
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8P34S2106 Datasheet
Figure 13. 40-VFQFN Recommended Land Pattern (Sheet 3)
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8P34S2106 Datasheet
Figure 14. 48-WL-CSP Package Outline and Dimensions (Sheet 1)
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8P34S2106 Datasheet
Figure 15. 48-WL-CSP Package Outline and Dimensions (Sheet 2)
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8P34S2106 Datasheet
Marking Diagram
40-VFQFN Package
1. Line 1 and line 2 indicates the part number.
2. Line 3:
▪ “#” indicates stepping.
▪ “YYWW” indicates the date code (YY are the last two digits of the year, and
“WW” is a work week number that the part was assembled.
▪ “$” indicates the mark code.
48-WL-CSP Package
1. Line 1 and line 2 indicates the part number.
2. Line 3:
▪ “#” indicates stepping.
▪ “YYWW” indicates the date code (YY are the last two digits of the year, and
“WW” is a work week number that the part was assembled.
▪ “$” indicates the mark code.
Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8P34S2106NLGI
8P34S2106NLGI8
IDT8P34S2106NLGI
IDT8P34S2106NLGI
Tray
Tape & Reel, Pin 1 Orientation:
EIA-481-C
40-VFQFN, 6 x 6 x 0.9mm
-40°C to 85°C
8P34S2106NLGI/W
IDT8P34S2106NLGI
Tape & Reel, Pin 1 Orientation:
EIA-481-D/E
8P34S2106AHGI
8P34S2106AHGI8
IDT8P34S2106AHGI
IDT8P34S2106AHGI8
Tray
48-WL-CSP, 3.59 x 3.04 x
0.6mm
-40°C to 105°C
Tape & Reel, Pin 1 Orientation:
EIA-481-D/E
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8P34S2106 Datasheet
Table 17. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
8
Quadrant 1 (EIA-481-C)
/W
Quadrant 2 (EIA-481-D/E)
Revision History
Revision Date
Description of Change
Added information about the 48-WL-CSP package option.
July 5, 2017
October 20, 2016
▪ Page 1, Features, added Device current consumption.
▪ Page 9, added Additive Phase Jitter.
▪ Page 19, added Marking Diagram.
▪ Updated datasheet formatting.
July 28, 2016
July 8, 2016
Features Section: corrected phase jitter bullet spec from < 50fs to 45fs.
Initial release.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
©2017 Integrated Device Technology, Inc.
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July 5, 2017
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