8SLVD2102 [IDT]
Dual 1:2, LVDS Output Fanout Buffer;
| 型号： | 8SLVD2102 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual 1:2, LVDS Output Fanout Buffer |
| 文件： | 总18页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 1:2, LVDS Output Fanout Buffer
8SLVD2102
Datasheet
Description
Features
The 8SLVD2102 is a high-performance differential dual 1:2 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2102 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2102 ideal for those clock distribution applications
demanding well-defined performance and repeatability.
• Two 1:2, low skew, low additive jitter LVDS fanout buffers
• Two differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS and LVPECL
• Maximum input clock frequency: 2GHz
• Output bank skew: 15ps (maximum)
Two independent buffers with two low skew outputs each are
available. The integrated bias voltage generators enables easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
• Propagation delay: 300ps (maximum)
• Low additive phase jitter: 200fs, RMS (maximum);
f
REF = 156.25MHz, VPP = 1V, VCMR = 1V,
Integration Range 10kHz - 20MHz
• 2.5V supply voltage
• Maximum device current consumption (IDD): 90mA
• Lead-free (RoHS 6) 16-Lead VFQFPN package
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
V
DD
QA0
nQA0
15
14
13
12
PCLKA
16
1
2
3
4
nQA1
QA1
GND
EN
nPCLKA
QA1
nQA1
11
10
9
8SLVD2102I
nQA0
QA0
PCLKB
nPCLKB
V
DD
QB0
nQB0
PCLKB
5
6
7
8
nPCLKB
QB1
nQB1
Voltage
Reference
VREF
16-pin, 3.0 x 3.0 mm VFQFPN Package
V
DD
EN
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8SLVD2102 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
GND
Power
Input
Input
Input
Power supply ground.
Pullup/
Pulldown
2
3
4
EN
Output enable pin.
PCLKB
nPCLKB
Pulldown
Non-inverting differential clock/data input.
Inverting differential clock/data input. VDD/2 default when left floating.
Pullup/
Pulldown
5
6
VDD
Power
Input
Power supply pin.
PCLKA
Pulldown
Non-inverting differential clock/data input.
Pullup/
Pulldown
7
nPCLKA
Input
Inverting differential clock/data input. VDD/2 default when left floating.
8
VREF
Output
Output
Output
Output
Output
Bias voltage reference for the PCLKx, nPCLKx inputs.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
9, 10
11, 12
13, 14
15, 16
QA0, nQA0
QA1, nQA1
QB0, nQB0
QB1, nQB1
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
Input Pulldown
2
pF
RPULLDOWN
PCLK inputs
51
51
51
51
k
k
k
k
Resistor
Input Pullup
Resistor
RPULLUP
PCLK inputs
EN input
Input Pulldown
Resistor
RPULLDOWN
Input Pullup
Resistor
RPULLUP
EN input
Table 3. EN Input Selection Function Table
Input
EN
Operation
Outputs are disabled and outputs are static at Qx = 0 (low level) and nQx = 1 (high level).
0 (Low)
Bank A outputs are enabled and Bank B outputs are disabled at the following static levels: QBx = 0 (low level) and
nQBx = 1 (high level).
1 (High)
Open
All outputs enabled.
NOTE: EN is an asynchronous control.
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
125C
-65C to 150C
2000V
ESD - Human Body Model; NOTE 1
ESD - Charged Device Model; NOTE 1
1500V
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Power Supply Voltage
2.375
2.5
2.625
V
All outputs terminated 100
IDD
Power Supply Current
80
90
mA
between nQx, Qx
Table 4B. Output Enable (EN) Input DC Characteristics, VDD = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
VMID
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input Voltage - Open Pin
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Open
VDD / 2
0.8 * VDD
-0.3
VDD + 0.3
0.2 * VDD
150
V
VIL
V
IIH
VDD = VIN = 2.625V
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-150
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Table 4C. Differential Input Characteristics, VDD = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input
IIH
PCLKA, nPCLKA
High Current PCLKB, nPCLKB
VDD = VIN = 2.625V
150
µA
PCLKA, PCLKB
Input
VDD = 2.625V, VIN = 0V
VDD = 2.625V, VIN = 0V
VDD = 2.5V, IREF = +100µA
-10
-150
1.00
0.15
0.2
µA
µA
V
IIL
Low Current
nPCLKA, nPCLKB
VREF_AC Reference Voltage for Input Bias
1.35
1.6
fREF < 1.5 GHz
V
VPP
Peak-to-Peak Voltage; NOTE 1
fREF > 1.5 GHz
1.6
V
Common Mode Input Voltage;
NOTE 1, 2
VCMR
1
VDD – VPP/2
V
NOTE 1: VIL should not be less than -0.3V. VIH should be less than VDD.
NOTE 2: Common mode input voltage is defined at the crosspoint.
Table 4D. LVDS Output DC Characteristics, VDD = 2.5V ± 5%, T = -40°C to 85°C°
A
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
VOD
Differential Output Voltage
100 termination between nQx, Qx
100 termination between nQx, Qx
100 termination between nQx, Qx
100 termination between nQx, Qx
247
454
50
VOD
VOS
VOD Magnitude Change
Offset Voltage
1.0
1.4
50
VOS
VOS Magnitude Change
mV
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Table 5. AC Electrical Characteristics, VDD = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
V/ns
fREF
Input Frequency
2
V/t
Input Edge Rate
0.75
100
PCLKA, nPCLKA to QA[0:1], nQA[0:1],
PCLKB, nPCLKB to QB[0:1], nQB[0:1]
tPD
Propagation Delay; NOTE 1
196
300
ps
Channel Isolation
75
14
7
dB
ps
ps
ps
ps
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Output Skew; NOTE 2, 3
Output Bank Skew; NOTE 3
Pulse Skew
QA[0:1], nQA[0:1], QB[0:1], nQB[0:1]
Between Outputs within Each Bank
50% Input Duty Cycle, fREF = 100MHz
40
15
-50
50
Part-to-Part Skew; NOTE 3, 4
200
fREF = 1228.8MHz, VPP = 0.2V, VCMR = 1V
Integration Range: 10kHz – 20MHz
20
140
80
50
fs
fs
fs
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
fREF = 156.25MHz, VPP = 0.5V, VCMR = 1V
Integration Range: 10kHz – 20MHz
tJIT
250
200
fREF = 156.25MHz, VPP = 1V, VCMR = 1V
Integration Range: 10kHz – 20MHz
fQB0 = 500MHz, VPP (PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
68
dB
fQA1 = 62.5MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
Spurious Suppression,
Coupling from QA1 to QB0
tJIT, SP
fQB0 = 500MHz, VPP (PCLKB) = 0.15V,
VCMR(PCLKB) = 1V and
74
dB
ps
fQA1 = 15.625MHz, VPP (PCLKA) = 1V,
VCMR(PCLKA) = 1V
tR / tF
Output Rise/ Fall Time
20% to 80%
120
200
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHz, VPP = 1V
Integration Range (10kHz to 20MHz) = 80fs (typical)
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Rohde & Schwarz SMA100 as the input source.
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Parameter Measurement Information
V
DD
nPCLKA[0:1],
nPCLKB[0:1]
V
DD
PCLKA[0:1],
PCLKB[0:1]
GND
LVDS Output Load Test Circuit
Differential Input Level
nPCLKA[0:1],
nPCLKB[0:1]
nQx
Qx
PCLKA[0:1],
PCLKB[0:1]
nQy
nQy
Qy
Qy
tPLH
tPHL
tsk(p)= |tPHL - tPLH
|
Pulse Skew
Output Skew
nQA[0:1],
nQB[0:1]
Part 1
nQx
80%
80%
Qx
VOD
20%
QA[0:1],
Part 2
20%
nQy
nQB[0:1]
tF
tR
Qy
tsk(pp)
Part-to-Part Skew
Output Rise/Fall Time
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Parameter Measurement Information, continued
Spectrum of Output Signal Q
Active Channel
A0
nQX1
QX1
Channel_ISOL = A0 – A1
nQX0
Inactive Channel
A1
QX0
tsk(b)
ƒ
(fundamental)
Frequency
X = A or B
Bank Skew
Channel Isolation
nPCLKA[0:1],
nPCLKB[0:1]
PCLKA[0:1],
PCLKB[0:1]
nQA[0:1],
nQB[0:1]
QA[0:1],
nQB[0:1]
tPD
Propagation Delay
Offset Voltage Setup
Differential Output Voltage Setup
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Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
PCLK/nPCLK Inputs
LVDS Outputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from PCLK to
ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1 = VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V1 in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 2.5V,
R1 and R2 value should be adjusted to set V1 at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Suggest edge
rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, and other differential
signals. Both signals must meet the VPP and VCMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
2.5V
2.5V
PCLK
nPCLK
LVPECL
Input
LVPECL
Figure 2A. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 2B. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
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LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Receiver
LVDS
Driver
ZT
Figure 3A. Standard Termination
ZT
ZO ZT
LVDS
Driver
2
ZT
2
LVDS
Receiver
C
Figure 3B. Optional Termination
LVDS Termination
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VFQFPN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
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Power Considerations
This section provides information on power dissipation and junction temperature for the 8SLVD2102. Equations and example calculations are
also provided.
1. Power Dissipation.
The total power dissipation for the 8SLVD2102 is the sum of the core power plus the output power dissipation due to the load. The following is
the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
The maximum current at 85°C is as follows: IDD_MAX = 84mA
•
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 84mA = 220.5mW
Total Power_MAX = 220.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.221W * 74.7°C/W = 101.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFPN, Forced Convection
JA at 0 Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
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Reliability Information
Table 7. vs. Air Flow Table for a 16 Lead VFQFPN
JA
JA at 0 Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count for the 8SLVD2102 is: 993
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Package Outline Drawings
The package outline drawings are located at the end of this document. The package information is the most current data available and is
subject to change without notice or revision of this document.
Ordering Information
Table 8. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8SLVD2102NLGI
2102I
16 Lead VFQFPN, Lead-Free
Tube
-40C to 85C
Tape & Reel
pin 1 orientation: EIA-481-C
8SLVD2102NLGI8
8SLVD2102NLGI/W
2102I
2102I
16 Lead VFQFPN, Lead-Free
16 Lead VFQFPN, Lead-Free
-40C to 85C
-40C to 85C
Tape & Reel
pin 1 orientation: EIA-481-D
Table 9. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
8
Quadrant 1 (EIA-481-C)
/W
Quadrant 2 (EIA-481-D)
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Revision History
Revision Date
Description of Change
• Updated the package outline drawings; however, no technical changes.
• Replaced the package term VFQFN with VFQFPN.
January 21, 2018
Section , “Pin Assignment” - updated Pin Assignment format.
November 11, 2015 Section , “Parameter Measurement Information, continued” - changed MUX Isolation to Channel Isolation.
Throughout the datasheet, deleted “IDT” prefix and “I” suffix from the part number.
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8SLVD2102 January 21, 2018
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©2018 Integrated Device Technology, Inc.
16-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad
NL/NLG16P2, PSC-4169-02, Rev 05, Page 1
ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ
16-VFQFPN Package Outline Drawing
3.0 x 3.0 x 0.9 mm, 0.5mm Pitch, 1.70 x 1.70 mm Epad
NL/NLG16P2, PSC-4169-02, Rev 05, Page 2
Package Revision History
Description
Rev 04 Remove Bookmak at Pdf Format & Update Thickness Tolerance
Change QFN to VFQFPN
Date Created Rev No.
Oct 25, 2017
Jan 18, 2018
Rev 05
ꢀ,QWHJUDWHGꢀ'HYLFHꢀ7HFKQRORJ\ꢁꢀ,QFꢂ
相关型号：
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