首页 |元器件品牌

8T49N203A-012NLGI [IDT]

PLL/Frequency Synthesis Circuit, PQCC40;
8T49N203A-012NLGI
型号： 8T49N203A-012NLGI
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

PLL/Frequency Synthesis Circuit, PQCC40
文件： 总40页 (文件大小：1222K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
FemtoClock® NG Universal Frequency  
Translator  
IDT8T49N203I  
DATA SHEET  
General Description  
Features  
The IDT8T49N203I is a highly flexible FemtoClock® NG general  
purpose, low phase noise Universal Frequency Translator /  
Synthesizer with alarm and monitoring functions suitable for  
networking and communications applications. It is able to generate  
any output frequency in the 0.98MHz - 312.5MHz range and most  
output frequencies in the 312.5MHz - 1,300MHz range (see Table 3  
for details). A wide range of input reference clocks and a range of  
low-cost fundamental mode crystal frequencies may be used as the  
source for the output frequency.  
• Fourth generation FemtoClock® NG technology  
• Universal Frequency Translator (UFT) / Frequency Synthesizer  
• Two outputs, individually programmable as LVPECL or LVDS  
• Both outputs may be set to use 2.5V or 3.3V output levels  
• Programmable output frequency: 0.98MHz up to 1,300MHz  
• Zero ppm frequency translation  
• Two differential inputs support the following input types:  
LVPECL, LVDS, LVHSTL, HCSL  
The IDT8T49N203I has three operating modes to support a very  
broad spectrum of applications:  
• Input frequency range: 8kHz - 710MHz  
• Crystal input frequency range: 16MHz - 40MHz  
1) •FrSeyqnutehnecsyizeSsynotuhtepsuitzefrrequencies from a 16MHz - 40MHz  
• Two factory-set register configurations for power-up default state  
• Power-up default configuration pin or register selectable  
• Configurations customized via One-Time Programmable ROM  
fundamental mode crystal.  
• Fractional feedback division is used, so there are no  
requirements for any specific crystal frequency to produce the  
desired output frequency with a high degree of accuracy.  
2
• Settings may be overwritten after power-up via I C  
2
• I C Serial interface for register programming  
2) •HAigphp-Blicaantdiownisd:thPCFrIeEqxupernecsys,TCraonmslpautotirng, General Purpose  
• RMS phase jitter at 155.52MHz, using a 40MHz crystal LVDS  
Output (12kHz - 20MHz): 439fs (typical), Low Bandwidth Mode  
(FracN)  
• Translates any input clock in the 16MHz - 710MHz frequency  
range into any supported output frequency.  
• RMS phase jitter at 400MHz, using a 40MHz crystal  
(12kHz - 40MHz):285fs (typical), Synthesizer Mode (Integer FB)  
• This mode has a high PLL loop bandwidth in order to track input  
reference changes, such as Spread-Spectrum Clock  
modulation, so it will not attenuate much jitter on the input  
reference.  
• Output supply voltage modes:  
VCC/VCCA/VCCO  
3.3V/3.3V/3.3V  
3.3V/3.3V/2.5V (LVPECL only)  
2.5V/2.5V/2.5V  
3) •LoAwp-pBliacantdiownidst:hNFertewqoureknincgy&TrCanosmlamtournications.  
• Translates any input clock in the 8kHz -710MHz frequency  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
Pin Assignment  
range into any supported output frequency.  
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz  
range and makes use of an external crystal to provide  
significant jitter attenuation.  
This device provides two factory-programmed default power-up  
configurations burned into One-Time Programmable (OTP) memory.  
The configuration to be used is selected by the CONFIG pin. The two  
configurations are specified by the customer and are programmed by  
IDT during the final test phase from an on-hand stock of blank  
devices. The two configurations may be completely independent of  
one another.  
30 29 28 27  
23 22 21  
26 25 24  
31  
20  
nc  
CLK_ACTIVE  
nc  
nc  
32  
33  
34  
35  
36  
37  
38  
39  
40  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IDT8T49N203I  
S_A0  
S_A1  
CONFIG  
SCLK  
SDATA  
VCC  
LF0  
40 Lead VFQFN  
6mm x 6mm x 0.925mm  
K Package  
LF1  
One usage example might be to install the device on a line card with  
two optional daughter cards: an OC-12 option requiring a 622.08MHz  
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet  
option requiring a 125MHz LVPECL clock translated from the same  
19.44MHz input reference.  
VEE  
VCCA  
Top View  
HOLDOVER  
CLK0BAD  
CLK1BAD  
XTALBAD  
PLL_BYPASS  
nc  
To implement other configurations, these power-up default settings  
1
2
3
4
8
9 10  
5
6 7  
2
can be overwritten after power-up using the I C interface and the  
device can be completely reconfigured. However, these settings  
would have to be re-written next time the device powers-up.  
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.  
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
1
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Complete Block Diagram  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
2
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Table 1. Pin Descriptions  
Number  
Name  
Type  
Description  
1
2
XTAL_IN  
XTAL_OUT  
Crystal Oscillator interface designed for 12pF parallel resonant crystals.  
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.  
Core supply pins. All must be either 3.3V or 2.5V.  
Input  
3, 7, 13, 29  
VCC  
Power  
Input clock select. Selects the active differential clock input. LVCMOS/LVTTL  
interface levels.  
0 = CLK0, nCLK0 (default)  
1 = CLK1, nCLK1  
4
CLK_SEL  
Input  
Pulldown  
5
6
CLK0  
Input  
Input  
Pulldown  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
Inverting differential clock input. VCC/2 default when left floating (set by the  
internal pullup and pulldown resistors).  
nCLK0  
8, 21, 35  
9
VEE  
Power  
Input  
Negative supply pins.  
CLK1  
Pulldown  
Non-inverting differential clock input.  
Pullup/  
Pulldown  
Inverting differential clock input. VCC/2 default when left floating (set by the  
internal pullup and pulldown resistors).  
10  
nCLK1  
nc  
Input  
11, 19,  
20, 32  
Unused  
No connect. These pins are to be left unconnected.  
Bypasses the VCXO PLL. In bypass mode, outputs are clocked off the falling  
edge of the input reference. LVCMOS/LVTTL interface levels.  
0 = PLL Mode (default)  
12  
PLL_BYPASS  
Input  
Pulldown  
1 = PLL Bypassed  
2
14  
15  
SDATA  
SCLK  
I/O  
Pullup  
Pullup  
I C Data Input/Output. Open drain.  
2
Input  
I C Clock Input. LVCMOS/LVTTL interface levels.  
Configuration Pin. Selects between one of two factory programmable pre-set  
power-up default configurations. The two configurations can have different  
output/input frequency translation ratios, different PLL loop bandwidths, etc.  
2
16  
CONFIG  
Input  
Pulldown  
These default configurations can be overwritten after power-up via I C if the  
user so desires. LVCMOS/LVTTL interface levels.  
0 = Configuration 0 (default)  
1 = Configuration 1  
2
17  
18  
S_A1  
S_A0  
Input  
Input  
Pulldown  
Pulldown  
I C Address Bit 1. LVCMOS/LVTTL interface levels.  
2
I C Address Bit 0. LVCMOS/LVTTL interface levels.  
Active High Output Enable for Q1, nQ1. LVCMOS/LVTTL interface levels.  
0 = Output pins high-impedance  
22  
OE1  
Input  
Pullup  
1 = Output switching (default)  
Differential output pair. Output type is programmable to LVDS or LVPECL  
interface levels.  
23, 24  
25  
nQ1, Q1  
VCCO  
Output  
Power  
Output  
Output supply pins for Q1, nQ1 and Q0, nQ0 outputs. Either 2.5V or 3.3V.  
Differential output pair. Output type is programmable to LVDS or LVPECL  
interface levels.  
26, 27  
nQ0, Q0  
Active High Output Enable for Q0, nQ0. LVCMOS/LVTTL interface levels.  
0 = Output pins high-impedance  
1 = Output switching (default)  
28  
30  
OE0  
Input  
Pullup  
Lock Indicator - indicates that the PLL is in a locked condition. LVCMOS/LVTTL  
interface levels.  
LOCK_IND  
Output  
Indicates which of the two differential clock inputs is currently selected.  
LVCMOS/LVTTL interface levels.  
0 = CLK0, nCLK0 differential input pair  
31  
Output  
CLK_ACTIVE  
1 = CLK1, nCLK1 differential input pair  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
3
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Number  
Name  
Type  
Description  
Analog  
I/O  
33, 34  
LF0, LF1  
VCCA  
Loop filter connection node pins. LF0 is the output. LF1 is the input.  
Analog supply voltage. See Applications section for details on how to connect  
this pin.  
36  
37  
Power  
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL  
interface levels.  
0 = Device is locked to a valid input reference  
1 = Device is not locked to a valid input reference  
HOLDOVER  
Output  
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.  
0 = Input Clock 0 is switching within specifications  
1 = Input Clock 0 is out of specification  
38  
39  
40  
CLK0BAD  
CLK1BAD  
XTALBAD  
Output  
Output  
Output  
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.  
0 = Input Clock 1 is switching within specifications  
1 = Input Clock 1 is out of specification  
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.  
0 = crystal is switching within specifications  
1 = crystal is out of specification  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical  
3.5  
Maximum  
Units  
pF  
Input Capacitance  
Input Pullup Resistor  
Input Pulldown Resistor  
RPULLUP  
RPULLDOWN  
51  
kΩ  
51  
kΩ  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
4
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Functional Description  
The IDT8T49N203I is designed to provide two copies of almost any  
desired output frequency within its operating range (0.98 - 1300MHz)  
from any input source in the operating range (8kHz - 710MHz). It is  
capable of synthesizing frequencies from a crystal or crystal  
oscillator source. The output frequency is generated regardless of  
the relationship to the input frequency. The output frequency will be  
exactly the required frequency in most cases. In most others, it will  
only differ from the desired frequency by a few ppb. IDT configuration  
software will indicate the frequency error, if any. The IDT8T49N203I  
can translate the desired output frequency from one of two input  
clocks. Again, no relationship is required between the input and  
output frequencies in order to translate to the output clock rate. In this  
frequency translation mode, a low-bandwidth, jitter attenuation option  
is available that makes use of an external fixed-frequency crystal or  
crystal oscillator to translate from a noisy input source. If the input  
clock is known to be fairly clean or if some modulation on the input  
needs to be tracked, then the high-bandwidth frequency translation  
mode can be used, without the need for the external crystal.  
ratios within the IDT8T49N203I for the two different card  
configurations. Access via I C would not be necessary for operation  
using either of the internal configurations.  
2
Operating Modes  
The IDT8T49N203I has three operating modes which are set by the  
MODE_SEL[1:0] bits. There are two frequency translator modes -  
low bandwidth and high bandwidth and a frequency synthesizer  
mode. The device will operate in the same mode regardless of which  
configuration is active.  
Please make use of IDT-provided configuration applications to  
determine the best operating settings for the desired configurations  
of the device.  
Output Dividers & Supported Output Frequencies  
In all 3 operating modes, the output stage behaves the same way, but  
different operating frequencies can be specified in the two  
configurations.  
The input clock references and crystal input are monitored  
continuously and appropriate alarm outputs are raised both as  
register bits and hard-wired pins in the event of any  
out-of-specification conditions arising. Clock switching is supported  
in manual, revertive & non-revertive modes.  
The internal VCO is capable of operating in a range anywhere from  
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of  
the desired output frequency that results in a VCO operating  
frequency within that range. The output divider stage N[10:0] is  
limited to selection of integers from 2 to 2046. Please refer to Table 3  
for the values of N applicable to the desired output frequency.  
The IDT8T49N203I has two factory-programmed configurations that  
may be chosen from as the default operating state after reset. This is  
intended to allow the same device to be used in two different  
2
applications without any need for access to the I C registers. These  
Table 3. Output Divider Settings & Frequency Ranges  
2
defaults may be over-written by I C register access at any time, but  
Register  
Setting  
Frequency  
Divider  
Minimum  
fOUT  
Maximum  
fOUT  
those over-written settings will be lost on power-down. Please  
contact IDT if a specific set of power-up default settings is desired.  
Nn[10:0]  
N
(MHz)  
997.5  
997.5  
665  
(MHz)  
1300  
1300  
866.7  
650  
0000000000x  
00000000010  
00000000011  
00000000100  
00000000101  
0000000011x  
0000000100x  
0000000101x  
0000000110x  
0000000111x  
0000001000x  
0000001001x  
...  
2
Configuration Selection  
2
3
The IDT8T49N203I comes with two factory-programmed default  
configurations. When the device comes out of power-up reset the  
selected configuration is loaded into operating registers. The  
IDT8T49N203I uses the state of the CONFIG pin or CONFIG register  
bit (controlled by the CFG_PIN_REG bit) to determine which  
configuration is active. When the output frequency is changed either  
via the CONFIG pin or via internal registers, the output behavior may  
not be predictable during the register writing and output settling  
periods. Devices sensitive to glitches or runt pulses may have to be  
reset once reconfiguration is complete.  
4
498.75  
399  
5
520  
6
332.5  
249.4  
199.5  
166.3  
142.5  
124.7  
110.8  
1995 / N  
0.98  
433.3  
325  
8
10  
12  
14  
16  
18  
Even N  
2046  
260  
216.7  
185.7  
162.5  
144.4  
2600 / N  
1.27  
Once the device is out of reset, the contents of the operating registers  
2
can be modified by write access from the I C serial port. Users that  
2
have a custom configuration programmed may not require I C  
access.  
It is expected that the IDT8T49N203I will be used almost exclusively  
in a mode where the selected configuration will be used from device  
power-up without any changes during operation. For example, the  
device may be designed into a communications line card that  
supports different I/O modules such as a standard OC-12 module  
running at 622.08MHz or a (255/237) FEC rate OC-12 module  
running at 669.32MHz. The different I/O modules would result in a  
different level on the CONFIG pin which would select different divider  
1111111111x  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
5
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
The input reference frequency range is now extended up to 710MHz.  
A pre-divider stage P is needed to keep the operating frequencies at  
the phase detector within limits.  
Frequency Synthesizer Mode  
This mode of operation allows an arbitrary output frequency to be  
generated from a fundamental mode crystal input. For improved  
phase noise performance, the crystal input frequency may be  
doubled. As can be seen from the block diagram in Figure 1, only the  
upper feedback loop is used in this mode of operation. It is  
recommended that CLK0 and CLK1 be left unused in this mode of  
operation.  
Low-Bandwidth Frequency Translator Mode  
As can be seen from the block diagram in Figure 3, this mode  
involves two PLL loops. The lower loop with the large integer dividers  
is the low bandwidth loop and it sets the output-to-input frequency  
translation ratio.This loop drives the upper DCXO loop (digitally  
controlled crystal oscillator) via an analog-digital converter.  
The upper feedback loop supports a delta-sigma fractional feedback  
divider. This allows the VCO operating frequency to be a non-integer  
multiple of the crystal frequency. By using an integer multiple only,  
lower phase noise jitter on the output can be achieved, however the  
use of the delta-sigma divider logic will provide excellent  
performance on the output if a fractional divisor is used.  
Figure 3. Low Bandwidth Frequency Translator Mode  
Block Diagram  
The pre-divider stage is used to scale down the input frequency by  
an integer value to achieve a frequency in this range. By dividing  
down the fed-back VCO operating frequency by the integer divider  
M1[16:0] to as close as possible to the same frequency, exact output  
frequency translations can be achieved. The phase detector of the  
lower loop is designed to work with frequencies in the 8kHz - 16kHz  
range. For improved phase noise performance, the crystal input  
frequency may be doubled.  
Figure 1. Frequency Synthesizer Mode Block Diagram  
High-Bandwidth Frequency Translator Mode  
This mode of operation is used to translate one of two input clocks of  
the same nominal frequency into an output frequency with little jitter  
attenuation. As can be seen from the block diagram in Figure 2,  
similarly to the Frequency Synthesizer mode, only the upper  
feedback loop is used.  
Alarm Conditions & Status Bits  
The IDT8T49N203I monitors a number of conditions and reports their  
status via both output pins and register bits. All alarms will behave as  
indicated below in all modes of operation, but some of the conditions  
monitored have no valid meaning in some operating modes. For  
example, the status of CLK0BAD, CLK1BAD and CLK_ACTIVE are  
not relevant in Frequency Synthesizer mode. The outputs will still be  
active and it is left to the user to determine which to monitor and how  
to respond to them based on the known operating mode.  
PLL_BYPASS  
Output Divider  
1
Q0  
÷N[10:0]  
FemtoClock® NG  
VCO  
1995 - 2600 MHz  
nQ0  
OE0  
PD/LF  
0
Feedback Divider  
Q1  
÷M_INT  
÷M_FRAC  
[17:0]  
[7:0]  
nQ1  
OE1  
CLK_ACTIVE - indicates which input clock reference is being used to  
derive the output frequency.  
CLK_SEL  
CLK0  
nCLK0  
CLK1  
nCLK1  
0
1
÷P[16:0]  
LOCK_IND - This status is asserted on the pin & register bit when the  
PLL is locked to the appropriate input reference for the chosen mode  
of operation. The status bit will not assert until frequency lock has  
been achieved, but will de-assert once lock is lost.  
Status Indicators  
POR  
Control Logic  
Global Registers  
Register Set 0  
Register Set 1  
CLK_ACTIVE  
LOCK_IND  
0
1
CLK0BAD  
CLK1BAD  
HOLDOVER  
CONFIG  
SCLK, S_A0, S_A1  
SDATA  
Figure 2. High Bandwidth Frequency Translator Mode  
Block Diagram  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
6
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
XTALBAD - indicates if valid edges are being received on the crystal  
input. Detection is performed by comparing the input to the feedback  
signal at the upper loop’s Phase / Frequency Detector (PFD). If three  
edges are received on the feedback without an edge on the crystal  
input, the XTALBAD alarm is asserted on the pin & register bit. Once  
an edge is detected on the crystal input, the alarm is immediately  
deasserted.  
mode) state. In either case, the HOLDOVER alarm will be raised.  
This will occur even if there is a valid clock on the non-selected  
reference input. The device will recover from holdover / free-run state  
once a valid clock is re-established on the selected reference input.  
The IDT8T49N203I will only switch input references on command  
from the user. The user must either change the CLK_SEL register bit  
(if in Manual via Register) or CLK_SEL input pin (if in Manual via Pin).  
CLK0BAD - indicates if valid edges are being received on the CLK0  
reference input. Detection is performed by comparing the input to the  
feedback signal at the appropriate Phase / Frequency Detector  
(PFD). When operating in high-bandwidth mode, the feedback at the  
upper PFD is used. In low-bandwidth mode, the feedback at the lower  
PFD is used. If three edges are received on the feedback without an  
edge on the divided down (÷P) CLK0 reference input, the CLK0BAD  
alarm is asserted on the pin & register bit. Once an edge is detected  
on the CLK0 reference input, the alarm is deasserted.  
Automatic Switching Mode  
When the AUTO_MAN[1:0] field is set to either of the automatic  
selection modes (Revertive or Non-Revertive), the IDT8T49N203I  
determines which input reference it prefers / starts from by the state  
of the CLK_SEL register bit only. The CLK_SEL input pin is not used  
in either Automatic switching mode.  
When starting from an unlocked condition, the device will lock to the  
input reference indicated by the CLK_SEL register bit. It will not pay  
attention to the non-selected input reference until a locked state has  
been achieved. This is necessary to prevent ‘hunting’ behavior during  
the locking phase.  
CLK1BAD - indicates if valid edges are being received on the CLK1  
reference input. Behavior is as indicated for the CLK0BAD alarm, but  
with the CLK1 input being monitored and the CLK1BAD output pin &  
register bits being affected.  
Once the IDT8T49N203I has achieved a stable lock, it will remain  
locked to the preferred input reference as long as there is a valid clock  
on it. If at some point, that clock fails, then the device will  
automatically switch to the other input reference as long as there is a  
valid clock there. If there is not a valid clock on either input reference,  
the IDT8T49N203I will go into holdover (Low Bandwidth Frequency  
Translator mode) or free-run (High Bandwidth Frequency Translator  
mode) state. In either case, the HOLDOVER alarm will be raised.  
HOLDOVER - indicates that the device is not locked to a valid input  
reference clock. This can occur in Manual switchover mode if the  
selected reference input has gone bad, even if the other reference  
input is still good. In automatic mode, this will only assert if both input  
references are bad.  
Input Reference Selection and Switching  
When operating in Frequency Synthesizer mode, the CLK0 and  
CLK1 inputs are not used and the contents of this section do not  
apply. Except as noted below, when operating in either High or Low  
Bandwidth Frequency Translator mode, the contents of this section  
apply equally when in either of those modes.  
The device will recover from holdover / free-run state once a valid  
clock is re-established on either reference input. If clocks are valid on  
both input references, the device will choose the reference indicated  
by the CLK_SEL register bit.  
If running from the non-preferred input reference and a valid clock  
returns, there is a difference in behavior between Revertive and  
Non-revertive modes. In Revertive mode, the device will switch back  
to the reference indicated by the CLK_SEL register bit even if there  
is still a valid clock on the non-preferred reference input. In  
Both input references CLK0 and CLK1 must be the same nominal  
frequency. These may be driven by any type of clock source,  
including crystal oscillator modules. A difference in frequency may  
cause the PLL to lose lock when switching between input references.  
Please contact IDT for the exact limits for your situation.  
Non-revertive mode, the IDT8T49N203I will not switch back as long  
as the non-preferred input reference still has a valid clock on it.  
The global control bits AUTO_MAN[1:0] dictate the order of priority  
and switching mode to be used between the CLK0 and CLK1 inputs.  
Switchover Behavior of the PLL  
Even though the two input references have the same nominal  
frequency, there may be minor differences in frequency and  
potentially large differences in phase between them. The  
IDT8T49N203I will adjust its output to the new input reference. It will  
use Phase Slope Limiting to adjust the output phase at a fixed  
maximum rate until the output phase and frequency are now aligned  
to the new input reference. Phase will always be adjusted by  
extending the clock period of the output so that no unacceptably short  
clock periods are generated on the output IDT8T49N203I.  
Manual Switching Mode  
When the AUTO_MAN[1:0] field is set to Manual via Pin, then the  
IDT8T49N203I will use the CLK_SEL input pin to determine which  
input to use as a reference. Similarly, if set to Manual via Register,  
then the device will use the CLK_SEL register bit to determine the  
input reference. In either case, the PLL will lock to the selected  
reference if there is a valid clock present on that input.  
If there is not a valid clock present on the selected input, the  
IDT8T49N203I will go into holdover (Low Bandwidth Frequency  
Translator mode) or free-run (High Bandwidth Frequency Translator  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
7
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
The two outputs are individually selectable as LVDS or LVPECL  
output types via the Q0_TYPE and Q1_TYPE register bits. These  
two selection bits are provided in each configuration to allow different  
output type settings under each configuration.  
Holdover / Free-run Behavior  
When both input references have failed (Automatic mode) or the  
selected input has failed (Manual mode), the IDT8T49N203I will  
enter holdover (Low Bandwidth Frequency Translator mode) or  
free-run (High Bandwidth Frequency Translator mode) state . In both  
cases, once the input reference is lost, the PLL will stop making  
adjustments to the output phase.  
The two outputs can be enabled individually also via both register  
control bits and input pins. When both the OEn register bit and OEn  
pin are enabled, then the appropriate output is enabled. The OEn  
register bits default to enabled so that by default the outputs can be  
directly controlled by the input pins. Similarly, the input pins are  
provisioned with weak pull-ups so that if they are left unconnected,  
the output state can be directly controlled by the register bits. When  
the differential output is in the disabled state, it will show a high  
impedance condition.  
If operating in Low Bandwidth Frequency Translation mode, the PLL  
will continue to reference itself to the local oscillator and will hold its  
output phase and frequency in relation to that source. Output stability  
is determined by the stability of the local oscillator in this case.  
However, if operating in High Bandwidth Frequency Translation  
mode, the PLL no longer has any frequency reference to use and  
output stability is now determined by the stability of the internal VCO.  
Serial Interface Configuration Description  
If the device is programmed to perform Manual switching, once the  
selected input reference recovers, the IDT8T49N203I will switch back  
to that input reference. If programmed for either Automatic mode, the  
device will switch back to whichever input reference has a valid clock  
first.  
2
The IDT8T49N203I has an I C-compatible configuration interface to  
access any of the internal registers (Table 4D) for frequency and PLL  
parameter programming. The IDT8T49N203I acts as a slave device  
2
on the I C bus and has the address 0b11011xx, where xx is set by the  
values on the S_A0 & S_A1 pins (see Table 4A for details). The  
interface accepts byte-oriented block write and block read  
operations. An address byte (P) specifies the register address (Table  
4D) as the byte position of the first register to write or read. Data  
bytes (registers) are accessed in sequential order from the lowest to  
the highest byte (most significant bit first, see table 4B, 4C). Read  
and write block transfers can be stopped after any complete byte  
The switchover that results from returning from holdover or free-run  
is handled in the same way as a switch between two valid input  
references as described in the previous section.  
Output Configuration  
The two outputs of the IDT8T49N203I both provide the same clock  
frequency. Both must operate from the same output voltage level of  
3.3V or 2.5V, although this output voltage may be less than or equal  
to the core voltage (3.3V or 2.5V) the rest of the device is operating  
from. The output voltage level used on the two outputs is supplied on  
the VCCO pin.  
2
transfer. It is recommended to terminate I C the read or write transfer  
after accessing byte #23.  
2
For full electrical I C compliance, it is recommended to use external  
pull-up resistors for SDATA and SCLK. The internal pull-up resistors  
have a size of 50kΩ typical.  
Note: if a different device slave address is desired, please contact  
IDT.  
2
Table 4A. I C Device Slave Address  
1
1
0
1
1
S_A1  
S_A0  
R/W  
Table 4B. Block Write Operation  
Bit  
1
2:8  
9
10  
11:18  
19  
20:27  
28  
29-36  
37  
...  
...  
...  
Slave  
Address  
Address  
Byte (P)  
Data Byte  
(P)  
Data Byte  
(P+1)  
Data Byte  
...  
Description  
Length (bits)  
START  
1
W (0)  
1
ACK  
1
ACK  
1
ACK  
1
ACK  
1
ACK  
1
STOP  
1
7
8
8
8
8
Table 4C. Block Read Operation  
Bit  
1
2:8  
9
10  
11:18  
19  
20  
21:27  
28  
29  
30:37  
38  
39-46  
47  
...  
...  
...  
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Description  
Length (bits)  
Slave  
Address  
W
(0)  
Address  
Byte (P)  
Repeate  
d START Address  
Slave  
R
(1)  
Data  
Byte (P)  
DataByte  
(P+1)  
Data Byte  
...  
START  
1
STOP  
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
8
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Register Descriptions  
Please consult IDT for configuration software and/or programming guides to assist in selection of optimal register settings for the desired  
configurations.  
2
Table 4D. I C Register Map  
Binary  
Register  
Reg Address  
Register Bit  
D4  
D7  
MFRAC0[17]  
MFRAC1[17]  
MFRAC0[9]  
MFRAC1[9]  
MFRAC0[1]  
MFRAC1[1]  
MINT0[1]  
MINT1[1]  
P0[10]  
D6  
MFRAC0[16]  
MFRAC1[16]  
MFRAC0[8]  
MFRAC1[8]  
MFRAC0[0]  
MFRAC1[0]  
MINT0[0]  
MINT1[0]  
P0[9]  
D5  
MFRAC0[15]  
MFRAC1[15]  
MFRAC0[7]  
MFRAC1[7]  
MINT0[7]  
MINT1[7]  
P0[16]  
D3  
MFRAC0[13]  
MFRAC1[13]  
MFRAC0[5]  
MFRAC1[5]  
MINT0[5]  
MINT1[5]  
P0[14]  
D2  
MFRAC0[12]  
MFRAC1[12]  
MFRAC0[4]  
MFRAC1[4]  
MINT0[4]  
MINT1[4]  
P0[13]  
D1  
MFRAC0[11]  
MFRAC1[11]  
MFRAC0[3]  
MFRAC1[3]  
MINT0[3]  
MINT1[3]  
P0[12]  
D0  
MFRAC0[10]  
MFRAC1[10]  
MFRAC0[2]  
MFRAC1[2]  
MINT0[2]  
MINT1[2]  
P0[11]  
00000  
00001  
00010  
00011  
00100  
00101  
00110  
00111  
01000  
01001  
01010  
01011  
01100  
01101  
01110  
01111  
10000  
10001  
10010  
10011  
10100  
10101  
10110  
10111  
MFRAC0[14]  
0
1
MFRAC1[14]  
MFRAC0[6]  
MFRAC1[6]  
MINT0[6]  
MINT1[6]  
P0[15]  
2
3
4
5
6
P1[16]  
P1[15]  
P1[14]  
P1[13]  
P1[12]  
P1[11]  
7
P0[8]  
P0[7]  
P0[6]  
P0[5]  
P0[4]  
P0[3]  
8
P1[10]  
P1[9]  
P1[8]  
P1[7]  
P1[6]  
P1[5]  
P1[4]  
P1[3]  
9
P0[2]  
P0[1]  
P0[0]  
M1_0[16]  
M1_1[16]  
M1_0[8]  
M1_1[8]  
M1_0[0]  
M1_1[0]  
N0[3]  
M1_0[15]  
M1_1[15]  
M1_0[7]  
M1_1[7]  
N0[10]  
M1_0[14]  
M1_1[14]  
M1_0[6]  
M1_1[6]  
N0[9]  
M1_0[13]  
M1_1[13]  
M1_0[5]  
M1_1[5]  
N0[8]  
M1_0[12]  
M1_1[12]  
M1_0[4]  
M1_1[4]  
N0[7]  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
P1[2]  
P1[1]  
P1[0]  
M1_0[11]  
M1_1[11]  
M1_0[3]  
M1_1[3]  
N0[6]  
M1_0[10]  
M1_1[10]  
M1_0[2]  
M1_1[2]  
N0[5]  
M1_0[9]  
M1_1[9]  
M1_0[1]  
M1_1[1]  
N0[4]  
N1[10]  
N1[9]  
N1[8]  
N1[7]  
N0[2]  
N0[1]  
N0[0]  
BW0[6]  
N1[6]  
N1[5]  
N1[4]  
N1[3]  
N1[2]  
N1[1]  
N1[0]  
BW1[6]  
BW0[5]  
BW0[4]  
BW0[3]  
BW1[3]  
BW0[2]  
BW0[1]  
BW0[0]  
Q1_TYPE0  
Q1_TYPE1  
Q0_TYPE0  
Q0_TYPE1  
BW1[5]  
BW1[4]  
BW1[2]  
BW1[1]  
BW1[0]  
MODE_SEL[1]  
CLK_SEL  
1
MODE_SEL[0]  
AUTO_MAN[1]  
0
CONFIG  
AUTO_MAN[0]  
1
CFG_PIN_REG  
OE1  
OE0  
ADC_RATE[0]  
0
Rsvd  
LCK_WIN[1]  
0
Rsvd  
LCK_WIN[0]  
0
0
0
ADC_RATE[1]  
DBL_XTAL  
XTAL_BAD  
CLK_ACTIVE  
HOLDOVER  
CLK1BAD  
CLK0BAD  
LOCK_IND  
Rsvd  
Rsvd  
Register Bit Color Key  
Configuration 0 Specific Bits  
Configuration 1 Specific Bits  
Global Control & Status Bits  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
9
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
The register bits described in Table 4E are duplicated, with one set  
applying for Configuration 0 and the other for Configuration 1. The  
functions of the bits are identical, but only apply when the  
configuration they apply to is enabled. Replace the lowercase n in the  
bit field description with 0 or 1 to find the field’s location in the bitmap  
in Table 4D.  
Table 4E. Configuration-Specific Control Bits  
Register Bits  
Function  
Determines the output type for output pair Q0, nQ0 for Configuration n.  
Q0_TYPEn  
0 = LVPECL  
1 = LVDS  
Determines the output type for output pair Q1, nQ1 for Configuration n.  
Q1_TYPEn  
0 = LVPECL  
1 = LVDS  
Pn[16:0]  
M1_n[16:0]  
M_INTn[7:0]  
M_FRACn[17:0]  
Nn[10:0]  
Reference Pre-Divider for Configuration n.  
Integer Feedback Divider in Lower Feedback Loop for Configuration n.  
Feedback Divider, Integer Value in Upper Feedback Loop for Configuration n.  
Feedback Divider, Fractional Value in Upper Feedback Loop for Configuration n.  
Output Divider for Configuration n.  
Internal Operation Settings for Configuration n.  
Please use IDT IDT8T49N203I Configuration Software to determine the correct settings for these bits for the  
specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these  
bits.The function of these bits are explained in Tables 4J and 4K.  
BWn[6:0]  
Table 4F. Global Control Bits  
Register Bits  
Function  
PLL Mode Select  
00 = Low Bandwidth Frequency Translator  
01 = Frequency Synthesizer  
MODE_SEL[1:0]  
10 = High Bandwidth Frequency Translator  
11 = High Bandwidth Frequency Translator  
Configuration Control. Selects whether the configuration selection function is under pin or register control.  
CFG_PIN_REG  
CONFIG  
0 = Pin Control  
1 = Register Control  
Configuration Selection. Selects whether the device uses the register configuration set 0 or 1. This bit only has an  
effect when the CONFIG_PIN_REG bit is set to 1 to enable register control.  
Output Enable Control for Output 0. Both this register bit and the corresponding Output Enable pin OE0 must be  
asserted to enable the Q0, nQ0 output.  
0 = Output Q0, nQ0 disabled  
OE0  
1 = Output Q0, nQ0 under control of the OE0 pin  
Output Enable Control for Output 1. Both this register bit and the corresponding Output Enable pin OE1 must be  
asserted to enable the Q1, nQ1 output.  
0 = Output Q1, nQ1 disabled  
OE1  
1 = Output Q1, nQ1 under control of the OE1 pin  
Rsvd  
Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed  
Selects how input clock selection is performed.  
00 = Manual Selection via pin only  
01 = Automatic, non-revertive  
10 = Automatic, revertive  
11 = Manual Selection via register only  
AUTO_MAN[1:0]  
CLK_SEL  
In manual clock selection via register mode, this bit will command which input clock is selected. In the automatic  
modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.  
0 = CLK0  
1 = CLK1  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
10  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the crystal input frequency.  
00 = Crystal Frequency / 16  
ADC_RATE[1:0]  
01 = Crystal Frequency / 8  
10 = Crystal Frequency / 4 (recommended)  
11 = Crystal Frequency / 2  
Sets the width of the window in which a new reference edge must fall relative to the feedback edge: 00 = 2usec  
(recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec  
LCK_WIN[1:0]  
DBL_XTAL  
When set, this bit will double the frequency of the crystal input before applying it to the Phase_Frequency Detector.  
Table 4G. Global Status Bits  
Register Bits  
Function  
Status Bit for input clock 0. This function is mirrored in the CLK0BAD pin.  
0 = input CLK0 is good  
CLK0BAD  
1 = input CLK0 is bad. Self clears when input clock returns to good status  
Status Bit for input clock 1. This function is mirrored in the CLK1BAD pin.  
0 = input CLK1 is good  
1 = input CLK1 is bad. Self clears when input clock returns to good status  
CLK1BAD  
XTALBAD  
LOCK_IND  
Status Bit. This function is mirrored on the XTALBAD pin.  
0 = crystal input good  
1 = crystal input bad. Self-clears when the XTAL clock returns to good status  
Status bit. This function is mirrored on the LOCK_IND pin.  
0 = PLL unlocked  
1 = PLL locked  
Status Bit. This function is mirrored on the HOLDOVER pin.  
HOLDOVER  
CLK_ACTIVE  
0 = Input to phase detector is within specifications and device is tracking to it  
1 = Phase detector input is not within specifications and DCXO is frozen at last value  
Status Bit. Indicates which input clock is active. Automatically updates during fail-over switching. Status also  
indicated on CLK_ACTIVE pin.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
11  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Table 4J. BW[6:0] Bits  
Mode  
BW[6]  
BW[5]  
BW[4]  
BW[3]  
BW[2]  
BW[1]  
BW[0]  
Synthesizer Mode  
High-Bandwidth Mode  
Low-Bandwidth Mode  
PLL2_LF[1]  
PLL2_LF[1]  
PLL2_LF[0]  
PLL2_LF[0]  
DSM_ORD  
DSM_ORD  
DSM_EN  
DSM_EN  
PLL2_CP[1] PLL2_CP[0] PLL2_LOW_ICP  
PLL2_CP[1] PLL2_CP[0] PLL2_LOW_ICP  
ADC_GAIN[3] ADC_GAIN[2] ADC_GAIN[1] ADC_GAIN[0] PLL1_CP[1] PLL1_CP[0] PLL2_LOW_ICP  
Table 4K. Functions of Fields in BW[6:0]  
Register Bits  
PLL2_LF[1:0]  
DSM_ORD  
Function  
Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes.  
Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4L for settings.  
Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation  
Enables Delta-Sigma Modulator  
DSM_EN  
0 = Disabled - feedback in integer mode only  
1 = Enabled - feedback in fractional mode  
Upper loop PLL charge pump current settings:  
00 = 173µA (defaults to this setting in Low Bandwidth Mode)  
PLL2_CP[1:0]  
01 = 346µA  
10 = 692µA  
11 = reserved  
Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register  
settings or high VCO operating frequency (>2.4GHz).  
PLL2_LOW_ICP  
ADC_GAIN[3:0]  
Gain setting for ADC in Low Bandwidth Mode.  
Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode):  
00 = 800µA  
01 = 400µA  
10 = 200µA  
11 = 100µA  
PLL1_CP[1:0]  
Table 4L. High Bandwidth Frequency and Frequency Synthesizer Bandwidth Settings  
Desired Bandwidth  
PLL2_CP  
PLL2_LOW_ICP  
PLL2_LF  
Frequency Synthesizer Mode  
200kHz  
400kHz  
800kHz  
2MHz  
00  
01  
10  
10  
1
1
1
1
00  
01  
10  
11  
High Bandwidth Frequency Translator Mode  
200kHz  
400kHz  
800kHz  
4MHz  
00  
01  
10  
10  
1
1
1
0
00  
01  
10  
11  
NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
12  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  
extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VCC  
3.63V  
Inputs, VI  
XTAL_IN  
0V to 2V  
Other Inputs  
-0.5V to VCC + 0.5V  
Outputs, VO (LVCMOS)  
-0.5V to VCCO + 0.5V  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
10mA  
15mA  
Package Thermal Impedance, θJA  
32.4°C/W (0 mps)  
-65°C to 150°C  
Storage Temperature, TSTG  
DC Electrical Characteristics  
Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCCO = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
VCC  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
VCCA  
VCCO  
IEE  
VCC – 0.30  
3.135  
3.3  
V
3.3  
3.465  
332  
V
mA  
mA  
ICCA  
30  
Table 5B. LVPECL Power Supply DC Characteristics, VCC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
VCC  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
VCCA  
VCCO  
IEE  
VCC – 0.30  
2.375  
3.3  
V
2.5  
2.625  
332  
V
mA  
mA  
ICCA  
30  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
13  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Table 5C. LVPECL Power Supply DC Characteristics, VCC = VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
2.375  
Typical  
2.5  
Maximum  
2.625  
VCC  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
VCCA  
VCCO  
IEE  
VCC – 0.26  
2.375  
2.5  
V
2.5  
2.625  
319  
V
mA  
mA  
ICCA  
26  
Table 5D. LVDS Power Supply DC Characteristics, VCC = VCCO = 3.3V 5ꢀ, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum  
3.465  
VCC  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
VCCA  
VCCO  
ICC  
VCC – 0.30  
3.135  
3.3  
V
3.3  
3.465  
284  
V
mA  
mA  
mA  
ICCA  
30  
ICCO  
40  
Table 5E. LVDS Power Supply DC Characteristics, VCC = VCCO = 2.5V 5ꢀ, TA = -40°C to 85°C  
Symbol  
VCC  
Parameter  
Test Conditions  
Minimum  
2.375  
Typical  
2.5  
Maximum  
2.625  
VCC  
Units  
V
Core Supply Voltage  
Analog Supply Voltage  
Output Supply Voltage  
Power Supply Current  
Analog Supply Current  
Output Supply Current  
VCCA  
VCCO  
ICC  
VCC – 0.26  
2.375  
2.5  
V
2.5  
2.625  
275  
V
mA  
mA  
mA  
ICCA  
26  
ICCO  
40  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
14  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Table 5F. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
CC = 3.3V  
VCC = 2.5V  
Minimum  
Typical  
Maximum  
VCC + 0.3  
VCC + 0.3  
0.8  
Units  
V
2
V
V
V
V
VIH  
VIL  
Input High Voltage  
1.7  
-0.3  
-0.3  
V
CC = 3.3V  
CC = 2.5V  
Input Low Voltage  
CLK_SEL, CONFIG,  
V
0.7  
V
CC = VIN = 3.465V or 2.625V  
150  
5
µA  
µA  
µA  
PLL_BYPASS, S_A[0:1]  
Input  
High Current  
IIH  
OE0, OE1,  
SCLK, SDATA  
VCC = VIN = 3.465V or 2.625V  
CLK_SEL, CONFIG,  
PLL_BYPASS, S_A[0:1]  
VCC = 3.465V or 2.625V,  
VIN = 0V  
-5  
Input  
Low Current  
IIL  
OE0, OE1,  
SCLK, SDATA  
VCC = 3.465V or 2.625V,  
VIN = 0V  
-150  
2.6  
µA  
V
HOLDOVER, SDATA  
CLK_ACTIVE,  
LOCK_IND, XTALBAD,  
CLK0BAD, CLK1BAD  
VCC = 3.3V 5ꢀ, IOH = -8mA  
Output  
High Voltage  
VOH  
V
CC = 2.5V 5ꢀ, IOH = -8mA  
1.8  
V
HOLDOVER, SDATA  
CLK_ACTIVE,  
LOCK_IND, XTALBAD,  
CLK0BAD, CLK1BAD  
Output  
Low Voltage  
VCC = 3.3V 5ꢀ or  
2.5V 5ꢀ, IOL = 8mA  
VOL  
0.5  
V
Table 5G. Differential DC Characteristics, VCC = VCCO = 3.3V 5ꢀ or 2.5V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
Parameter  
Input  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CLK0, nCLK0,  
CLK1, nCLK1  
CLK0, CLK1  
IIH  
VCC = VIN = 3.465V or 2.625V  
150  
µA  
High Current  
VCC = 3.465V or 2.625V, VIN = 0V  
VCC = 3.465V or 2.625V, VIN = 0V  
-5  
µA  
µA  
V
Input  
IIL  
Low Current  
nCLK0, nCLK1  
-150  
0.15  
VPP  
VCMR  
Peak-to-Peak Voltage; Note 1  
Common Mode Input Voltage;  
NOTE 1, 2  
1.3  
VEE + 0.5  
VCC - 1.0  
V
NOTE 1: VIL should not be less than -0.3v.  
NOTE 2: Common mode input voltage is defined as the crosspoint.  
Table 5H. LVPECL DC Characteristics, VCC = VCCO = 3.3V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCCO – 1.1  
VCCO – 2.0  
0.6  
Typical  
Maximum  
VCCO – 0.7  
VCCO – 1.5  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
15  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Table 5I. LVPECL DC Characteristics, VCC = 3.3V 5ꢀ or 2.5V 5ꢀ, VCCO = 2.5V 5ꢀ, VEE = 0V, TA = -40°C to 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
VCCO – 1.1  
VCCO – 2.0  
0.6  
Typical  
Maximum  
VCCO – 0.8  
VCCO – 1.5  
1.0  
Units  
Output High Voltage; NOTE 1  
Output Low Voltage NOTE 1  
Peak-to-Peak Output Voltage Swing  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.  
Table 5J. LVDS DC Characteristics, VCC = VCCO = 3.3V 5ꢀ, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
∆VOD  
VOS  
50  
1.125  
1.375  
50  
∆VOS  
VOS Magnitude Change  
mV  
Table 5K. LVDS DC Characteristics, VCC = VCCO = 2.5V 5ꢀ, TA = -40°C to 85°C  
Symbol  
VOD  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
454  
Units  
mV  
mV  
V
Differential Output Voltage  
VOD Magnitude Change  
Offset Voltage  
247  
∆VOD  
VOS  
50  
1.125  
1.375  
50  
∆VOS  
VOS Magnitude Change  
mV  
Table 6. Input Frequency Characteristics, VCC = VCCO = 3.3V 5ꢀ, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
XTAL_IN, XTAL_OUT  
NOTE 1  
16  
40  
MHz  
Input  
Frequency  
High Bandwidth Mode  
Low Bandwidth Mode  
16  
710  
710  
5
MHz  
MHz  
MHz  
fIN  
CLK0, nCLK0,  
CLK1, nCLK1  
0.008  
SCLK  
NOTE 1: For the input crystal and CLKx, nCLKx frequency range, the M value must be set for the VCO to operate within the 1995MHz to  
2600MHz range.  
Table 7. Crystal Characteristics  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Mode of Oscillation  
Frequency  
Fundamental  
16  
40  
100  
7
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
Load Capacitance (CL)  
pF  
12  
pF  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
16  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
AC Electrical Characteristics  
Table 8. AC Characteristics, VCC = VCCO = 3.3V 5ꢀ or 2.5V 5ꢀ, or  
V
CC = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ (LVPECL Only), VEE = 0V, TA = -40°C to 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
fOUT  
Output Frequency  
0.98  
1300  
MHz  
Synth Mode (Integer FB),  
fOUT = 400MHz, 40MHz XTAL,  
Integration Range: 12kHz – 40MHz  
285  
363  
313  
446  
521  
490  
fs  
fs  
fs  
Synth Mode (FracN FB),  
fOUT = 698.81MHz, 40MHz XTAL,  
Integration Range: 12kHz – 20MHz  
HBW Mode, (NOTE 1)  
fIN = 133.33MHz, fOUT = 400MHz,  
RMS Phase Jitter;  
Integer Divide Ratio  
tjit(Ø)  
Integration Range: 12kHz – 20MHz  
LBW Mode (FracN), 40MHz XTAL,  
f
IN = 19.44MHz, fOUT = 155.52MHz,  
Integration Range: 12kHz – 20MHz  
(LVDS Output)  
439  
450  
670  
670  
fs  
fs  
LBW Mode (FracN), 40MHz XTAL,  
fIN = 25MHz, fOUT = 161.1328125MHz,  
Integration Range: 12kHz – 20MHz  
(LVDS Output)  
LVPECL Outputs  
LVDS Output  
2.2  
5.1  
5.3  
8.7  
30  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ꢀ
tjit(per)  
RMS Period Jitter NOTE 5  
Frequency Synthesizer Mode  
Frequency Translator Mode  
tjit(cc)  
tsk(o)  
tR / tF  
Cycle-to-Cycle Jitter; NOTE 2  
Output Skew; NOTE 2, 3  
40  
42  
LVPECL Outputs  
LVDS Outputs  
20ꢀ to 80ꢀ  
20ꢀ to 80ꢀ  
100  
80  
520  
520  
55  
Output  
Rise/Fall Time  
fOUT < 600MHz  
45  
odc  
Output Duty Cycle  
f
OUT ≥ 600MHz  
40  
60  
ꢀ
from falling edge of the 8th SCLK for a  
register change  
200  
10  
ns  
ns  
Output Re-configuration Settling  
Time  
tSET  
from edge on CONFIG pin  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE 1: Measured using a Rohde & Schwarz SMA100 Signal Generator, 9kHz to 6GHz as the input source.  
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.  
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential  
cross points.  
NOTE 4: RMS Phase Jitter are measured with DBL_XTAL bit set to 1 and crystal CL = 12pf.  
NOTE 5: This parameter is defined in accordance with Jedec Standard 65.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
17  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Typical Phase Noise at 400MHz (HBW Mode)  
400MHz  
RMS Phase Jitter  
12kHz to 40MHz = 258fs (typical)  
Offset Frequency (Hz)  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
18  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Parameter Measurement Information  
2V  
2V  
2V  
2V  
SCOPE  
SCOPE  
V
V
CC,  
V
CCO  
CC,  
Qx  
Qx  
V
CCO  
V
CCA  
V
CCA  
nQx  
nQx  
VEE  
VEE  
-1.3V+0.165V  
-0.5V 0.125V  
2.5 Core/2.5V LVPECL Output Load Test Circuit  
3.3 Core/3.3V LVPECL Output Load Test Circuit  
2.8V 0.04V  
2V  
2.8V 0.04V  
SCOPE  
V
CC  
SCOPE  
Qx  
V
V
Qx  
CC,  
V
3.3V 5ꢀ  
CCO  
POWER SUPPLY  
V
CCO  
V
CCA  
CCA  
+
Float GND –  
nQx  
nQx  
VEE  
-0.5V 0.125V  
3.3 Core/3.3V LVDS Output Load Test Circuit  
3.3 Core/2.5V LVPECL Output Load Test Circuit  
V
CC  
SCOPE  
V
Qx  
CC,  
nCLKx  
2.5V 5ꢀ  
POWER SUPPLY  
V
CCO  
V
CCA  
VPP  
Cross Points  
+
Float GND –  
CLKx  
nQx  
VCMR  
V
EE  
2.5 Core/2.5V LVDS Output Load Test Circuit  
Differential Input Levels  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
19  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Parameter Measurement Information, continued  
Phase Noise Plot  
nQx  
Qx  
nQy  
Qy  
Offset Frequency  
tsk(o)  
f1  
f2  
RMS Phase Jitter =  
1
*
Area Under Curve Defined by the Offset Frequency Markers  
2 * * ƒ  
RMS Phase Jitter  
Output Skew  
nQx  
Qx  
nQx  
tPW  
Qx  
tPERIOD  
➤
➤
tcycle n  
tcycle n+1  
➤
➤
tPW  
tjit(cc) = tcycle n – tcycle n+1  
|
|
odc =  
x 100ꢀ  
1000 Cycles  
tPERIOD  
Cycle-to-Cycle Jitter  
Differential Output Duty Cycle/Output Pulse Width/Period  
nQx  
nQx  
80ꢀ  
tF  
80ꢀ  
tF  
80ꢀ  
tR  
80ꢀ  
VSWING  
20ꢀ  
VOD  
20ꢀ  
20ꢀ  
20ꢀ  
Qx  
Qx  
tR  
LVDS Output Rise/Fall Time  
LVPECL Output Rise/Fall Time  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
20  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Parameter Measurement Information, continued  
Offset Voltage Setup  
VDD  
VOH  
out  
out  
VREF  
DC Input  
100  
LVDS  
VOL  
1σ contains 68.26ꢀ of all measurements  
2σ contains 95.4ꢀ of all measurements  
3σ contains 99.73ꢀ of all measurements  
4σ contains 99.99366ꢀ of all measurements  
6σ contains (100-1.973x10-7)ꢀ of all measurements  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
Differential Output Voltage Setup  
Period Jitter  
VDD  
out  
DC Input  
LVDS  
out  
VOS/∆ VOS  
ä
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
21  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Applications Information  
Recommendations for Unused Input and Output Pins  
Inputs:  
Outputs:  
Crystal Inputs  
LVPECL Outputs  
All unused LVPECL outputs can be left floating. We recommend that  
there is no trace attached. Both sides of the differential output pair  
should either be left floating or terminated.  
For applications not requiring the use of the crystal oscillator input,  
both XTAL_IN and XTAL_OUT can be left floating. Though not  
required, but for additional protection, a 1kΩ resistor can be tied from  
XTAL_IN to ground.  
LVDS Outputs  
All unused LVDS output pairs can be either left floating or terminated  
with 100Ω across. If they are left floating there should be no trace  
attached.  
CLKx/nCLKx Inputs  
For applications not requiring the use of either differential input, both  
CLKx and nCLKx can be left floating. Though not required, but for  
additional protection, a 1kΩ resistor can be tied from CLKx to ground.  
It is recommended that CLKx, nCLKx be left unconnected in  
frequency synthesizer mode.  
LVCMOS Outputs  
All unused LVCMOS output can be left floating. There should be no  
trace attached.  
LVCMOS Control Pins  
All control pins have internal pullups or pulldowns; additional  
resistance is not required but can be added for additional protection.  
A 1kΩ resistor can be used.  
Recommended Values for Low-Bandwidth Mode Loop Filter  
External loop filter components are not needed in Frequency  
Synthesizer or High-Bandwidth modes. In Low-Bandwidth mode, the  
loop filter structure and components shown in Figure 11 are  
recommended. Please consult IDT if other values are needed.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
22  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 4 shows how a differential input can be wired to accept single  
ended levels. The reference voltage VREF = VCC/2 is generated by  
the bias resistors R1 and R2. The bypass capacitor (C1) is used to  
help filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the VREF in the center of the input voltage  
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,  
R1 and R2 value should be adjusted to set VREF at 1.25V. The values  
below are for when both the single ended swing and VCC are at the  
same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of  
two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some  
of the recommended components might not be used, the pads  
should be placed in the layout. They can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a differential signal.  
Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
23  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Overdriving the XTAL Interface  
The XTAL_IN input can be overdriven by an LVCMOS driver or by one  
side of a differential driver through an AC coupling capacitor. The  
XTAL_OUT pin can be left floating. The amplitude of the input signal  
should be between 500mV and 1.8V and the slew rate should not be  
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be  
reduced from full swing to at least half the swing in order to prevent  
signal interference with the power rail and to reduce internal noise.  
Figure 5A shows an example of the interface diagram for a high  
speed 3.3V LVCMOS driver. This configuration requires that the sum  
of the output impedance of the driver (Ro) and the series resistance  
(Rs) equals the transmission line impedance. In addition, matched  
termination at the crystal input will attenuate the signal in half. This  
can be done in one of two ways. First, R1 and R2 in parallel should  
equal the transmission line impedance. For most 50Ω applications,  
R1 and R2 can be 100Ω. This can also be accomplished by removing  
R1 and changing R2 to 50Ω. The values of the resistors can be  
increased to reduce the loading for a slower and weaker LVCMOS  
driver. Figure 5B shows an example of the interface diagram for an  
LVPECL driver. This is a standard LVPECL termination with one side  
of the driver feeding the XTAL_IN input. It is recommended that all  
components in the schematics be placed in the layout. Though some  
components might not be used, they can be utilized for debugging  
purposes. The datasheet specifications are characterized and  
guaranteed by using a quartz crystal as the input.  
VCC  
XTAL_OUT  
R1  
100  
C1  
Rs  
Zo = 50 ohms  
Ro  
XTAL_IN  
.1uf  
R2  
100  
Zo = Ro + Rs  
LVCMOS Driver  
Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface  
XTAL_OUT  
C2  
Zo = 50 ohms  
XTAL_I N  
.1uf  
Zo = 50 ohms  
R1  
50  
R2  
50  
LVPECL Driver  
R3  
50  
Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
24  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Differential Clock Input Interface  
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other  
differential signals. Both VSWING and VOH must meet the VPP and  
VCMR input requirements. Figures 6A to 6E show interface examples  
for the CLK/nCLK input driven by the most common driver types. The  
input interfaces suggested here are examples only. Please consult  
with the vendor of the driver component to confirm the driver  
termination requirements. For example, in Figure 6A, the input  
termination applies for IDT open emitter LVHSTL drivers. If you are  
using an LVHSTL driver from another vendor, use their termination  
recommendation.  
3.3V  
3.3V  
3.3V  
1.8V  
Zo = 50Ω  
Zo = 50Ω  
CLK  
CLK  
Zo = 50Ω  
Zo = 50Ω  
nCLK  
Differential  
Input  
nCLK  
LVPECL  
Differential  
R1  
R2  
LVHSTL  
50Ω  
50Ω  
Input  
R1  
50Ω  
R2  
50Ω  
IDT  
LVHSTL Driver  
R2  
50Ω  
Figure 6A. CLK/nCLK Input  
Figure 6B. CLK/nCLK Input  
Driven by an IDT Open Emitter LVHSTL Driver  
Driven by a 3.3V LVPECL Driver  
3.3V  
3.3V  
3.3V  
3.3V  
R3  
R4  
3.3V  
125Ω  
125Ω  
Zo = 50Ω  
Zo = 50Ω  
Zo = 50Ω  
CLK  
CLK  
R1  
100Ω  
nCLK  
nCLK  
Zo = 50Ω  
Differential  
Input  
LVPECL  
Receiver  
LVDS  
R1  
R2  
84Ω  
84Ω  
Figure 6C. CLK/nCLK Input  
Figure 6D. CLK/nCLK Input  
Driven by a 3.3V LVDS Driver  
Driven by a 3.3V LVPECL Driver  
3.3V  
3.3V  
Zo = 50Ω  
*R3  
*R4  
33Ω  
33Ω  
CLK  
Zo = 50Ω  
nCLK  
Differential  
Input  
HCSL  
R1  
50Ω  
R2  
50Ω  
*Optional – R3 and R4 can be 0Ω  
Figure 6E. CLK/nCLK Input  
Driven by a 3.3V HCSL Driver  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
25  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90Ω and 132Ω. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100Ω parallel resistor at the receiver and a 100Ω differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in Figure 7A can be used  
with either type of output structure. Figure 7B, which can also be  
used with both output types, is an optional termination with center tap  
capacitance to help filter common mode noise. The capacitor value  
should be approximately 50pF. If using a non-standard termination, it  
is recommended to contact IDT and confirm if the output structure is  
current source or voltage source type. In addition, since these  
outputs are LVDS compatible, the input receiver’s amplitude and  
common-mode input range should be verified for compatibility with  
the output.  
ZO ≈ ZT  
LVDS  
Receiver  
LVDS  
Driver  
ZT  
Figure 7A. Standard Termination  
ZT  
ZO ≈ ZT  
LVDS  
Driver  
2
ZT  
2
LVDS  
Receiver  
C
Figure 7B. Optional Termination  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
26  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Termination for 3.3V LVPECL Outputs  
The clock layout topology shown below is a typical termination for  
LVPECL outputs. The two different layouts mentioned are  
recommended only as guidelines.  
transmission lines. Matched impedance techniques should be used  
to maximize operating frequency and minimize signal distortion.  
Figures 8A and 8B show two different layouts which are  
recommended only as guidelines. Other suitable clock layouts may  
exist and it would be recommended that the board designers  
simulate to guarantee compatibility across all printed circuit and clock  
component process variations.  
The differential outputs are low impedance follower outputs that  
generate ECL/LVPECL compatible outputs. Therefore, terminating  
resistors (DC current path to ground) or current sources must be  
used for functionality. These outputs are designed to drive 50Ω  
3.3V  
R3  
R4  
3.3V  
3.3V  
125Ω  
125Ω  
3.3V  
Z
Z
o = 50Ω  
o = 50Ω  
3.3V  
+
_
Z
o = 50Ω  
+
_
Input  
LVPECL  
LVPECL  
Input  
Z
o = 50Ω  
R1  
R2  
50Ω  
50Ω  
R1  
84Ω  
R2  
84Ω  
VCC - 2V  
1
RTT =  
* Zo  
RTT  
((VOH + VOL) / (VCC – 2)) – 2  
Figure 8A. 3.3V LVPECL Output Termination  
Figure 8B. 3.3V LVPECL Output Termination  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
27  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Termination for 2.5V LVPECL Outputs  
Figure 9A and Figure 9B show examples of termination for 2.5V  
LVPECL driver. These terminations are equivalent to terminating 50Ω  
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground  
level. The R3 in Figure 9B can be eliminated and the termination is  
shown in Figure 9C.  
2.5V  
VCCO = 2.5V  
2.5V  
2.5V  
VCCO = 2.5V  
R1  
R3  
50Ω  
250  
250  
+
50Ω  
50Ω  
+
–
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
2.5V LVPECL Driver  
R2  
62.5  
R4  
62.5  
R3  
18  
Figure 9A. 2.5V LVPECL Driver Termination Example  
Figure 9B. 2.5V LVPECL Driver Termination Example  
2.5V  
VCCO = 2.5V  
50Ω  
+
50Ω  
–
2.5V LVPECL Driver  
R1  
50  
R2  
50  
Figure 9C. 2.5V LVPECL Driver Termination Example  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
28  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 10. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Lead frame Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
Figure 10. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
29  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Schematic Layout  
Figure 11 (next page), shows an example of the UFT  
In order to achieve the best possible filtering, it is recommended that  
the placement of the filter components be on the device side of the  
PCB as close to the power pins as possible. If space is limited, the  
0.1uf capacitor in each power pin filter should be placed on the device  
side. The other components can be on the opposite side of the PCB.  
(IDT8T49N203I) application schematic. Input and output  
terminations shown are intended as examples only and may not  
represent the exact user configuration. In this example, the device is  
operated at VCC = 3.3V. For 2.5V option, please refer to the  
“Termination for 2.5V LVPECL Outputs” for output termination  
recommendation. The decoupling capacitors should be located as  
close as possible to the power pin. A 12pF parallel resonant 16MHz  
to 40MHz crystal is used in this example. Different crystal  
frequencies may be used. The C1 = C2 = 5pF are recommended for  
frequency accuracy. If different crystal types are used, please consult  
IDT for recommendations. For different board layout, the C1 and C2  
may be slightly adjusted for optimizing frequency accuracy. It is  
recommended that the loop filter components be laid out for the  
3-pole option. This will also allow either 2-pole or 3-pole filter to be  
used. The 3-pole filter can be used for additional spur reduction. If a  
2-pole filter construction is used, the LF0 and LF1 pins must be  
tied-together to the filter.  
Power supply filter recommendations are a general guideline to be  
used for reducing external noise from coupling into the devices. The  
filter performance is designed for a wide range of noise frequencies.  
This low-pass filter starts to attenuate noise at approximately 10 kHz.  
If a specific frequency noise component is known, such as switching  
power supplies frequencies, it is recommended that component  
values be adjusted and if required, additional filtering be added.  
Additionally, good general design practices for power plane voltage  
stability suggests adding bulk capacitance in the local area of all  
devices.  
The schematic example focuses on functional connections and is not  
configuration specific. Refer to the pin description and functional  
tables in the datasheet to ensure the logic control inputs are properly  
set  
As with any high speed analog circuitry, the power supply pins are  
vulnerable to random noise. To achieve optimum jitter performance,  
power supply isolation is required. The UFT (IDT8T49N203I)  
provides separate power supplies to isolate any high switching noise  
from coupling into the internal PLL.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
30  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
3.3V  
3.3V  
FB1  
VDDO  
muRata, BLM18BB221SN1  
Output Termination Example  
output shown (Note 3)  
-
LVDS  
VDD  
C14  
C15  
C13  
0.1uF  
10uF  
0.1uF  
C4  
C5  
C6  
C7  
0.1uF  
0.1uF  
0.1uF  
0.1uF  
FB2  
Zo = Zo_Dif f = 100-ohm  
VDD  
U1  
muRata, BLM18BB221SN1  
+
-
C9  
C10  
R2 10  
C11  
C12  
R1  
C8  
0.1uF  
10uF  
0.1uF  
10uF  
0.1uF  
100  
C1  
16MHz to 40 MHz  
27  
26  
28  
X1  
12pF  
Q0  
Q0  
5pF  
OE0  
OE1  
(Note 1)  
OE0  
1
2
VDDO  
C2  
XTAL_I N  
24  
23  
22  
XTAL_OU T  
Q1  
Q1  
5pF  
(Note 1)  
CLK_SEL  
4
5
R17  
125  
R4  
(Note 2)  
(Note 1)  
CLK_SEL  
CLK0  
OE1  
CLK0  
6
30  
31  
37  
38  
39  
40  
LOCK_IND  
125  
CLK0  
LOCK_IND  
9
CLK_ACTIVE  
HOLDOVER  
CLKBAD  
CLK1BAD  
XTALBAD  
Zo = 50-ohm  
Zo = 50-ohm  
Input Termination  
UFT  
CLK1  
CLK_ACTIVE  
HOLDOVER  
CLK0BAD  
+
-
10  
R5  
Example  
- LVDS input  
CLK1  
(Note 1)  
PLL_BYPASS  
12  
18  
17  
15  
14  
16  
shown (Note 3)  
100  
(Note 2)  
PLL_BYPASS  
S_A0  
CLK1BAD  
S_A0  
(Note 1)  
XTALBAD  
nCLK0  
S_A1  
(Note 1)  
S_A1  
34  
33  
SCLK  
R6  
84  
R7  
84  
3-pole loop filter  
SCLK  
LF1  
LF0  
SDATA  
SDATA  
CONFIG  
VDD  
CONFIG  
(Note 1)  
(Note 2)  
C3  
0.001uF  
R9  
R10  
125  
R3  
Output Termination Example  
output shown (Note 3)  
-
LVPECL  
125  
R11  
220K  
Rs  
R12  
CLK1  
4.7K  
4.7K  
470K  
Input Termination  
Cp  
Example  
- LVPECL  
nCLK1  
Cs  
input shown (Note 3)  
VDD  
0.001uF  
1uF  
R14  
84  
R15  
84  
Logic Input Pin Examples  
Notes  
Note 1: CE0, OE1, CLK_SEL, PLL_BYPASS, S_A0 and S_A1 are digital control inputs. If  
external pull-up/down needed, see "Logic Input Pin Examples" shown at left. Please note  
that OE0 and OE1 are internally pulled up so no external pull-ups are required to enable  
them.  
VDD  
VDD  
2-pole loop filter - (optional)  
Set Logic  
Input to '1'  
Set Logic  
Input to '0'  
LF1  
LF0  
RU1  
RU2  
1K  
Not Installed  
Note 2: CLK_SEL, PLL_BYPASS and CONFIG are internally pulled down. No external  
compononents required to select default condition.  
To Logic  
To Logic  
Input pins  
Input pins  
Rs  
470K  
Note 3: Other configurations are supported. Please contact IDT for details.  
Cp  
Cs  
RD1  
Not Installed  
RD2  
1K  
0.001uF  
1uF  
Figure 11. IDT8T49N203I Application Schematic  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
31  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
LVPECL Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8T49N203I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8T49N203I is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 332mA = 1150.4W  
Power (outputs)MAX = 33.2mW/Loaded Output pair  
If all outputs are loaded, the total power is 2 * 33.2mW = 66.4mW  
Total Power_MAX (3.465V, with all outputs switching) = 1150.4mW + 66.4mW = 1216.8mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 32.4°C/W per Table 9 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.127W * 32.4°C/W = 124.4°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 9. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
32.4°C/W  
25.7°C/W  
23.4°C/W  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
32  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
3. Calculations and Equations.  
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.  
LVPECL output driver circuit and termination are shown in Figure 12.  
VCCO  
Q1  
VOUT  
RL  
50Ω  
VCCO - 2V  
Figure 12. LVPECL Driver Circuit and Termination  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of  
VCCO – 2V.  
•
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.7V  
(VCCO_MAX – VOH_MAX) = 0.7V  
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.5V  
(VCCO_MAX – VOL_MAX) = 1.5V  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =  
[(2V – 0.7V)/50Ω] * 0.7V = 18.2mW  
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =  
[(2V – 1.5V)/50Ω] * 1.5V = 15mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
33  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
LVDS Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8T49N203I.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8T49N203I is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
•
•
Power (core)MAX = VCC_MAX * (ICC_MAX + ICCA_MAX) = 3.465V * (284mA + 30mA) = 1088.01mW  
Power (outputs)MAX = VCCO_MAX* ICCO_MAX = 3.465V * 40mA = 138.6mW  
Total Power_MAX = 1088.01mW + 138.6mW = 1226.61mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 32.4°C/W per Table 10 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 1.227W * 32.4°C/W = 124.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 10. Thermal Resistance θJA for 40 Lead VFQFN, Forced Convection  
θJA by Velocity  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
32.4°C/W  
25.7°C/W  
23.4°C/W  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
34  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Reliability Information  
Table 11. θJA vs. Air Flow Table for a 40 Lead VFQFN  
θJA vs. Air Flow  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
32.4°C/W  
25.7°C/W  
23.4°C/W  
Transistor Count  
The transistor count for IDT8T49N203I is: 50,917  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
35  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
40 Lead VFQFN Package Outline and Package Dimensions  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
36  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
40 Lead VFQFN Package Outline and Package Dimensions, continued  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
37  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Ordering Information  
Table 12. Ordering Information  
Part/Order Number  
Marking  
Package  
“Lead-Free” 40 Lead VFQFN  
“Lead-Free” 40 Lead VFQFN  
Shipping Packaging  
Tray  
Temperature  
-40°C to +85°C  
-40°C to +85°C  
8T49N203A-dddNLGI  
8T49N203A-dddNLGI8  
IDT8T49N203A-dddNLGI  
IDT8T49N203A-dddNLGI  
Tape & Reel  
NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
38  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
Revision History Sheet  
Rev  
Table  
T12  
T8  
Page  
38  
Description of Change  
Date  
A
5/29/2012  
Ordering Information Table - deleted quantity from tape & reel.  
17  
Per Errata #NEN-12-02, AC Characteristics Table - corrected fourth row test condition  
of RMS Phase Jitter LBW Mode from fIN - 25MHz to fIN - 19.44MHz.  
B
C
8/10/2012  
10/9/2012  
T5A - T5E  
13 - 14  
34  
Per Errata #NEN-12-07, Power Supply Tables - changed VCCA min. specs and ICCA  
max specs.  
LVDS Power Considerations - updated calculations to correspond to ICCA spec.  
IDT8T49N203ANLGI REVISION C OCTOBER 9, 2012  
39  
©2012 Integrated Device Technology, Inc.  
IDT8T49N203I Data Sheet  
FemtoClock® NG Universal Frequency Translator  
We’ve Got Your Timing Solution  
6024 Silver Creek Valley Road Sales  
Technical Support  
800-345-7015 (inside USA)  
netcom@idt.com  
San Jose, California 95138  
+408-284-8200 (outside USA) +480-763-2056  
Fax: 408-284-2775  
www.IDT.com/go/contactIDT  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,  
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not  
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the  
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any  
license under intellectual property rights of IDT or any third parties.  
IDT’s products are not intended for use in applications involving extreme environmental conditons or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signif-  
icantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third  
party owners.  
Copyright 2012. All rights reserved.  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明