8T74S208C-01NLGI8 [IDT]
2.5 V Differential LVDS Clock Divider and Fanout Buffer;
| 型号： | 8T74S208C-01NLGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5 V Differential LVDS Clock Divider and Fanout Buffer |
| 文件： | 总20页 (文件大小：469K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V Differential LVDS Clock Divider
and Fanout Buffer
8T74S208C-01
Datasheet
General Description
Features
The 8T74S208C-01 is a high-performance differential LVDS clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T74S208C-01 is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T74S208C-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
One differential input reference clock
Differential pair can accept the following differential input levels:
LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVDS outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enabled/ disabled by I2C interface
Output skew: 45ps (maximum)
Output rise/fall times: 370ps (maximum)
Low additive phase jitter, RMS: 96fs (typical)
Full 2.5V supply voltage
Outputs disabled at power-up
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
Q0
nQ0
31 30 29 28 27 26 25
32
Q1
nQ1
fREF
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
ADR1
GND
Q0
FSEL0
GND
nQ7
Q7
IN
÷1, ÷2,
÷4, ÷8
nIN
Q2
nQ2
50
50
VT
nQ0
Q1
Q3
nQ3
Pulldown (2)
FSEL[1:0]
nQ6
Q6
2
Q4
nQ4
nQ1
GND
VDDO
GND
VDDO
Q5
nQ5
Pullup
SDA
I2C
9
10 11 12 13 14 15 16
Pullup
8
SCL
Q6
nQ6
Pulldown (2)
ADR[1:0]
2
Q7
nQ7
8T74S208C-01
32-Lead VFQFN, 5mm x 5mm x 0.925mm
©2016 Integrated Device Technology, Inc.
1
August 22, 2016
8T74S208C-01 Datasheet
Pin Descriptions and Pin Characteristics
1
Table 1. Pin Descriptions
Number
1
Name
ADR1
GND
Q0
Type
Description
Input
Pulldown
I2C Address input. LVCMOS/LVTTL interface levels.
2
Power
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Power
Ground pin.
3
Differential output pair 0. LVDS interface levels.
Differential output pair 1. LVDS interface levels.
4
nQ0
Q1
5
6
nQ1
GND
VDDO
Q2
7
Ground pin.
8
Output supply pin.
9
Differential output pair 2. LVDS interface levels.
Differential output pair 3. LVDS interface levels.
Differential output pair 4. LVDS interface levels.
Differential output pair 5. LVDS interface levels.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
VDDO
GND
Q6
Output supply pin.
Ground pin.
Differential output pair 6. LVDS interface levels.
nQ6
Q7
Differential output pair 7. LVDS interface levels.
Ground pin.
nQ7
GND
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
24
FSEL0
Input
Pulldown
Pulldown
Frequency divider select control. See Table 3A for function.
LVCMOS/LVTTL interface levels.
25
26
27
FSEL1
IN
Input
Input
Non-inverting differential clock input. RT = 50 termination to VT.
Termination
Input
Input for termination. Both IN and nIN inputs are internally terminated 50
to this pin. See input termination information in the applications section.
VT
28
29
nIN
Input
Inverting differential clock input. RT = 50 termination to VT.
VDD
Power
Power supply pin.
I2C Data Input/Output. Input. LVCMOS/LVTTL interface levels.
Output: open drain.
30
SDA
I/O
Pullup
31
32
SCL
Input
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
I2C Address input. LVCMOS/LVTTL interface levels.
ADR0
Pulldown
NOTE 1: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
©2016 Integrated Device Technology, Inc.
2
August 22, 2016
8T74S208C-01 Datasheet
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
2
RPULLDOWN
RPULLUP
51
51
k
k
©2016 Integrated Device Technology, Inc.
3
August 22, 2016
8T74S208C-01 Datasheet
Function Tables
8T74S208C-01 is a combination of a 5-bit fixed addresses and two
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T74S208C-01 devices on the same
bus.
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
1
Table 3A. FSEL[1:0] Input Selection Function Table
2
Table 3D. I C Slave Address
Input
7
1
6
1
5
0
4
1
3
0
2
1
0
FSEL1
FSEL0
Operation
ADR1 ADR0 R/W
0 (default)
0 (default)
fQ[7:0] = fREF ÷ 1
0
1
1
1
0
1
fQ[7:0] = fREF ÷ 2
SCL
fQ[7:0] = fREF ÷ 4
fQ[7:0] = fREF ÷ 8
NOTE 1: FSEL1, FSEL0 are asynchronous controls
SDA
Output Enable Operation
START
Valid Data
Acknowledge
STOP
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
2
Figure 1. Standard I C Transaction
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDAis synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
Table 3B. Individual Output Enable Control
Bit
STOP (P) – defined as low-to-high transition on SDA while holding
SCL HIGH
Dn
Operation
0
Output Qx, nQx is enabled.
Output Qx, nQx is disabled in high-impedance
state.
S
DevAdd W A Data Byte
A P
1 (default)
Figure 2. Write Transaction
Table 3C. Individual Output Enable Control
Bit
D7
Q7
1
D6
Q6
1
D5
Q5
1
D4
Q4
1
D3
Q3
1
D2
Q2
1
D1
Q1
1
D0
Q0
1
Output
Default
S
DevAdd R A
Data Byte
A P
2
Figure 3. Read Transaction
I C Interface Protocol
The 8T74S208C-01 uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
S – Start or Repeated Start
W – R/W is set for Write
R – R/W is set for Read
A – Ack
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I2C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I2C slave address of the
DevAdd –7 bit Device Address
P – Stop
©2016 Integrated Device Technology, Inc.
4
August 22, 2016
8T74S208C-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
±35mA
Input Termination Current, IVT
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Storage Temperature, TSTG
-65C to 150C
125°C
Maximum Junction Temperature, TJMAX
ESD - Human Body Model 1
2000V
ESD - Charged Device Model 1
500V
NOTE 1: According to JEDEC/JS-001-2012/JESD22-C101E.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
64
Units
V
Power Supply Voltage
Output Supply Voltage
Power Supply Current
VDDO
IDD
2.375
2.5
V
54
mA
All Outputs are Enabled and
Terminated
IDDO
Output Supply Current
155
182
mA
.
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDO = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
Parameter
Test Conditions
VDD = 2.5V ± 5%
VDD = 2.5V ± 5%
Minimum
1.7
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.7
Units
V
FSEL[1:0],
ADR[1:0]
Input
VIH
High Voltage1
SCL, SDA
1.9
V
FSEL[1:0],
ADR[1:0]
VDD = 2.5V ± 5%
-0.3
V
Input
VIL
IIH
IIL
Low Voltage1
SCL, SDA
VDD = 2.5V ± 5%
-0.3
0.5
V
FSEL[1:0],
ADR[1:0]
VDD = VIN = 2.625V
150
µA
µA
µA
µA
Input
High Current
SCL, SDA
V
DD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
DD = 2.625V, VIN = 0V
5
FSEL[1:0],
ADR[1:0]
-10
Input
Low Current
SCL, SDA
V
-150
NOTE 1: VIL should not be lower than -0.3V and VIH should not be higher than VDD + 0.3V.
©2016 Integrated Device Technology, Inc.
5
August 22, 2016
8T74S208C-01 Datasheet
Table 4C. Differential Input DC Characteristics, VDD = VDDO = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input Voltage
Swing1
VIN
IN, nIN
0.15
1.2
V
Common Mode Input
Voltage1, 2
VCMR
VDIFF
RIN
1.2
0.3
40
V
DD – (VIN/2)
V
V
Differential Input
Voltage Swing
IN, nIN
2.4
60
IN,
nIN to VT
Input Resistance
50
Differential Input IN to nIN,
Resistance VT = open
RIN, DIFF
80
100
120
NOTE 1: VIL should not be less than -0.3V and VIH should not be greater than VDD.
NOTE 2: Common Mode Input Voltage is defined as the cross point.
.
Table 4D. LVDS DC Characteristics, VDD = VDDO = 2.5V, T = -40°C to 85°C
A
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
VOD
VOS
50
1.120
1.425
50
VOS
VOS Magnitude Change
mV
©2016 Integrated Device Technology, Inc.
6
August 22, 2016
8T74S208C-01 Datasheet
AC Electrical Characteristics
1
Table 5. AC Electrical Characteristics, VDD = VDDO = 2.5V ± 5%, T = -40°C to 85°C
A
Symbol
fREF
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
kHz
Input
Frequency
IN, nIN
1
fSCL
I2C Clock Frequency
400
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section, measured with
FSEL[1:0] = 00
f
REF =156.25MHz,
tJIT
Integration Range:
12kHz – 20MHz
96
120
fs
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
FSEL[1:0] = 11
420
580
680
780
700
880
1080
1180
45
ps
ps
ps
ps
ps
ps
ps
%
Propagation
Delay2
IN, nIN to
Qx, nQx
tPD
tsk(o)
tsk(p)
tsk(pp)
Output Skew3, 4
Pulse Skew
FSEL[1:0] = 00
55
Part-to-Part Skew4, 5, 6
200
FSEL[1:0] = 00
FSEL[1:0] = 01
FSEL[1:0] = 10
FSEL[1:0] = 11
50
50
50
50
48
48
48
52
52
52
%
odc
Output Duty Cycle7
%
%
Output Enable and
Output Enable/ Disable State
from/ to Active/ Inactive
tPDZ
1
µs
Disable Time8
20% to 80%
10% to 90%
155
245
230
370
ps
ps
tR / tF
Output Rise/ Fall Time
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-
spoint.
NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices.
NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 8: Measured from SDA rising edge of I2C stop command.
©2016 Integrated Device Technology, Inc.
7
August 22, 2016
8T74S208C-01 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Typical Phase Jitter at 156.25MHz
Additive Phase: 96fs (typical)
Offset from Carrier Frequency (Hz)
The input source is 156.25MHz Wenzel Oscillator.
©2016 Integrated Device Technology, Inc.
8
August 22, 2016
8T74S208C-01 Datasheet
Parameter Measurement Information
V
DD
V
V
,
DD
nIN
IN
DDO
VIN
Cross Points
VCMR
GND
LVDS Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
Qx
nQx
Qx
Part 2
nQy
Qy
nQy
Qy
tsk(pp)
Part-to-Part Skew
Output Skew
nQx
80%
80%
VOD
20%
nIN
IN
20%
Qx
tF
tR
nQy
nQx
Qy
90%
90%
tPLH
tPHL
VOD
10%
tsk(p)= |tPHL - tPLH
|
10%
Qx
tF
tR
Pulse Skew
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc.
9
August 22, 2016
8T74S208C-01 Datasheet
Parameter Measurement Information, continued
nQx
Qx
nIN
IN
nQx
Qx
tPD
Propagation Delay
Output Duty Cycle/Pulse Width/Period
nIN
VDIFF_IN
VIN
IN
Differential Voltage Swing = 2 x Single-ended VIN
Single-Ended & Differential Input Voltage Swing
Differential Output Voltage Setup
Offset Voltage Setup
©2016 Integrated Device Technology, Inc.
10
August 22, 2016
8T74S208C-01 Datasheet
Applications Information
Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both differential signals must
meet the VIN and VCMR requirements. Figure 4A to Figure 4C show
interface examples for the IN/nIN input with built-in 50 terminations
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
2.5V
2.5V
3.3V or 2.5V
2.5V
LVD
S
Zo = 50
Zo = 50
Ω
Ω
Zo = 50
Ω
Ω
IN
IN
50
Ω
Ω
50
Ω
Ω
Zo = 50
VT
nIN
VT
nIN
50
50
LVPECL
R1
18
Ω
Receiver
Receiver
w ith Built-in
w ith Built-in
50Ω
50Ω
Figure 4A. IN/nIN Input with Built-In 50 driven by an
Figure 4C. IN/nIN Input with Built-In 50 driven by an
LVDS Driver
LVPECL Driver
2.5V
2.5V
Zo = 50
Ω
Ω
IN
50
Ω
Ω
VT
nIN
50
Zo = 50
CML – Open Collector
Receiver
with Built-in
50
Ω
Figure 4B. IN/nIN Input with Built-In 50 Driven by a CML
Driver with Open Collector
©2016 Integrated Device Technology, Inc.
11
August 22, 2016
8T74S208C-01 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
PIN
SOLDER
EXPOSED HEAT SLUG
PIN
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pullup or pulldown resistors; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
©2016 Integrated Device Technology, Inc.
12
August 22, 2016
8T74S208C-01 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 6A can be used
with either type of output structure. Figure 6B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
LVDS
Driver
LVDS
ZT
Receiver
Figure 6A. Standard LVDS Termination
Z
T
2
ZO ZT
LVDS
LVDS
Driver
Receiver
C
Z
T
2
Figure 6B. Optional LVDS Termination
©2016 Integrated Device Technology, Inc.
13
August 22, 2016
8T74S208C-01 Datasheet
Power Considerations
1. Power Dissipation.
The total power dissipation for the 8T74S208C-01 is the sum of the core power plus the power dissipated due to the load. The following is the
power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
Note: IDD_MAX and IDDO_MAX @ 85°C = 57.7mA and 164.5mA, respectively.
▪ Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 57.7mA = 151.46mW
▪ Power (output)MAX = VDDO_MAX * IDDO = 2.625V * 164.5mA = 431.81mW
▪ Power Dissipation for internal termination RT
Power (RT)MAX = (VIN_MAX)^2/80 = 18mW
Total Power_MAX = (2.625V, with all outputs switching) = 151.46mW + 431.81mW + 18mW = 601.27mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.601W * 42.7°C/W = 111°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance for 32-Lead VFQFN, Forced Convection
JA
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
42.7°C/W
37.3°C/W
33.5°C/W
©2016 Integrated Device Technology, Inc.
14
August 22, 2016
8T74S208C-01 Datasheet
Reliability Information
Table 7. vs. Air Flow Table for a 32-Lead VFQFN
JA
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
42.7°C/W
37.3°C/W
33.5°C/W
Transistor Count
The transistor count for 8T74S208C-01 is 4969.
©2016 Integrated Device Technology, Inc.
15
August 22, 2016
8T74S208C-01 Datasheet
32-Lead VFQFN Package Outline and Package Dimensions
©2016 Integrated Device Technology, Inc.
16
August 22, 2016
8T74S208C-01 Datasheet
32-Lead VFQFN Package Outline and Package Dimensions, continued
©2016 Integrated Device Technology, Inc.
17
August 22, 2016
8T74S208C-01 Datasheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
8T74S208C-01NLGI
8T74S208C-01NLGI8
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
IDT8T74S208C-01NLGI
IDT8T74S208C-01NLGI
32-Lead VFQFN, Lead-Free
32-Lead VFQFN, Lead-Free
Tape & Reel
©2016 Integrated Device Technology, Inc.
18
August 22, 2016
8T74S208C-01 Datasheet
Datasheet Revision History
Revision Date
Description of Change
This is the first release of the 8T74S208C-01 Datasheet.
August 22, 2016
Silicon Revision History
Revision Date
Description of Change
August 22, 2016
Revision C:
8T74S208A-01NLGI to
8T74S208C-01NLGI
▪ Datasheet part number updated from 8T74S208A-01 to 8T74S208C-01.
▪ Power Supply DC Characteristics Table:
– IDD typical parameter from 41mA to 54mA, maximum from 49mA to 64mA.
– IDDO typical parameter from 153mA to 155mA, maximum from 176mA to 182mA.
▪ AC Characteristics Table:
– tPD:
(FSEL[1:0] = 00 row), maximum parameter from 620ps to 700ps.
(FSEL[1:0] = 01 row), maximum parameter from 800ps to 880ps.
(FSEL[1:0] = 10 row), maximum parameter from 920ps to 1080ps.
(FSEL[1:0] = 11 row), maximum parameter from 1050ps to 1180ps.
– tR /tF maximum parameter from 350ps to 370ps.
▪ The Power Considerations section has been updated to reflect the changes in the Power Supply DC
Characteristics Table.
©2016 Integrated Device Technology, Inc.
19
August 22, 2016
8T74S208C-01 Datasheet
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
相关型号：
8TA00835PA
Circular Connector, 6 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
8TA00835PD
Circular Connector, 6 Contact(s), Aluminum Alloy, Male, Crimp Terminal, Receptacle
AMPHENOL
©2020 ICPDF网 联系我们和版权申明