8V79S680NLGI_技术文档

JESD204B Compliant Fanout Buffer

and Divider

8V79S680

Datasheet

Description

Features

▪ Supports high-speed, low phase noise converter clocks

The 8V79S680 is a fully integrated, clock and SYSREF signal fanout

buffer for JESD204B applications. It is designed as a high-performance

clock and converter synchronization solution for wireless base station

radio equipment boards with JESD204B subclass 0, 1 and 2

▪ Distribution, fanout, phase-delay of clock and SYSREF signals

▪ Very low output noise floor: -158.8dBc/Hz noise floor

(245.76MHz)

compliance. The main function of the device is the distribution and

fanout of high-frequency clocks and low-frequency system reference

signals generated by a JESB204B clock generator such as the IDT

8V19N480, extending its fanout capabilities and providing additional

phase-delay. The 8V79S680 is optimized to deliver very low phase noise

clocks and precise, phase-adjustable SYSREF synchronization signals

as required in GSM, WCDMA, LTE, LTE-A radio board implementations.

Low-skew outputs, low device-to-device skew characteristics and fast

output rise/fall times help the system design to achieve deterministic

clock and SYSREF phase relationship across devices.

▪ Supports clock frequencies up to 3GHz, including clock output

frequencies of 983.04MHz, 491.52MHz, 245.76MHz and

122.88MHz

▪ 4 output channels with a total of 16 differential outputs, organized

in:

— 8 dedicated clock outputs

— 8 outputs configurable as SYSREF outputs with individual

phase delay stages, or configurable as additional clock outputs

▪ Each channel contains:

The device distributes the input clock (CLK) and JESD204B SYSREF

signals (REF) to four fanout channels. In each channel, both input clock

and SYSREF signals are fanned-out to multiple clock (QCLK) and

SYSREF (QREF) outputs. Clock signals can be frequency-divided in

each channel. Configurable phase-delay circuits are available for both

clock and SYSREF signals. The propagation delays in all signal paths

are fully deterministic to support fixed phase relationships between clock

and SYSREF signals within one device. Clock divider can be bypassed

for low-latency clock paths. The device facilitates synchronization

between frequency dividers within the device and across multiple

devices, removing phase ambiguity introduced in dividers between

power and configuration cycles.

— frequency dividers: ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16

— clock phase delay circuits

▪ Clock phase delay circuits

— Clock: delay unit is the clock period; 256 steps

— SYSREF: Configurable precision phase delay circuits: 8 steps

of 131ps, 262ps, 393ps or 524ps

▪ Flexible differential outputs:

— LVDS/LVPECL configurable

— Amplitude configurable

— Power-down modes for unused outputs

— Supports DC and AC coupling

Each channel supports clock frequencies up to 3GHz. In an alternative

configuration, for instance JESD204B subclass 0 and 2, the SYSREF

(QREF) outputs can be configured as regular clock outputs adding

additional clock fanout to the device.

— QREF (SYSREF) output pre-bias feature to prevent glitches

when turning output on or off

▪ Supply voltage:

All outputs are very flexible in amplitude configuration, output signal

termination and allow both DC and AC coupling. Outputs can be

disabled and powered-down when not used. The SYSREF output

pre-bias feature supports prevention of power-on glitches and enables

AC-coupling of the system synchronization signals.

— 3.3V core and signal I/O

— 1.8V Digital control SPI I/O (3.3V-tolerant inputs)

▪ 64 VFQFN-P package (9mm x 9mm x 0.85mm)

▪ Ambient temperature range: -40°C to +85°C

The device is configured through a 3-wire SPI serial interface. The

device is packaged in a lead-free (RoHS 6) 64-lead VFQFN package.

The extended temperature range supports wireless infrastructure,

telecommunication and networking end equipment requirements. The

device is a member of the high-performance clock family from IDT.

Typical Applications

▪ JESD204B low phase noise clock and SYSREF signal distribution

▪ Supports JESD204 subclass 0, 1 and 2

▪ Clock distribution device for jitter-sensitive ADC and DAC circuits

▪ Wireless infrastructure

▪ Radar and imaging

▪ Instrumentation and medical

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8V79S680 Datasheet

Block Diagram

Figure 1: Block Diagram

QCLK_A0

nQCLK_A0

Clock

f_IN

QCLK_A1

nQCLK_A1

CLK

nCLK

÷N_A

_{CLK_A}

_{REF_A0}

_{REF_A1}

_{REF_A2}

2x

50

QCLK_A2

nQCLK_A2

VTC

0

1

QREF_A0

nQREF_A0

MUX_A0

MUX_A1

MUX_A2

0

1

QREF_A1

nQREF_A1

0

1

QREF_A2

nQREF_A2

Channel A

QCLK_B0

nQCLK_B0

÷N_B

SYSREF f_REF

_{CLK_B}

_{REF_B0}

_{REF_B1}

REF

nREF

QCLK_B1

nQCLK_B1

2x

50

0

1

QREF_B0

nQREF_B0

MUX_B0

MUX_B1

VTR

0

1

QREF_B1

nQREF_B1

Channel B

f_IN

_{REF_r}

Delay Calibration

Block

QCLK_C0

nQCLK_C0

÷N_C

_{CLK_C}

_{REF_C0}

_{REF_C1}

QCLK_C1

nQCLK_C1

0

1

QREF_C0

nQREF_C0

V_DD

MUX_C0

MUX_C1

50k

0

1

QREF_C1

nQREF_C1

nCS

SDAT

SCLK

SPI

Channel C

Register

File

QCLK_D

nQCLK_D

÷N_D

`

_{CLK_D}

50k

0

1

QREF_D

nQREF_D

MUX_D

_{REF_D}

Channel D

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August 4, 2016

8V79S680 Datasheet

Pin Assignments

Figure 2: Pin Assignments 9mmx9mmx0.85mm 64 VFQFN-P Package (Top View)

64

63 62

61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

QREF_B0

nQREF_B0

QREF_B1

nQREF_B1

V_{DD_QREFB}

48 QREF_A2

47 nQREFA2

46 V_{DD_QREFA2}

45 V_{DD_QCLKA}

44 QCLK_A2

43 nQCLK_A2

42 QCLK_A1

41 nQCLK_A1

40 QCLK_A0

39 nCLK_A0

38 V_{DD_QCLKA}

37 V_{DD_QREFA01}

36 QREF_A1

35 nQREF_A1

34 QREF_A0

33 nQREF_A0

3

4

5

V_{DD_QCLKB}

6

QCLK_B0

nQCLK_B0

QCLK_B1

nQCLK_B1

V_{DD_QCLKB}

7

8

Exposed Pad

(GND)

9

10

11

12

13

14

15

16

V_{DD_QREFC}

QREF_C0

nQREF_C0

QREF_C1

nQREF_C1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

32

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8V79S680 Datasheet

Pin Descriptions

Table 1: Pin Descriptions

Number

Name

Type^a

Description

1,

2

QREF_B0,

nQREF_B0

Differential SYSREF/clock output QREF_B0. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

3,

4

QREF_B1,

nQREF_B1

Differential SYSREF/clock output QREF_B1. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

5

6

V_{DD_QREFB}

V_{DD_QCLKB}

Power

Positive supply voltage (3.3V) for the QREF_B[1:0] outputs.

Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.

7,

8

QCLK_B0,

nQCLK_B0

Output

Differential clock output QCLK_B0. Configurable LVPECL/LVDS style and amplitude.

Differential clock output QCLK_B1. Configurable LVPECL/LVDS style and amplitude.

9,

10

QCLK_B1,

nQCLK_B1

11

12

V_{DD_QCLKB}

V_{DD_QREFC}

Power

Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.

Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.

13,

14

QREF_C0,

nQREF_C0

Differential SYSREF/clock output QREF_C0. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

15,

16

QREF_C1,

nQREF_C1

Differential SYSREF/clock output QREF_C1. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

17

18

V_{DD_QREFC}

V_{DD_QCLKC}

Power

Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.

Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.

19,

20

QCLK_C0,

nQCLK_C0

Output

Differential clock output QCLK_C0. Configurable LVPECL/LVDS style and amplitude.

Differential clock output QCLK_C1. Configurable LVPECL/LVDS style and amplitude.

21,

22

QCLK_C1,

nQCLK_C1

23

24

V_{DD_QCLKC}

V_{DD_QREFD}

Power

Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.

Positive supply voltage (3.3V) for the QREF_D outputs.

25,

26

QREF_D,

nQREF_D

Differential SYSREF/clock output QREF_D. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

27

28

V_{DD_QREFD}

V_{DD_QCLKD}

Power

Positive supply voltage (3.3V) for the QREF_D outputs.

Positive supply voltage (3.3V) for the QCLK_D outputs.

29,

30

QCLK_D,

nQCLK_D

Output

Differential clock output QCLK_D. Configurable LVPECL/LVDS style and amplitude.

31

32

V_{DD_QCLKD}

Power

Positive supply voltage (3.3V) for the QCLK_D outputs.

Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.

V_{DD_QREFA01}

33,

34

nQREF_A0,

QREF_A0

Differential SYSREF/clock output QREF_A0. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

35,

36

nQREF_A1,

QREF_A1

Differential SYSREF/clock output QREF_A1. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

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8V79S680 Datasheet

Table 1: Pin Descriptions (Continued)

Number

Name

Type^a

Power

Description

37

38

V_{DD_QREFA01}

V_{DD_QCLKA}

Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.

Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.

Power

Output

39,

40

nQCLK_A0,

QCLK_A0

Differential clock output QCLK_A0. Configurable LVPECL/LVDS style and amplitude.

Differential clock output QCLK_A1. Configurable LVPECL/LVDS style and amplitude.

Differential clock output QCLK_A2. Configurable LVPECL/LVDS style and amplitude.

41,

42

nQCLK_A1,

QCLK_A1

Output

43,

44

nQCLK_A2,

QCLK_A2

45

46

V_{DD_QCLKA}

V_{DD_QREFA2}

Power

Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.

Positive supply voltage (3.3V) for the QREF_A2 output.

47,

48

nQREF_A2,

QREF_A2

Differential SYSREF/clock output QREF_A2. LVDS style for SYSREF operation,

configurable LVPECL/LVDS style and amplitude for clock operation.

Output

49

50

V_{DD_QREFA2}

V_{DD_REF}

Power

Positive supply voltage (3.3V) for the QREF_A2 output.

Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF

SYSREF inverting and non-inverting differential input. Compatible with LVPECL and LVDS

signals. REF and nREF are internally 50terminated to the VTR pin

51, 52

53

REF, nREF

Input

–

Internal termination for the differential clock input REF, nREF. Both REF and nREF inputs

are internally terminated 50 to this pin. See input termination information in Section

“Application Information”.

VTR

54

55

56

V_{DD_REF}

RES_CAL

V_{DD_CLK}

Power

Analog

Power

Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF

Connect a 2.8 k (1%) resistor to GND for output current calibration.

Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.

Internal termination for the differential clock input CLK, nCLK. Both CLK and nCLK inputs

are internally 50terminated to the VTR pin. See input termination information in Section

“Application Information”.

57

VTC

–

Device clock inverting and non-inverting differential clock input. Compatible with LVPECL

and LVDS signals. CLK and nCLK are internally terminated to VTC through 50.

58, 59

60

nCLK, CLK

V_{DD_CLK}

SDAT

Input

Power

Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.

Input/

Output

Serial Control Port SPI Mode Data Input and Output. 1.8V LVCMOS/LVTTL interface

levels. 3.3V tolerant when input.

61

Serial Control Port SPI Mode Clock Input. 1.8V LVCMOS/LVTTL interface levels.

3.3V-tolerant when input.

62

SCLK

Input

PD

PU

Serial Control Port SPI Chip Select Input. 1.8V LVCMOS/LVTTL interface levels and 3.3V

tolerant.

63

64

nCS

V_{DD_SPI}

GND

Input

Power

Positive supply voltage (3.3V) for the SPI interface.

Exposed

Pad (EP)

Ground supply voltage (GND) and ground return path. Connect to board GND (0V).

a. Internal pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. See Table 22 for values.

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August 4, 2016

8V79S680 Datasheet

Principles of Operation

Overview

The 8V79S680 is a JESD204B Fanout Buffer with Configurable Phase Delay. The device supports the division, phase-delay and distribution of

high-frequency clocks (input: CLK, nCLK) and the fanout and phase-delay of low-frequency synchronization (SYSREF) signals (input: REF/nREF).

Clock and SYSREF signal paths are independent and are organized in channels, with each channel consisting of several clock and SYSREF outputs.

Outputs are configurable with support for LVPECL, LVDS and four amplitude settings. Individual channels and unused circuit blocks support a

powered-down state for reduced power consumption operation. The register map, accessible through a SPI interface with read-back capability

controls the main device settings.

Signal Flow

The device offers four channels with the names A, B, C and D. Each channel supports individual frequency-division, phase-delay and fan-out functions

of the input clock to a total of eight QCLK_y clock outputs; each channel also distributes the SYSREF input signal to multiple QREF_r outputs with

individual per-output phase delay capability.

The central clock distribution ensures low skew clock outputs within each channel; outputs are synchronous across channels (independent on the

divider setting) on the incident rising clock edge for all outputs with equal phase delay settings.

SYSREF output are synchronous with each other for equal phase-delay settings. QCLK_y and QREF_r outputs will be phase-locked to each other if

the CLK and REF inputs are phase-locked. The phase-delay capability in each signal path can be used to establish repeatable and deterministic clock

to SYSREF phase relationships at the outputs.

The CLK and QREF signal paths are optimized for channel isolation. allowing high-speed clocks of 983.04MHz, 1474.56MHz or 1966.08MHz (up to

3GHz) and lower-speed SYSREF signals at e.g. 7.68MHz or 9.6MHz with a minimum of signal crosstalk and spurious signals.

Clock Channel Divider

Each of the four independent frequency dividers N_A-N_Dcan be individually set to the divider values ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16. The dividers are

synchronous and have an equal propagation delay on the incident edge. See Table 2 for the supported frequency divider settings.

Table 2: N_A-DFrequency Divider Settings

N_A-D

Clock Divider

÷1

000

Divider bypass and powered down

001

010

011

100

101

110

111

÷2

÷4

÷6

÷8

÷12

÷16

Not defined

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August 4, 2016

8V79S680 Datasheet

Phase Delay

Output phase delay is independently supported on each clock channel and each SYSREF output. The delay unit of the clock channel phase-delay

circuits _{CLK_x}is a function of the frequency f_INapplied to CLK input: 1 ÷ f_IN.

The delay unit of the SYSREF phase-delay circuits _{REF_r}is a function of an internal oscillator frequency f_DCOand the DLC multiplier setting. The

oscillator is fully self-contained and located in delay calibration block (DCB). At startup, this oscillator is calibrated with the input frequency f_INas

reference. After the calibration, the oscillator is turned-off to save power and to eliminate noise. See Table 3 for details on the delay unit, number of

available steps and the delay range.

Table 3: Delay Circuit Characteristics

Delay Circuit

Unit

Steps

Range

a

1 ÷ f_IN

256 ÷ f_IN

Clock channel _{CLK_x}

256

1.017ns at f_IN= 983.04MHz

0 to 259.3ns at f_IN= 983.04MHz

b

c

T_DCB

0…7 * T_DCB

DLC = 0: 131ps

DLC = 1: 262ps

DLC = 2: 393ps

DLC = 3: 524ps

DLC = 0: 0 to 0.917ns

DLC = 1: 0 to 1.834ns

DLC = 2: 0 to 2.751ns

DLC = 3: 0 to 3.668ns

SYSREF _{REF_r}

8

a. At f_IN= 983.04MHz, the clock channel delay range is equal to 260.416ns and encompasses 32 periods of a 122.88MHz clock signal.

b. T_DCB~ DLC ÷ (8·f_DCO). f_DCO= 983.04MHz. DLC = 1, 2, 3 or 4.

c. SYSREF phase delay supports 8 delay stops within one input reference period for f_IN= 254.76MHz to f_IN= 983.04MHz.

Delay Calibration Block (DCB)

The DCB sets the SYSREF delay unit by providing a reference signal to the QREF_r delay circuits. Figure 3 shows the functional diagram. The DCB

requires configuration and calibration. Verification of the calibration is optional.

Description. The DCB consists of an internal DCO running at f_DCO= 983.04±20MHz, three frequency dividers P_DCB,M_DCBand N_DCBand a digital

hold circuit. The DCB input frequency is the device input frequency f_INat the differential CLK, nCLK input. The input frequency acts as a reference to

lock the oscillator to a stable and known frequency.

The output of the DCB is the effective delay unit T_DCBwhich is approx. one eighth of the oscillator period multiplied by the DLC multiplier. The DLC

multiplier extends the delay unit by a factor of 1, 2, 3 or 4. For instance, at a DCO frequency of 983.04MHz, DLC = 1 sets the SYSREF delay unit to

131ps; DLC = 2 sets the delay unit to 262ps, etc.

Configuration. Select a desired delay unit and corresponding DLC multiplier from Table 4. DLC[1:0] also sets the N_DCBdivider. Then, find a P_DCB

and M_DCBdivider configuration to locate the oscillator frequency into the range of f_DCO= 983.04MHz according to the formula in Figure 3. The DCO

lock condition is f₁= f₂while both f₁and f₂must be lower than 200MHz. For instance, if f_IN= 245.76MHz and the smallest possible SYSREF delay

unit is desired, set DLC = 1 (DLC[1:0] = 00; also sets N_DCB= ÷1). Then, set P_DCB= ÷24 and M_DCB= ÷96. As a result, f₁= f₂= 10.24MHz, f_DCO

983.04MHz. This example configuration results in a delay unit of measured: 131ps. Figure 5 shows more configuration examples.

=

Calibration. Calibration requires a valid DCB configuration with the DCO locking to an input frequency. Setting DCB_CAL = 1 starts an automatic

calibration. At the end, the DCB_CAL bit will clear, the delay unit value is stored digitally and the DCO, P_DCB,M_DCBand N_DCBfrequency dividers turn

off. The QREF_r delay circuits now use the stored constant delay unit. The delay unit remains digitally stored until the next power cycle. The DCB

calibration must run once as part of the device startup procedure and must be re-run after each input frequency or DCB configuration change.

Verification. Verify a successful calibration by reading the DAC_CODE value. 0 < DAC_CODE< 32767 indicates a successful calibration. If

DAC_CODE = 0 or DAC_CODE = 32767, the DCB calibration should be re-run with an alternative P_DCB,M_DCBsetting while maintaining the desired

M_DCB· N_DCB/P_DCBratio for locking the DCO to the input frequency.

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August 4, 2016

8V79S680 Datasheet

Figure 3: DCB Functional Diagram

DCB_CAL

f

IN

DCO

----------------------------------------

----------------

=

P

M

 N

f_IN

f₁

f₂

DCB

÷P_DCB

÷M_DCB

DCO

983.04±20MHz

Digital

Hold

Delay Unit T_DCB

131ps · (1+DLC[1:0])

÷N_DCB

f

= 983MHz  20MHz

DCO

DLC[1:0]

Table 4: DCB Delay Unit at f_DCO= 983.04MHz

DLC

T_DCB

Delay Unit (ps)

N_DCB

DLC[1:0] Setting

Numeric Value

131

262

393

524

00

01

10

11

1

2

3

4

1

2

3

4

Table 5: DCB Divider Configuration Examples^a

T_DCB

Delay Unit in ps

f_IN(MHz)

DLC

P_DCB

M_DCB

131

1

2

3

4

1

2

3

4

1

2

3

4

24

48

96

48

32

24

96

48

32

24

96

48

32

24

262

245.76

393

524

131

262

491.52

393

524

131

262

983.04

393

524

a. f_DCO= 983.04MHz.

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August 4, 2016

8V79S680 Datasheet

QCLK to SYSREF Phase Alignment

To achieve an output phase alignment between the QCLK_y clock and the QREF_r SYSREF outputs, the CLK and REF input signals must be phase

aligned or have a known, deterministic phase relationship. Figure 4 shows an example output phase alignment for aligned clock and SYREF inputs.

The closest (smallest phase error) output alignment is achieved by setting the clock phase delay register _{QCLK_Y}to 0x00 (clock) and the SYSREF

phase delay register _{QCLK_Y}to 0x04. With a SYSREF phase delay setting of 0x03 or less, the QREF_r output phase is in advance of the QCLK_y

phase, which is applicable in JESD204B application. Phase delay settings and propagation delays are independent on the clock and SYSREF

frequencies. Table 6 shows recommended phase delay setting several device configurations.

Figure 4: QCLK to QREF Phase Alignment

Input Phase

Alignment

1017 ps

CLK

983.04MHz

REF

7.68MHz

Output Phase

Alignment

t_PD~ 550ps

QCLK_y

_{QCLK_y}= 0x00



t_PD~ 900ps + (4·131)ps

QREF_r

_{REF_r}= 0x04

QREF_r in advance of QCLK_y

QCLK_y

_{QCLK_y}= 0x00



131ps

262ps

QREF_r

_{REF_r}= 0x03

QREF_r

_{REF_r}= 0x02

Table 6: Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment^a

Divider Configuration

CLK_y

REF_r

N = ÷1

0x00

0x04

a. QCLK and QREF outputs are aligned on the incident edge.

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August 4, 2016

8V79S680 Datasheet

Differential Outputs

Table 7: Output Features

Output

Style

Ampl.^a

Disable

Power Down

DC Bias

Termination

d

QCLK_y^b, QREF_r^c

250-1000mV

4 steps

LVPECL

LVDS

50 to V_T

Yes

–

100 differential^{e f}

(Clock)

d

LVPECL

LVDS

–

Yes^g

50 to V_T

QREF_r

250-1000mV

4 steps

Yes

100 differential^{e f}

(SYSREF)

a. Amplitudes are measured single-ended. Differential amplitudes supported are 500mV, 1000mV, 1500mV and 2000mV.

b. y = A0, A1, A2, B0, B1, C0, C1 and D.

c. r = A0, A1, A2, B0, B1, C0, C1 and D.

d. V_T= V_{DD_V}– 1.5V (250mV amplitude setting), V_{DD_V}– 1.75V (500mV amplitude setting), V_{DD_V}– 2.0V (750mV amplitude setting),

V_{DD_V}– 2.25V (1000mV amplitude setting).

e. AC coupling and DC coupling supported.

f. See Section “Application Information” on page 42 for output termination information.

g. In JESD204B applications, it is recommended to use QREF_r (SYSREF) outputs configured to LVDS and 500mV amplitude. AC-coupling

and DC-coupling is supported. See?? for more information.

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August 4, 2016

8V79S680 Datasheet

Table 8: Individual Clock Output (QCLK_y) Settings^a

PD STYLE EN

A[1:0]

Output Power

Termination^b

State

Amplitude (mV)

1

X

0

X

Off

100 differential (LVDS) or no termination

Off

Disable^c

X

XX

00

01

10

11

XX

00

01

10

11

250

500

750

1000

X

0

100 differential (LVDS)

1

0

1

Enable

Disable

Enable

0

On

250

500

750

1000

1

50 to V_T(LVPECL)

a. Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0).

b. See Section “Application Information” on page 42 for output termination information.

c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.

Table 9: Individual SYSREF Output (QREF_r) Settings^a

Output

Power

PD

STYLE Enable A[1:0]

nBIAS

Termination^b

State

Amplitude (mV)

100 differential or no

1

X

0

X

0

X

Off

X

termination

XX

00

0

1

0

Disable^c

Enabled

X

250

See Table 10

01

100 differential (LVDS)

500

1

10

11

XX

00

01

10

11

Enabled

Disable

750

1000

X

0

On

0

1

250

500

750

1000

1

0

50 to V_T(LVPECL)

Enable

a. Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).

b. See Section “Application Information” on page 42 for output termination information.

c. Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.

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8V79S680 Datasheet

Table 10: QREF_r Setting for JESD204B Applications

QREF_r Outputs (LVDS, 500mV amplitude)

BIAS_TYPE nBIAS_r

Application

Active Rising Edge on the

REF Input

Initial

SYSREF Completed

0

Static Low (QREF = L, nQREF_r = H)

Start switching for the

number of received

0

QREF_r DC coupled

Static Low

(QREF = L, nQREF_r = H)

Released to static low

(QREF = L, nQREF_r = H)

1

SYSREF pulses

0

Static LVDS crosspoint level (QREF = nQREF_r = VOS)

Start switching for the

number of received

SYSREF pulses

Released to static LVDS

crosspoint level

(QREF = nQREF_r = VOS)

1

QREF_r AC coupled

Static LVDS crosspoint level

(QREF = nQREF_r = VOS)

1

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8V79S680 Datasheet

Device Startup, Reset and Synchronization

At startup, an internal POR (power-on reset) resets the device and sets all register bits to its default value. In the default configuration the QCLK_y

and QREF_r outputs are disabled at startup.

Recommended configuration sequence (in order):

1. (Optional) set the value of the CPOL register bit to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read

accesses.

2. Configure the channel circuits and the outputs to the desired values and configure the DCB:

▪ Output source MUX_r, output divider N_A-D, clock delay _A-D;MUX-output style, amplitude and power down mode for QCLK_y and

QREF_r outputs

▪ For synchronization between multiple devices: Set N_A-D= ÷1 and set BYP_INIT = 1)

▪ (Optional) the global BIAS_TYPE bit and nBIAS_r for each QREF_r in preparation for JESD204B/SYSREF operation

▪ Phase delay for _{REF_r}values for the QREF_r outputs

▪ Setup the DCB settings DLC, P_DCBand M_DCBas described in the paragraph Configuration, see Delay Calibration Block (DCB)

3. If not already applied: apply a valid input frequency to CLK. Set the PB_CAL bit and the DCB_CAL bit to start the calibration of the precision

bias current circuit and the DCB calibration. Both bits will auto-clear. See paragraph Configuration in section Delay Calibration Block (DCB).

▪ (Optional): verify the success of the DCB calibration by reading the DAC_CODE value. See paragraph Verification in section Delay

Calibration Block (DCB)

4. Set the initialization bit INIT_CLK. This will initiate the N_x divider and CLK_x delay circuits and synchronize them to each other. The

INIT_CLK bit will self-clear.

5. At this point, the configuration of the registers 0x00 to 0x73 should be completed and the SPI transfer ended. Set nCS to high level.

6. In a separate SPI write access, enable the outputs as desired by accessing the output-enable registers 0x74 and 0x76.

Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF range.

Changing Frequency Dividers and Phase Delay Values

Clock Frequency Divider and Delay

Following procedure has to be applied for a change of a clock divider and phase delay value N_A-D,and _CLKA-D:

1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read

accesses.

2. (Optional) disable the outputs whose frequency divider or delay value is changed.

3. Configure the N_A-Ddividers and the delay circuits _CLKA-Dto the desired new values.

▪ For synchronization between multiple devices: Set N_A-D= ÷1 and set BYP_INIT = 1)

4. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will

self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.

5. (Optional) Enable the outputs whose frequency divider was changed.

SYSREF Delay

Following procedure has to be applied for a change of any SYSREF phase delay value _{REF_r:}

1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read

accesses.

2. Configure any delay circuits _{REF_r}to their desired new values. During configuration of _{REF_r}outputs are not stopped or interrupted.

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8V79S680 Datasheet

SPI Interface

The 8V79S680 has a 3-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any of the

internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDAT (serial data input and output), and nCS

(chip select) pins. A data transfer consists of any integer multiple of 8 bits and is always initiated by the SPI master on the bus. Internal register data

is organized in SPI bytes of 8 bits each. If nCS is at logic high, the SDAT data I/O is in high-impedance state and the SPI interface of the 8V79S680

is disabled. In a write operation, data on SDAT will be clocked in on the rising edge of SCLK. In a read operation, data on SDAT will be clocked out

on the falling or rising edge of SCLK depending on the CPOL setting (CPOL = 0: output data changes on the falling edge, CPOL = 1: output data

changes on the rising edge).

Starting a data transfer requires nCS to set and hold at logic low level during the entire transfer. Setting nCS = 0 will enable the SPI interface with

SDAT in data input mode. The master must initiate the first 8-bit transfer. The first bit presented to the slave is the direction bit R/nW (1 = Read,

0 = Write) and the following seven bits are the address bits A[0:6] pointing to an internal register in the address space 0 to 127. Data is presented

with the LSB (least significant bit) first.

Read operation from an internal register: a read operation starts with an 8 bit transfer from the master to the slave: SDAT is clocked on the rising

edge of SCLK. The first bit is the direction bit R/nW which must be to 1 to indicate a read transfer, followed by 7 address bits A[0:6]. After the first 8

bits are clocked into SDAT, the SDAT I/O changes to output: the register content addressed by A[0:6] is loaded into the shift register and the next 8

SCLK falling clock cycles (if CPOL = 0) will then present the loaded register data on the SDAT output and transfer these to the master. Transfers must

be completed by de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is

undefined. SPI byte (8 bit) and back-to-back read transfers of multiple registers are supported with an address auto-increment. During multiple

transfers, nCS must stay at logic low level and SDAT will present multiple registers (A), (A+1), (A+2), etc. with each 8 SCLK cycles. During SPI Read

operations, the user may continue to hold nCS low and provide further bytes in a single block read.

Write operation to a 8V79S680 register: During a write transfer, a SPI master transfers one or more bytes of data into the internal registers of the

8V79S680. A write transfer starts by asserting nCS to low logic level. The first bit presented by the master must set the direction bit R/nW to 0 (Write)

and the 7 address bits A[0:6] must contain the 7-bit register address. Bits D0 to D7 contain 8 bit of payload data, which is written into the register

addressed by A[0:6] at the end of a 8-bit write transfer. Multiple, subsequent register transfers from the master to the slave are supported by holding

nCS asserted at logic low level during write transfers. The 7 bit register address will auto-increment. Transfers must be completed by de-asserting

nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is undefined.

End of transfer: After de-asserting nCS, the SPI bus is available to transfers to other slaves on the SPI bus. See also the READ diagram (Figure 5)

and WRITE diagram (Figure 6) displaying the transfer of two bytes of data from and into registers.

Registers 0x78 to 0xFF: Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF range.

Figure 5: Logic Diagram: READ Data from 8V79S680 Registers for CPOL = 0 and CPOL = 1

SCLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

nCS

SDAT, CPOL=0

SDAT, CPOL=1

Hi-Imp

1

A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

Output Register Data

(Address)

Output Register Data

(Address+1)

Input R=1, 7-bit Address

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8V79S680 Datasheet

Figure 6: Logic Diagram WRITE Data into 8V79S680 Registers

SCLK

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

nCS

Hi-Imp

0

A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

SDAT

Input Register Data

Input nW=0, 7-bit Address

Input Register Data (Address)

(Address+1)

Table 11: SPI Read / Write Cycle Timing Parameters

Symbol

f_SCLK

Parameter

Test Condition

Minimum

Maximum

Unit

SCLK frequency

20

MHz

ns

t_S1

Setup time, nCS (falling) to SCLK (rising)

Setup time, SDAT (input) to SCLK (rising)

Setup time, nCS (rising) to SCLK (rising)

Hold time, SCLK (rising) to SDAT (input)

Hold time, SCLK (falling) to nCS (rising)

Propagation delay, SCLK (falling) to SDAT

Propagation delay, SCLK (rising) to SDAT

Propagation delay, nCS to SDAT disable

5

t_S2

ns

t_S3

ns

t_H1

ns

t_H2

ns

t_PD1F

t_PD1R

t_PD2

CPOL = 0

CPOL = 1

12

ns

Figure 7: SPI Timing Diagram

t_H2

nCS

t_S3

t_S1

SCLK

t_S2t_H1

SDAT

(Input)

t_PD1F

t_PD1R

t_PD2

SDAT

(Output)

High Impedance

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8V79S680 Datasheet

Register Descriptions

This section contains a list of all addressable registers and a register description, sorted by function, followed for a detailed description of each bit

field for each register. Several functional blocks with multiple instances in this device have individual registers controlling their settings, but since the

registers have an identical format and bit meaning, they are described only once, but with an additional table to indicate their addresses and default

values. All writable register fields will come up with a default values as indicated in the Factory Defaults column unless altered by values loaded from

non-volatile storage during the initialization sequence.

Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of the conditions

they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are Reserved. Reserved bit

fields will be unaffected by writes and are undefined on reads.

Table 12: Configuration Registers

Register Address

Register Description

0x00 - 0x17

0x18 - 0x1B

0x1C - 0x1F

0x20

Reserved

SYSREF Control

Reserved

Channel A, Output Divider

Channel A Delay CLK_A

Channel A PD

0x21

0x22

0x23

Reserved

0x24

Output State QCLK_A0

Output State QCLK_A1

Output State QCLK_A2

Reserved

0x25

0x26

0x27

0x28

REF_A0 Delay, MUX, PD

REF_A1 Delay, MUX, PD

REF_A2 Delay, MUX, PD

Reserved

0x29

0x2A

0x2B

0x2C

Output State QREF_A0

Output State QREF_A1

Output State QREF_A2

Reserved

0x2D

0x2E

0x2F

0x30

Channel B, Output Divider

Channel B Delay CLK_B

Channel B PD

0x31

0x32

0x33

Reserved

0x34

Output State QCLK_B0

Output State QCLK_B1

Reserved

0x35

0x36 - 0x37

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8V79S680 Datasheet

Table 12: Configuration Registers

Register Address

Register Description

0x38

0x39

REF_B0 Delay, MUX, PD

REF_B1 Delay, MUX, PD

Reserved

0x3A-0x3B

0x3C

Output State QREF_B0

Output State QREF_B1

Reserved

0x3D

0x3E-0x3F

0x40

Channel C, Output Divider

Channel C Delay CLK_C

Channel C PD

0x41

0x42

0x43

Reserved

0x44

Output State QCLK_C0

Output State QCLK_C1

Reserved

0x45

0x46-0x47

0x48

REF_C0 Delay, MUX, PD

REF_C1 Delay, MUX, PD

Reserved

0x49

0x4A-0x4B

0x4C

Output State QREF_C0

Output State QREF_C1

Reserved

0x4D

0x4E-0x4F

0x50

Channel D, Output Divider

Channel D Delay CLK_D

Channel D PD

0x51

0x52

0x53

Reserved

0x54

Output State QCLK_D

Reserved

0x55-0x57

0x58

REF_D Delay, MUX, PD

Reserved

0x59-0x5B

0x5C

Output State QREF_D

Reserved

0x5D-0x6B

0x6C-0x6D

0x6E-0x6F

0x70

DAC_CODE

General Control

Reserved

0x71-0x73

0x74

General Control

Output State QCLK

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8V79S680 Datasheet

Table 12: Configuration Registers

Register Address

Register Description

0x75

0x76

Reserved

Output State QREF

Reserved

0x77

0x78

Do not use

0x79

0x7A

0x7B

0x7C-0x7D

0x7E

0x7F

0x80-0xFF

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8V79S680 Datasheet

Channel and Clock Output Registers

The content of the channel register and clock output registers set the clock divider, output style, amplitude, power down state, enable state and the

clock phase delay.

Table 13: Channel and Clock Output Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x20

0x30

0x40

0x50

N_A[2:0]

N_B[2:0]

N_C[2:0]

N_D[2:0]

Reserved

0x21

0x31

0x41

0x51

CLK_A[7:0]

CLK_B[7:0]

CLK_C[7:0]

CLK_D[7:0]

0x22

0x32

0x42

0x52

PD_A

PD_B

PD_C

PD_D

Reserved

0x24: QCLK_A0

0x25: QCLK_A1

0x26: QCLK_A2

PD_A0

PD_A1

PD_A2

STYLE_A0

STYLE_A1

STYLE_A2

A_A0[1:0]

Reserved

A_A1[1:0]

A_A2[1:0]

Reserved

0x34: QCLK_B0

0x35: QCLK_B1

PD_B0

PD_B1

STYLE_B0

STYLE_B1

A_B0[1:0]

A_B1[1:0]

Reserved

0x44: QCLK_C0

0x45: QCLK_C1

PD_C0

PD_C1

STYLE_C0

STYLE_C1

A_C0[1:0]

A_C1[1:0]

Reserved

0x54: QCLK_D

0x74

PD_D

STYLE_D

A_D[1:0]

EN_QCLK_A0 EN_QCLK_A1 EN_QCLK_A2 EN_QCLK_B0 EN_QCLK_B1 EN_QCLK_C0 EN_QCLK_C1 EN_QCLK_D

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8V79S680 Datasheet

Table 14: Channel and Clock Output Register Descriptions^a

Register Description

Default

Bit Field Name

Field Type

Description

(Binary)

Output Frequency Divider N

N_x[2:0]

Frequency Divider

000

001

010

011

100

101

110

111

÷1 (Divider bypassed and powered-down)

÷2

÷4

000

÷6

N_x[2:0]

R/W

÷8

Value: ÷1

÷12

÷16

Not defined

If N_x[2:0] = 000 (÷1), set BYP_INIT = 1 to exclude the divider from

initialization.

0 = Channel x is powered up

1 = Channel x is powered down

PD_x

PD_y

R/W

0

0 = Output QCLK_y is powered up

1 = Output QCLK_y is powered down

CLK_x Phase Delay

CLK_x[7:0] Phase Delay in units of the input period: CLK_x[7:0] ÷ f_IN(256 steps).

0000 0000

Value: 0ns

0000 0000

0000 0001

…

0ps

CLK_x[7:0]

R/W

1 ÷ f_IN

…

1111 1111

255 ÷ f_IN

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August 4, 2016

8V79S680 Datasheet

Table 14: Channel and Clock Output Register Descriptions^a

Register Description

Default

Bit Field Name

Field Type

Description

(Binary)

QCLK_y Output Amplitude

Setting for STYLE = 0 (LVDS)

Setting for STYLE = 1 (LVPECL)

Termination: 50 to VT

00

Termination: 100 across

A_y[1:0]

R/W

A[1:0] = 00: 250mV

A[1:0] = 01: 500mV

A[1:0] = 10: 750mV

A[1:0] = 11:1000mV

Value: 250mV

QCLK_y Output Format:

0

0 = Output is LVDS (requires LVDS 100 output termination)

STYLE_y

EN_y

1 = Output is LVPECL (requires LVPECL 50 output termination to the specified

recommended termination voltage)

Value: LVDS

0

QCLK_y Output Enable:

0 = QCLK_y Output is disabled at the logic low state

1 = QCLK_y Output is enabled

Value:

disabled

a. x = A, B, C, D; y = A0, A1, A2, B0, B1, C0, C1, D.

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8V79S680 Datasheet

QREF Output State Registers

The content of the QREF output registers selects the source signal of the QREF outputs, set the phase delay, the style, the amplitude, the power

state, the enable state and the output bias.

Table 15: QREF Output State Register Bit Field Locations^a

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x28: QREF_A0

0x29: QREF_A1

0x2A:QREF_A2

MUX_A0

MUX_A1

MUX_A2

REF_A0[2:0]

REF_A1[2:0]

REF_A2[2:0]

Reserved

0x38: QREF_B0

0x39: QREF_B1

MUX_B0

MUX_B1

REF_B0[2:0]

REF_B1[2:0]

Reserved

0x48: QREF_C0

0x49: QREF_C1

MUX_C0

MUX_C1

REF_C0[2:0]

REF_C1[2:0]

Reserved

0x58: QREF_D

MUX_D

REF_D[2:0]

0x2C: QREF_A0

0x2D: QREF_A1

0x2E: QREF_A2

PD_A0

PD_A1

PD_A2

nBIAS_A0

nBIAS_A1

nBIAS_A2

STYLE_A0

STYLE_A1

STYLE_A2

A_A0[1:0]

Reserved

A_A1[1:0]

A_A2[1:0]

Reserved

0x3C: QREF_B0

0x3D: QREF_B1

PD_B0

PD_B1

nBIAS_B0

nBIAS_B1

STYLE_B0

STYLE_B1

A_B0[1:0]

A_B1[1:0]

0x4C: QREF_C0

0x4D: QREF_C1

PD_C0

PD_C1

nBIAS_C0

nBIAS_C1

STYLE_C0

STYLE_C1

A_C0[1:0]

A_C1[1:0]

Reserved

0x5C: QREF_D

0x76

PD_D

nBIAS_D

STYLE_D

A_D[1:0]

EN_QREF_A0 EN_QREF_A1 EN_QREF_A2 EN_QREF_B0 EN_QREF_B1EN_QREF_C0EN_QREF_C1 EN_QCLK_D

a. r = A0, A1, A2, B0, B1, C0, C1, D.

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8V79S680 Datasheet

Table 16: QREF Output State Register Descriptions^a

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

1

0 = QREF_r output signal source is the channel’s clock signal

MUX_r

R/W

1 = QREF_r output signal source is the centrally generated SYSREF signal

Value: QREF

= SYSREF

SYSREF Phase Delay:

QREF_r delay = REF_r[2:0] · T_DCB.

Delay values for f_DCO= 983.04MHz. Delay values are a function of T_DCB.

QREF_r delay in ps for a DLC[1:0] setting of:

REF_r[2:0]

000

00

01

10

0

11

REF_r[2:0]

R/W

000

001

010

…

0

Value: 0ps

131

262

…

262

524

…

393

786

…

524

1048

…

111

917

1834

2751

3668

QREF_r Output Bias Voltage:

Individual QREF_r output LVDS output bias operation. Not applicable to QREF_r outputs

set to LVPECL mode.

0 = Normal operation

1 = Output is biased to the LVDS cross-point voltage if BIAS_TYPE (register 0x19, bit 7)

is set to 1. Bit has no effect if BIAS_TYPE = 0.

BIAS_TYPE nBIAS_r

QREF_r output operation if set to LVDS.

QREF_r outputs are initially logic low (QREF_r = L,

nQREF_r = H) and will start switching on the first rising

edge of the REF input. Use in DC-coupled applications.

0

1

nBIAS_r

R/W

0

Disabled with static low/high levels. During a SYSREF

event, the output remains at static low levels (QREF_r = L,

nQREF_r = H).

Both QREF_r and nQREF_r outputs are initially set to the

LVDS crosspoint level (VOS) and will start switching on the

first rising edge of the REF input. Use in AC-coupled

applications.

1

0

1

Output is statically set to the LVDS crosspoint voltage.

During a SYSREF event, the output remains at the LVDS

crosspoint level (VOS).

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8V79S680 Datasheet

Table 16: QREF Output State Register Descriptions^a

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

QREF_r Output Amplitude

Setting for STYLE = 0 (LVDS)

Setting for STYLE = 1 (LVPECL)

Termination: 50 to VT

00

Termination: 100 across

A_r[1:0]

R/W

A[1:0] = 00: 250mV

A[1:0] = 01: 500mV

A[1:0] = 10: 750mV

A[1:0] = 11:1000mV

Value:

250mV

QREF_r Output Power Down:

0

PD_r

STYLE_r

EN_r

R/W

0 = Output is powered up

Value:

Powered up

1 = Output is powered down. STYLE, EN and A[1:0] settings have no effect

QREF_r Output Format:

0

0 = Output is LVDS (requires LVDS 100 output termination)

Value: LVDS

0

1 = Output is LVPECL (requires LVPECL 50 output termination of to the specified

recommended termination voltage)

QREF_r Output Enable:

0 = Output is disabled at the logic low state

1 = Output is enabled

Value:

Disabled

a. r = A0, A1, A2, B0, B1, C0, C1, D.

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8V79S680 Datasheet

SYSREF Control Registers

Table 17: SYSREF Control Register Bit Field Locations

Bit Field Location

Register Address

D7

D6

D5

D4

D3

D2

D1

D0

0x18

PD_S

Reserved

M_DCB[8]

0x19

0x1A

0x1B

BIAS_TYPE

DLC[1:0

Reserved

M_DCB[7:0]

P_DCB[6:0]

Reserved

Table 18: SYSREF Control Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

1

SYSREF Global Power-down:

PD_S

R/W

Value:

Powered

down

0 = SYSREF functional blocks are powered-up

1 = SYSREF functional blocks are powered-down

SYSREF Output Voltage Bias:

Global to all QREF_r outputs bit to control the LVDS output operation. Not applicable to

QREF_r outputs set to LVPECL mode.

BIAS_TYPE nBIAS_r

QREF_r output operation if set to LVDS.

QREF_r outputs are initially logic low (QREF_r = L,

nQREF_r = H) and will start switching on the first rising

edge of the REF input. Use in DC-coupled applications.

0

1

Disabled with static low/high levels. During a SYSREF

event, the output remains at static low levels (QREF_r = L,

nQREF_r = H).

BIAS_TYPE

R/W

1

Both QREF_r and nQREF_r outputs are initially set to the

LVDS crosspoint level (VOS) and will start switching on the

first rising edge of the REF input. Use in AC-coupled

applications.

1

0

1

Output is statically set to the LVDS crosspoint voltage.

During a SYSREF event, the output remains at the LVDS

crosspoint level (VOS).

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August 4, 2016

8V79S680 Datasheet

Table 18: SYSREF Control Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

Delay Unit Multiplier:

Effective delay unit for the SYSREF outputs is (1 + DLC[1:0]) ÷ (8 · f_DCO).

DLC[1:0]

Effective SYSREF Delay Unit for f_DCO= 983.04MHz

00

01

10

11

131ps

262ps

393ps

524ps

DLC[1:0]

R/W

Value: 131ps

0 0000 1000

Value: 8

Delay Calibration Block (DCB) DCO feedback divider. Set in conjunction with f_INand

P_DCB to achieve a DCO frequency of 983.04±20MHz: f_DCO= f_IN÷ P_DCB· M_DCB.

M_DCB[8:0]

P_DCB[6:0]

R/W

000 1000 Delay Calibration Block (DCB) DCO input divider. Set in conjunction with f_INand M_DCB

to achieve DCO frequency of 983.04±20MHz: f_DCO= f_IN÷ P_DCB· M_DCB. DCO phase

Value: 8 detector frequency should not exceed 200MHz.

26

August 4, 2016

8V79S680 Datasheet

General Control Registers

Table 19: General Control Register Bit Field Locations

Bit Field Location

D4

Register Address

D7

D6

D5

D3

D2

D1

D0

0x6C

Reserved

DAC_CODE[14:8]

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

DAC_CODE[7:0]

Reserved

INIT_CLK

DCB_CAL

PB_CAL

Reserved

PBIAS[5:0]

Reserved

BYP_INIT

Reserved

CPOL

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August 4, 2016

8V79S680 Datasheet

Table 20: General Control Register Descriptions

Register Description

Default

(Binary)

Bit Field Name

Field Type

Description

DAC_CODE is the result of the internal DCB calibration routine. Trigger calibration by

setting the DCB_CAL bit.

DAC_CODE[14:0]

PBIAS[5:0]

R only

X

BIAS level.

Clock divider and phase clock phase delay initialization.

W only

Set INIT_CLK = 1 to initialize N_x divider and CLK_x clock phase delay functions.

Required as part of the startup procedure and after each change of a clock divider or

clock phase delay value.

INIT_CLK

PB_CAL

X

Auto-Clear

Precision Bias Calibration:

Set PB_CAL to 1 starts the auto-calibration of an internal precision bias current source.

The bias current is used as reference for outputs configured as LVDS. This bit will

auto-clear after the calibration completed. Required to set as part of the startup

procedure.

W only

Auto-Clear

DCB Calibration:

Setting this bit to 1 will begin the auto-calibration of the DCB. The DCB provides a

reference for the SYSREF delay circuits. This bit will auto-clear. This bit should be set as

part of the startup procedure. The result of the calibration routine is stored in the

DAC_CODE register.

W only

DCB_CAL

X

Auto-Clear

Bypass Clock Frequency Divide Initializer:

0 = The clock dividers N_A-Dare initialized when INIT_CLK = 1

BYP_INIT

CPOL

R/W

1

0

1 = The clock dividers N_A-Dare excluded from the initialization. This setting is only

applicable to N_A-Ddividers = ÷1 and should be used to achieve output phase alignment

across multiple devices.

SPI Read Operation SCLK Polarity:

0 = Data bits on MISO are output at the falling edge of SCLK edge.

1 = Data bits on MISO are output at the rising edge of SCLK edge.

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August 4, 2016

8V79S680 Datasheet

Electrical Characteristics

Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.

Functional operation of the 8V79S680 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device

reliability.

Table 21: Absolute Maximum Ratings

Item

Rating

Supply Voltage, V_{DD_V}

Inputs

3.6V

-0.5V to V_{DD_V}+ 0.5V

Outputs, V_O(LVCMOS)

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Outputs, I_O(LVDS)

Continuous Current

Surge Current

50mA

100mA

Input termination current, I_VT

±35mA

Operating Junction Temperature, T_J

125C

Storage Temperature, T_STG

ESD - Human Body Model^a

-65C to 150C

2000V

ESD - Charged Device Model^a

500V

a. According to JEDEC JS-001-2012/JESD22-C101.

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August 4, 2016

8V79S680 Datasheet

Pin Characteristics

Table 22: Pin Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C

Symbol

C_IN

Parameter

Input Capacitance

Test Conditions

Minimum

Typical

Maximum

Units

2

4

pF

k



R_PD

Input Pull-Down Resistor

Input Pull-Up Resistor

SCLK

nCS

51

25

R_PU

R_OUT

LVCMOS Output Impedance

SDAT (when output)

DC Characteristics

Table 23: Power Supply DC Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^a

Symbol

V_{DD_V}

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Core Supply Voltage

3.135

3.3

3.465

V

QCLK_y and QREF_r set to LVDS,

750mV amplitude, terminated 100,

Nx dividers set to ÷1

I

_DD(Total) Power Supply Current

705

mA

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

Table 24: Typical Power Supply Current Characteristics, V_{DD_V}= 3.3V, T_A= 25°C^a

Test Case

Symbol

Supply Pin Current

Unit

1

2

3

4

5

6

Style

LVPECL

On

LVPECL

On

LVDS

On

LVDS

On

LVDS

On

LVDS

On

QCLK_y

QREF_r

State

Amplitude

Style

500

LVDS

Off

750

LVDS

Off

500

LVDS

Off

500

750

mV

LVDS

On

LVDS

On

LVDS

On

State

Amplitude

–

250

500

mV

mA

I_{DD_CA}

Current through V_{DD_QCLKA}pin(s)

Current through V_{DD_QREFA01}pin(s)

Current through V_{DD_QREFA2}pin(s)

Current through V_{DD_QCLKB}pin(s)

Current through V_{DD_QREFB}pin(s)

Current through V_{DD_QCLKC}pin(s)

Current through V_{DD_QREFC}pin(s)

Current through V_{DD_QCLKD}pin(s)

109.6

1.5

127.3

1.5

73.0

1.5

73.0

27.0

13.5

48.0

27.0

49.0

27.0

29.5

95.0

26.9

13.5

63.0

27.0

63.0

27.0

36.4

95.0

43.0

20.5

63.0

43.0

63.0

43.0

36.4

I_{DD_RA01}

I_{DD_RA2}

I_{DD_CB}

I_{DD_RB}

I_{DD_CC}

I_{DD_RC}

I_{DD_CD}

0.8

0.7

0.8

72.4

1.5

83.6

1.5

48.0

1.5

76.2

1.5

87.7

1.5

49.3

1.5

43.8

49.6

29.5

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August 4, 2016

8V79S680 Datasheet

Table 24: Typical Power Supply Current Characteristics, V_{DD_V}= 3.3V, T_A= 25°C^a

Test Case

Symbol

I_{DD_RD}

Supply Pin Current

Unit

1

2

3

4

5

6

Current through V_{DD_QREFD}pin(s)

Current through V_{DD_CLK}pin(s)

Current through V_{DD_REF}pin(s)

Current through V_{DD_SPI}pin(s)

Total Device Power Consumption

0.8

40.3

9.8

0.8

40.2

9.8

0.8

39.8

9.7

13.6

40.2

13.6

40.2

20.7

40.1

mA

W

I_{DD_CLK}

I_{DD_REF}

I_{DD_SPI}

P_TOT

52.8

53.5

54.2

12.8

1.223

1.403

13.1

1.377

1.557

12.9

0.885

13.3

13.4

1.365

1.559

1.766

P_{TOT, SYS}Total System Power Consumption^b

W

a. f_IN(input) = 983.04MHz, f_SYSREF= 7.68MHz. Supply current is independent on the output frequency. QCLK_y outputs terminated according

to amplitude settings. QREF_r outputs unterminated when SYSREF is turned off.

b. Includes total device power consumption and the power dissipated in external output termination components.

Table 25: LVCMOS (JESD8-7A, 1.8V) DC Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^{a b}

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Positive-going

input threshold

voltage

V_T+

0.660

1.365

V

Negative-going

input threshold

voltage

V_T-

0.495

0.165

1.170

V

SCLK, nCS, SDAT

Hysteresis

Voltage

V_H

V

_T+– V_T-

0.780

150

V

µA

V

Input

High Current

I_IH

V_{DD_V}= 3.3V, V_IN= 1.8V

Input

Low Current

I_IL

V

_{DD_V}= 3.465V, V_IN= 0V

I_OH= -4mA

-150

1.4

Output

High Voltage

V_OH

V_OL

SDAT (when output)

Output

Low Voltage

I_OL= 4mA

0.45

V

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

b. Table is valid for the SPI interface pins nCS, SCLK and SDAT. SPI inputs have hysteresis.

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August 4, 2016

8V79S680 Datasheet

Table 26: Differential Input DC Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^a

Symbol

Parameter

CLK, nCLK

Test Conditions

Minimum

Typical

Maximum

Units

R_IN

Input Resistance

43.5

50

56.5



REF, nREF

Differential Input

Resistance

CLK, nCLK

REF, nREF

R_{IN_DIFF}

87

100

113



a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

Table 27: LVPECL DC Characteristics (QCLK_y, QREF_r, STYLE = 1), V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^a

Symbol

V_OH

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Output High Voltage^b

Any Amplitude Setting

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

V_{DD_V}- 1.10 V_{DD_V}- 0.85 V_{DD_V}- 0.65

V_{DD_V}- 1.30 V_{DD_V}- 1.15 V_{DD_V}- 1.10

V_{DD_V}- 1.55 V_{DD_V}- 1.40 V_{DD_V}- 1.25

V

V_OL

Output Low Voltage^b

V

_{DD_V}- 1.80 V_{DD_V}- 1.65 V_{DD_V}- 1.50

V_{DD_V}- 2.10 V_{DD_V}- 1.90 V_{DD_V}- 1.75

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

b. Outputs terminated with 50 to V_{DD_V}– 1.5V (250mV amplitude setting), V_{DD_V}– 1.75V (500mV amplitude setting), V_{DD_V}– 2.0V (750mV

amplitude setting), V_{DD_V}– 2.25V (1000mV amplitude setting).V_{DD_V.}

Table 28: LVDS DC Characteristics (QCLK_y, QREF_r, STYLE = 0), V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^{a b}

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

2.00

1.80

1.70

1.55

2.40

2.23

2.08

1.93

2.80

2.60

2.50

2.35

50

V

V_OS

Offset Voltage^c

V

V_OS

V_OSMagnitude Change

mV

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

b. Outputs are terminated 100

c. V_OSchanges with V_{DD_V.}

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August 4, 2016

8V79S680 Datasheet

AC Characteristics

Table 29: AC Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^a

Symbol

f_IN

Parameter

Test Conditions

Minimum Typical

Maximum

Units

CLK, nCLK

0

983.04

3000

100

MHz

Input Frequency^b

REF, nREF

CLK, nCLK

REF, nREF

Input Voltage

Amplitude^c

V_IN

0.15

0.3

1.2

2.4

V

Differential Input

CLK, nCLK

REF, nREF

V_{DIFF_IN}Voltage

Amplitude^{c d}

V_CMR

f_OUT

Common Mode Input Voltage

Output Frequency

1.125

V_{DD_V}– (V_IN/ 2)

V

QCLK, QREF (Clock), N = ÷1 to ÷16

QREF (SYSREF)

0

983.04

3000÷N

100

MHz

%

QCLK, QREF (Clock), f_CLK≤ 2500MHz

45

50

55

QCLK, QREF (Clock),

2500MHz < f_CLK≤ 3000MHz

odc

Output Duty Cycle^e

43

45

57

%

QREF (SYSREF at 7.68MHz)

QCLK, QREF (LVPECL), 20% to 80%

QCLK, QREF (LVDS), 20% to 80%

QREF (SYSREF, LVDS), 20% to 80%

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

250mV Amplitude Setting

500mV Amplitude Setting

750mV Amplitude Setting

1000mV Amplitude Setting

55

%

250

ps

t

_R/ t_F

Output Rise/Fall Time

250

ps

250

ps

260

430

675

950

520

860

1350

1900

190

400

625

800

380

800

1250

1600

300

532

320

mV

650

LVPECL Output Voltage Swing,

Peak-to-peak, 983.04MHz

785

920

981

1150

640

f

V_O(PP)

600

LVPECL Differential Output

Voltage Swing, Peak-to-peak,

983.04MHz

1064

1570

1962

240

1300

1840

2300

280

500

570

LVDS Output Voltage Swing,

Peak-to-peak, 983.04MHz

750

840

1000

480

1160

560

g

V_O(PP)

LVDS Differential Output

Voltage Swing, Peak-to-peak,

983.04MHz

1000

1500

2000

1140

1680

2320

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August 4, 2016

8V79S680 Datasheet

Table 29: AC Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C^a

Symbol

Parameter

Test Conditions

QCLK (same N divider)^j

Minimum Typical

Maximum

Units

100

190

375

850

1050

ps

QCLK (any N divider, incident rising edge)

QREF (Clock)

Output Skew; NOTE^{h i}

All delays set to 0

tsk(o)

QREF (SYSREF)

QCLK to QREF (QREF as clock output)^j

CLK to any QCLK^j

Part-to-part skew

All delays set to 0

tsk(pp)

REF to any QREF

CLK to QCLK_y^j

CLK to QCLK_y (divider bypass)^j

300

Propagation Delay^j

t_PD

300

700

550

900

All delay circuits set to 0

REF to QREF_r (REF_y = 0)

Propagation delay variation

between the clock input and

any QCLK_y output

t_PD

CLK to QCLK_y^j

-100

+100

ps

f_{QCLK_y}= 983.04MHz^k

QCLK-QCLK and QREF-QREF f_{QCLK_y}= 491.52MHz^k

60

65

70

dB

Output isolation between any

outputs

f_{QCLK_y}= 245.76MHz^k

Output isolation between any f_{QCLK_y}= 983.04MHz, 491.52MHz,

50

dB

QREF/QCLK outputs

245.76MHz; f_{QREF_r}= 7.68MHz

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

b. The CLK, nCLK input supports 0Hz if the applied static signal has a minimum amplitude as specified by V_IN,V_{DIFF_IN.}

For REF, nREF interfaces at 0Hz, See “CLK, nCLK and REF, nREF Interface in JESD204B Applications”.

c. V_ILshould not be less than -0.3V and V_IHshould not be greater than V_{DD_V.}

d. Common Mode Input Voltage is defined as the cross-point voltage.

e. Input = 50% duty cycle.

f. LVPECL outputs terminated with 50 to V_T= V_{DD_V}– 1.5V (250mV amplitude setting), V_{DD_V}– 1.75V (500mV amplitude setting),

V_{DD_V}– 2.0V (750mV amplitude setting), V_{DD_V}– 2.25V (1000mV amplitude setting).

g. LVDS outputs terminated 100 across Q, nQ.

h. This parameter is defined in accordance with JEDEC standard 65.

i. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points

j. All frequency dividers N are in ÷1, ÷2, ÷4 or ÷8; output amplitude setting 750mV.

k. Output amplitudes set to 500mV or 750mV.

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August 4, 2016

8V79S680 Datasheet

Table 30: DCB and Phase Delay Characteristics, V_{DD_V}= 3.3V ± 5%, T_A= -40°C to +85°C ^a

Symbol

Parameter

DCO Lock Range

Test Conditions

Minimum Typical Maximum Units

f_DCO

963.04

115

230

345

460

113

226

339

452

112

224

336

448

983.04

131

262

393

524

134

268

402

536

128

256

384

512

1017

1003.04

150

300

450

600

152

304

456

608

142

284

426

568

MHz

ps

DLC = 1 (DLC[1:0] = 00)

DLC = 2 (DLC[1:0] = 01)

DLC = 3 (DLC[1:0] = 10)

DLC = 4 (DLC[1:0] = 11)

DLC = 1 (DLC[1:0] = 00)

DLC = 2 (DLC[1:0] = 01)

DLC = 3 (DLC[1:0] = 10)

DLC = 4 (DLC[1:0] = 11)

DLC = 1 (DLC[1:0] = 00)

DLC = 2 (DLC[1:0] = 01)

DLC = 3 (DLC[1:0] = 10)

DLC = 4 (DLC[1:0] = 11)

ps

f_DCO= 983.04MHz

ps

f

_DCO= 963.04MHz

T_DCB

REF_r Delay Unit Range

(min DCO frequency)

ps

f

_DCO= 1003.04MHz

(max DCO frequency)

ps

b

T_IN

CLK_x Delay Unit

f_IN= 983.04MHz

ps

f_1,f₂

DCO Phase Detector Frequency

200

+30

MHz

REF_r delay unit

variation (deviation

from nominal,

-30

-20

0

ps

DLC[1:0] = 00)

t_D

Delay unit variation

CLK_y delay unit

variation (deviation

from nominal)

+20

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

b. CLK_x clock channel delay unit is equal to 1 ÷ f_IN.

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August 4, 2016

8V79S680 Datasheet

Additive Clock Phase Noise Characteristics

The 8V79S680 is a buffer device, it does not filter the phase noise on the input clock source. Phase noise caused by noise sources within the device

can add to the input signal noise, resulting in an increased noise on the outputs (additive phase noise). Phase noise from within the part is not

correlated with the noise on the input, therefore the root-sum-square method must be used to calculate the output phase noise:

_OUT²= _IN² _DEVICE². As a consequence, at frequency offsets where the input phase noise _INis higher than internal noise sources, the effect

of additive phase noise is not measurable.

Simulations of the device phase noise performance are done with an ideal input source, however, simulation models may not account for all possible

internal noise sources. Table 31 shows the simulation results for the 8V79S680 buffer with an ideal input source. Table 33 shows output phase noise

measured with a low-noise input source, with one column for the measured data and a second column which de-rates the measured data by a factor

to model the process variation. Table 33 shows that the input phase noise is the dominating factor in the measured data up to an offset of 100kHz.

Above 100kHz, the noise floor of the device dominates the characteristics.

Table 31: Additive Clock Phase Noise Characteristics (Simulation^a), V_{DD_V}= 3.3V ± 5%^b

Symbol

_N(1k)

Parameter

Test Conditions

1kHz offset from Carrier

10kHz offset from Carrier

25°C

85°C, Worst Case

Units

-146.2

-156.6

-161.9

-162.4

-141.6

-152.7

-159.2

-159.8

-159.9

-134.5

-141.4

-155.8

-157.2

-145.5

-155.3

-159.6

-160.5

-141.6

-151.6

-157.0

-158.1

-158.2

-132.0

-141.8

-152.6

-155.3

-155.8

dBc/Hz

_N(10k)

_N(100k)

_N(1M)

_N(10M)

_N(1k)

245.76MHz 100kHz offset from Carrier

1MHz offset from Carrier

10MHz offset from Carrier and Noise Floor

1kHz offset from Carrier

10kHz offset from Carrier

_N(10k)

_N(100k)

_N(1M)

_N(10M)

_N(1k)

QCLK_y

491.52MHz 100kHz offset from Carrier

1MHz offset from Carrier

Phase Noise

10MHz offset from Carrier and Noise Floor

1kHz offset from Carrier

10kHz offset from Carrier

_N(10k)

_N(100k)

_N(1M)

_N(10M)

983.04MHz 100kHz offset from Carrier

1MHz offset from Carrier

10MHz offset from Carrier and Noise Floor

a. Ideal input signal: rectangular clock signal with a slew rate of 5V/ns and without phase noise.

b. Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase

noise specifications are applicable for all outputs active, Nx not equal, process and voltage variations included.

36

August 4, 2016

8V79S680 Datasheet

Figure 8: Additive Clock Phase Noise Characteristics (85°C, Worst Case Simulation Model)

-100.00

-110.00

-120.00

-130.00

983.04MHz

-140.00

491.52MHz

-150.00

-160.00

245.76MHz

-170.00

-180.00

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

Offset (Hz)

37

August 4, 2016

8V79S680 Datasheet

Table 32: Additive Clock Phase Noise Characteristics (Measured), V

= 3.3V ± 5%, T_A= -40°C to +85°C ^{a b}

DD_V

Symbol

Parameter

Test Conditions

1kHz offset from Carrier

10kHz offset from Carrier

Measured^c

De-Rated^d

Units

 (1k)

-141.4

-151.7

-157.8

-158.6

-158.8

-135.3

-145.8

-154.2

-157.2

-157.6

-131.3

-141.2

-149.6

-154.5

-155.3

-137.2

-149.5

-155.5

-156.2

-156.3

-128.4

-140.5

-149.5

-155.4

-156.3

-125.7

-138.5

-146.5

-152.2

-152.5

100

dBc/Hz

fs

N

 (10k)

N

 (100k)

245.76MHz 100kHz offset from Carrier

1MHz offset from Carrier

N

 (1M)

N

 (10M)

10MHz offset from Carrier and Noise Floor

N

 (1k)

1kHz offset from Carrier

10kHz offset from Carrier

N

 (10k)

N

QCLK

 (100k)

491.52MHz 100kHz offset from Carrier

1MHz offset from Carrier

N

Phase Noise

 (1M)

N

 (10M)

10MHz offset from Carrier and Noise Floor

N

 (1k)

1kHz offset from Carrier

10kHz offset from Carrier

N

 (10k)

N

 (100k)

983.04MHz 100kHz offset from Carrier

1MHz offset from Carrier

N

 (1M)

N

 (10M)

10MHz offset from Carrier and Noise Floor

N

Integration Range: 1kHz - 61.44MHz

Integration Range: 12kHz - 20MHz

Clock RMS Phase Jitter

(Random)

tjit(Ø)

100

fs

a. Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase

noise specifications are applicable for all outputs active, Nx not equal.

b. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

c. Measured results at the max. temperature of 85°C using an input source with a phase noise characteristics of:

• 245.76MHz: -143.7dBc/Hz (1kHz offset), -152.5dBc/Hz (10kHz), -160.8dBc/Hz (100kHz), -172.6dBc/Hz (1MHz), -179.5dBc/Hz (10MHz).

• 491.52MHz: -137.7dBc/Hz (1kHz offset), -147.4dBc/Hz (10kHz), -156.1dBc/Hz (100kHz), -167.6dBc/Hz (1MHz), -170.1dBc/Hz (10MHz).

• 983.04MHz: -132.5dBc/Hz (1kHz offset), -141.4dBc/Hz (10kHz), -149.9dBc/Hz (100kHz), -161.4dBc/Hz (1MHz), -164.2dBc/Hz (10MHz).

d. De-rating factor applied to the characterized data at 85°C to account for worst-case process variation.

38

August 4, 2016

8V79S680 Datasheet

Figure 9: Additive Clock Phase Noise Characteristics (Measured), f_CLK= 245.76MHz

-100.00

-110.00

-120.00

-130.00

-140.00

Characterized and de-rated for process variation

Characterized (high temperature)

-150.00

-160.00

Low phase noise input source

-170.00

-180.00

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

Offset (Hz)

39

August 4, 2016

8V79S680 Datasheet

Figure 10: Additive Clock Phase Noise Characteristics (Measured), f_CLK= 491.52MHz

-100.00

-110.00

-120.00

-130.00

Characterized and de-rated for process variation

-140.00

Characterized (high temperature)

-150.00

-160.00

Low phase noise input source

-170.00

-180.00

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

Offset (Hz)

40

August 4, 2016

8V79S680 Datasheet

Figure 11: Additive Clock Phase Noise Characteristics (Measured), f_CLK= 983.04MHz

-100.00

-110.00

-120.00

-130.00

Characterized and de-rated for process variation

-140.00

Characterized (high temperature)

-150.00

-160.00

-170.00

-180.00

Low phase noise input source

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

Offset (Hz)

Symbol

Parameter

Test Conditions

Typical

Units

 (1k)

1kHz offset from Carrier

-146

-152.5

-156

dBc/Hz

N

 (10k)

10kHz offset from Carrier

100kHz offset from Carrier

1MHz offset from Carrier

1kHz offset from Carrier

10kHz offset from Carrier

100kHz offset from Carrier

1MHz offset from Carrier

N

a

c

15.36MHz

30.72MHz

 (100k)

N

 (1M)

-156

N

QREF_r

Phase Noise

 (1k)

-147.5

-153.5

-155.5

N

 (10k)

N

 (100k)

N

 (1M)

N

a. Measured results with DLC[1:0] = 00 and REF_r = 3.

41

August 4, 2016

8V79S680 Datasheet

Application Information

Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)

Figure 12 shows an example termination for the QCLK_y, QREF_r LVDS outputs. In this example, the characteristic transmission line impedance is

50. The termination resistor R (100) is matched to the line impedance. The termination resistor must be placed at the line end. No external

termination resistor is required if R is an internal part of the receiver circuit. The LVDS termination in Figure 12 is applicable for any output amplitude

setting specified in Table 7.

Figure 12: LVDS (STYLE = 0) Output Termination

V

DD_V

T = 50

R = 100

LVDS

AC Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)

Figure 13 and Figure 14 show example AC terminations for the QCLK_y, QREF_r LVDS outputs. In the examples, the characteristic

transmission line impedance is 50. In Figure 13, the termination resistor R (100) is placed at the line end. No external termination resistor is

required if R is an internal part of the receiver circuit, which is shown in Figure 14. The LVDS terminations in both Figure 13 and Figure 14 are

applicable for any output amplitude setting specified in Table 7. The receiver input should be re-biased according to its common mode range

specifications.

Figure 13: LVDS (STYLE = 0) AC Output Termination

V_BIAS

V

DD_V

0.1µF

T = 50

R = 100

LVDS

Figure 14: LVDS (STYLE = 0) AC Output Termination

V

DD_V

0.1µF

T = 50

LVDS

R = 100

42

August 4, 2016

8V79S680 Datasheet

Termination for QCLK_y, QREF_r LVPECL Outputs (STYLE = 1)

Figure 15 shows an example termination for the QCLK_y, QREF_r LVPECL outputs. In this example, the characteristic transmission line impedance

is 50 The R1 (50) and R2 (50) resistors are matched load terminations. The output is terminated to the termination voltage V The V must

.

T

be set according to the output amplitude setting defined in Table 7. The termination resistors must be placed close at the line end.

Figure 15: LVPECL (STYLE = 1) Output Termination

V = V

- 1.50V (250 mV Amplitude)

- 1.75V (500 mV Amplitude)

- 2.00V (750mV Amplitude)

- 2.25V (1000mV Amplitude)

T

DD_V

V = V

T

V = V

T

V = V

V

T

DD_V

R = 50

2

1

T = 50

LVPECL

43

August 4, 2016

8V79S680 Datasheet

Package Exposed Pad Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed

Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in

Figure 16. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the

land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint,

thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground

through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the

minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is

recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to

0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result

in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed

heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Lead-frame Base Package, Amkor Technology.

Figure 16: Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

44

August 4, 2016

8V79S680 Datasheet

Thermal Characteristics

Table 33: Thermal Resistance for 64 VFQFN-P Package^a

Symbol

Thermal Parameter

Condition

Value

Unit

0 m/s air flow

1 m/s air flow

2 m/s air flow

3 m/s air flow

4 m/s air flow

5 m/s air flow

22.76

19.25

17.70

16.87

16.37

16.03

14.33

1.1

°C/W

_JA

Junction to ambient



Junction to case

Junction to board

JC

_JB

a. Standard JEDEC 2S2P multilayer PCB.

Case Temperature Considerations

This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air. The printed

circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature. The device

package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to the PCB where most of the heat

escapes from the bottom exposed pad. For this type of application, it is recommended to use the junction-to-board thermal characterization parameter



(Psi-JB) to calculate the junction temperature (T ) and ensure it does not exceed the maximum allowed operating junction temperature in the

JB

J

Absolute Maximum Rating table.

The junction-to-board thermal characterization parameter,  is calculated using the following equation:

JB,

T = T +  x P where:

J

CB

JB

D,

o

T_J= Junction temperature at steady state condition in ( C)

o

T

_CB= Case temperature (Bottom) at steady state condition in ( C)



_JB= Thermal characterization parameter to report the difference between junction temperature and the temperature of the board

measured at the top surface of the board

P_D= power dissipation (W) in desired operating configuration

T

J

T

CB

The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the IC to

the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case temperature (T ). A

CB

good connection ensures that temperature at the exposed pad (T ) and the board temperature (T ) are relatively the same. An improper connection

CB

B

can lead to increased junction temperature, increased power consumption and decreased electrical performance. In addition, there could be

long-term reliability issues and increased failure rate.

45

August 4, 2016

8V79S680 Datasheet

Example Calculation for Junction Temperature (T ): T = T

+  x P

JB D

J

CB

Table 34: Thermal Resistance for 64 VFQFN-P package^a

Package type

Body size (mm)

64 VFQFN-P

9mmx9mmx0.85mm

6.00mm x 6.00mm

8x8 Matrix

ePad size (mm)

Thermal Via



1.1 C/W

JB

CB

D

o

T

P

85 C

b

1.766 W

a. Standard JEDEC 2S2P multilayer PCB.

b. See Table 24, test case 6.

o

For the variables above, the junction temperature is T = T +  x P = 85 C + 1.1 C/W x 1.766W = 86.9 C. Since this operating junction

J

CB

JB

D

o

temperature is below the maximum operating junction temperature of 125 C, there are no long term reliability concerns. In addition, since the junction

temperature at which the device was characterized using forced convection is 87.6 C, this device can function without the degradation of the specified

o

AC or DC parameters.

46

August 4, 2016

8V79S680 Datasheet

Package Drawings

Figure 17: Package Drawings

47

August 4, 2016

8V79S680 Datasheet

Recommended Land Pattern

Figure 18: Recommended Land Pattern

48

August 4, 2016

8V79S680 Datasheet

Ordering Information

Orderable Part Number

Package

MSL Rating

Shipping Packaging

Temperature

8V79S680NLGI

8V79S680NLGI8

3

Tray

RoHS 6/6 64 VFQFN-P

-40°C to +85°C

Tape and Reel

Marking Diagram

IDT

8V79S680NLGI

#YYWW$

LOT C00

49

August 4, 2016

8V79S680 Datasheet

Revision History

Date

Description of Change

8/4/16

Initial Final datasheet.

50

August 4, 2016

8V79S680 Datasheet

Glossary

Abbreviation

Description

Index x

Index y

Index r

Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D.

Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D.

Denominates a QREF output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D.

Denominates voltage supply pins. Range: V

V

DD_QCLKA, DD_QREFA01, DD_QREFA2, DD_QCLKB, DD_QREFB,

V

DD_V

V

, V

V

DD_QCLKC DD_QREFC, DD_QCLKD, DD_QREFD, DD_CLK, DD_REF.

[...]

Index brackets describe a group associated with a logical function or a bank of outputs.

List of discrete values.

{…}

51

August 4, 2016

8V79S680 Datasheet

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.idt.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications

and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein

is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,

or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

IDT or their respective third party owners.

^{For datasheet type definitions and a glossary of common terms, visit}www.idt.com/go/glossary.


型号：	8V79S680NLGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	JESD204B Compliant Fanout Buffer and Divider
文件：	总52页 (文件大小：736K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V79S680NLGI [IDT]

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