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8V79S680_17 [IDT]

JESD204B-Compliant Fanout Buffer and Divider;
8V79S680_17
型号： 8V79S680_17
厂家： INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述：

JESD204B-Compliant Fanout Buffer and Divider
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JESD204B-Compliant Fanout Buffer  
and Divider  
8V79S680  
Datasheet  
Description  
Typical Applications  
The 8V79S680 is a fully integrated, clock and SYSREF signal fanout  
buffer for JESD204B applications. It is designed as a  
▪ JESD204B low phase noise clock and SYSREF signal distribution  
▪ Supports JESD204 subclass 0, 1 and 2  
▪ Clock distribution device for jitter-sensitive ADC and DAC circuits  
▪ Wireless infrastructure  
high-performance clock and converter synchronization solution for  
wireless basestation radio equipment boards with JESD204B  
subclass 0, 1, and 2 compliance. The main function of the device is  
the distribution and fanout of high-frequency clocks and  
▪ Radar and imaging  
low-frequency system reference signals generated by a JESB204B  
clock generator such as the IDT 8V19N480, extending its fanout  
capabilities and providing additional phase-delay.  
▪ Instrumentation and medical  
Features  
▪ Supports high-speed, low phase noise converter clocks  
The 8V79S680 is optimized to deliver very low phase noise clocks  
and precise, phase-adjustable SYSREF synchronization signals as  
required in GSM, WCDMA, LTE, and LTE-A radio board  
implementations. Low-skew outputs, low device-to-device skew  
characteristics and fast output rise/fall times help the system design  
to achieve deterministic clock and SYSREF phase relationship  
across devices.  
▪ Distribution, fanout, phase-delay of clock and SYSREF signals  
▪ Very low output noise floor: -158.8dBc/Hz noise floor  
(245.76MHz)  
▪ Supports clock frequencies up to 3GHz, including clock output  
frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and  
122.88MHz  
The device distributes the input clock (CLK) and JESD204B  
SYSREF signals (REF) to four fanout channels. In each channel,  
both input clock and SYSREF signals are fanned-out to multiple  
clock (QCLK) and SYSREF (QREF) outputs. Clock signals can be  
frequency-divided in each channel. Configurable phase-delay  
circuits are available for both clock and SYSREF signals. The  
propagation delays in all signal paths are fully deterministic to  
support fixed phase relationships between clock and SYSREF  
signals within one device. The clock divider can be bypassed for  
low-latency clock paths. The 8V79S680 facilitates synchronization  
between frequency dividers within the device and across multiple  
devices, removing phase ambiguity introduced in dividers between  
power and configuration cycles.  
▪ Four output channels with a total of 16 differential outputs,  
organized in:  
— 8 dedicated clock outputs  
— 8 outputs configurable as SYSREF outputs with individual  
phase delay stages, or configurable as additional clock  
outputs  
▪ Each channel contains:  
— frequency dividers: ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16  
— clock phase delay circuits  
▪ Clock phase delay circuits  
— Clock: delay unit is the clock period; 256 steps  
Each channel supports clock frequencies up to 3GHz. In an  
alternative configuration (e.g., JESD204B subclass 0 and 2) the  
SYSREF (QREF) outputs can be configured as regular clock outputs  
adding additional clock fanout to the device.  
— SYSREF: Configurable precision phase delay circuits: 8 steps  
of 131ps, 262ps, 393ps, or 524ps  
▪ Flexible differential outputs:  
— LVDS/LVPECL configurable  
— Amplitude configurable  
All outputs are very flexible in amplitude configuration, output signal  
termination, and allow both DC and AC coupling. Outputs can be  
disabled and powered down when not used. The SYSREF output  
pre-bias feature supports prevention of power-on glitches and  
enables AC-coupling of the system synchronization signals.  
— Power-down modes for unused outputs  
— Supports DC and AC coupling  
— QREF (SYSREF) output pre-bias feature to prevent glitches  
when turning output on or off  
The device is configured through a 3-wire SPI serial interface. The  
device is packaged in a lead-free (RoHS 6) 64-lead VFQFN  
package. The extended temperature range supports wireless  
infrastructure, telecommunication, and networking end equipment  
requirements. The 8V79S680 is a member of the high-performance  
clock family from IDT.  
▪ Supply voltage:  
— 3.3V core and signal I/O  
— 1.8V Digital control SPI I/O (3.3V-tolerant inputs)  
▪ 64-VFQFN-P package (9 x 9 x 0.85mm)  
▪ Ambient temperature range: -40°C to +85°C  
©2017 Integrated Device Technology, Inc.  
1
June 22, 2017  
8V79S680 Datasheet  
Block Diagram  
Figure 1. Block Diagram  
QCLK_A0  
nQCLK_A0  
Clock  
fIN  
QCLK_A1  
nQCLK_A1  
CLK  
nCLK  
÷NA  
CLK_A  
REF_A0  
REF_A1  
REF_A2  
2x  
50  
QCLK_A2  
nQCLK_A2  
VTC  
0
1
QREF_A0  
nQREF_A0  
MUX_A0  
MUX_A1  
MUX_A2  
0
1
QREF_A1  
nQREF_A1  
0
1
QREF_A2  
nQREF_A2  
Channel A  
QCLK_B0  
nQCLK_B0  
÷NB  
SYSREF fREF  
CLK_B  
REF_B0  
REF_B1  
REF  
nREF  
QCLK_B1  
nQCLK_B1  
2x  
50  
0
1
QREF_B0  
nQREF_B0  
MUX_B0  
MUX_B1  
VTR  
0
1
QREF_B1  
nQREF_B1  
Channel B  
fIN  
REF_r  
Delay Calibration  
Block  
QCLK_C0  
nQCLK_C0  
÷NC  
CLK_C  
REF_C0  
REF_C1  
QCLK_C1  
nQCLK_C1  
0
1
QREF_C0  
nQREF_C0  
VDD  
50k  
MUX_C0  
MUX_C1  
0
1
QREF_C1  
nQREF_C1  
nCS  
SDAT  
SCLK  
SPI  
Channel C  
Register  
File  
QCLK_D  
nQCLK_D  
÷ND  
CLK_D  
50k  
0
1
QREF_D  
nQREF_D  
MUX_D  
REF_D  
Channel D  
©2017 Integrated Device Technology, Inc.  
2
June 22, 2017  
8V79S680 Datasheet  
Pin Assignments  
Figure 2. Pin Assignments 9mmx9mmx0.85mm 64-VFQFN-P Package (Top View)  
64  
63 62  
61 60 59 58 57 56 55 54 53 52 51 50 49  
QREF_B0  
nQREF_B0  
QREF_B1  
nQREF_B1  
VDD_QREFB  
1
2
48 QREF_A2  
47 nQREFA2  
46 VDD_QREFA2  
45 VDD_QCLKA  
44 QCLK_A2  
43 nQCLK_A2  
42 QCLK_A1  
41 nQCLK_A1  
40 QCLK_A0  
39 nCLK_A0  
38 VDD_QCLKA  
37 VDD_QREFA01  
36 QREF_A1  
35 nQREF_A1  
34 QREF_A0  
33 nQREF_A0  
3
4
5
VDD_QCLKB  
6
QCLK_B0  
nQCLK_B0  
QCLK_B1  
nQCLK_B1  
VDD_QCLKB  
7
8
Exposed Pad  
(GND)  
9
10  
11  
12  
13  
14  
15  
16  
VDD_QREFC  
QREF_C0  
nQREF_C0  
QREF_C1  
nQREF_C1  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31  
32  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Pin Descriptions  
Table 1. Pin Descriptions  
Number  
Name  
Type[a]  
Description  
1,  
2
QREF_B0,  
nQREF_B0  
Differential SYSREF/clock output QREF_B0. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
3,  
4
QREF_B1,  
nQREF_B1  
Differential SYSREF/clock output QREF_B1. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
5
6
VDD_QREFB  
VDD_QCLKB  
Power  
Power  
Positive supply voltage (3.3V) for the QREF_B[1:0] outputs.  
Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.  
7,  
8
QCLK_B0,  
nQCLK_B0  
Differential clock output QCLK_B0. Configurable LVPECL/LVDS style and amplitude.  
Output  
Output  
9,  
10  
QCLK_B1,  
nQCLK_B1  
Differential clock output QCLK_B1. Configurable LVPECL/LVDS style and amplitude.  
11  
12  
VDD_QCLKB  
VDD_QREFC  
Power  
Power  
Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.  
Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.  
13,  
14  
QREF_C0,  
nQREF_C0  
Differential SYSREF/clock output QREF_C0. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
Output  
15,  
16  
QREF_C1,  
nQREF_C1  
Differential SYSREF/clock output QREF_C1. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
17  
18  
VDD_QREFC  
VDD_QCLKC  
Power  
Power  
Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.  
Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.  
19,  
20  
QCLK_C0,  
nQCLK_C0  
Differential clock output QCLK_C0. Configurable LVPECL/LVDS style and amplitude.  
Output  
Output  
21,  
22  
QCLK_C1,  
nQCLK_C1  
Differential clock output QCLK_C1. Configurable LVPECL/LVDS style and amplitude.  
23  
24  
VDD_QCLKC  
VDD_QREFD  
Power  
Power  
Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.  
Positive supply voltage (3.3V) for the QREF_D outputs.  
25,  
26  
QREF_D,  
nQREF_D  
Differential SYSREF/clock output QREF_D. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
27  
28  
VDD_QREFD  
VDD_QCLKD  
Power  
Power  
Positive supply voltage (3.3V) for the QREF_D outputs.  
Positive supply voltage (3.3V) for the QCLK_D outputs.  
29,  
30  
QCLK_D,  
nQCLK_D  
Differential clock output QCLK_D. Configurable LVPECL/LVDS style and amplitude.  
Output  
31  
32  
VDD_QCLKD  
Power  
Power  
Positive supply voltage (3.3V) for the QCLK_D outputs.  
Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.  
VDD_QREFA01  
33,  
34  
nQREF_A0,  
QREF_A0  
Differential SYSREF/clock output QREF_A0. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
35,  
36  
nQREF_A1,  
QREF_A1  
Differential SYSREF/clock output QREF_A1. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
Power  
37  
VDD_QREFA01  
Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.  
©2017 Integrated Device Technology, Inc.  
4
June 22, 2017  
8V79S680 Datasheet  
Table 1. Pin Descriptions (Cont.)  
Number  
Name  
Type[a]  
Power  
Description  
38  
VDD_QCLKA  
Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.  
39,  
40  
nQCLK_A0,  
QCLK_A0  
Differential clock output QCLK_A0. Configurable LVPECL/LVDS style and amplitude.  
Differential clock output QCLK_A1. Configurable LVPECL/LVDS style and amplitude.  
Differential clock output QCLK_A2. Configurable LVPECL/LVDS style and amplitude.  
Output  
Output  
Output  
41,  
42  
nQCLK_A1,  
QCLK_A1  
43,  
44  
nQCLK_A2,  
QCLK_A2  
45  
46  
VDD_QCLKA  
VDD_QREFA2  
Power  
Power  
Positive supply voltage (3.3V) for the QCLK_A[2:0] outputs.  
Positive supply voltage (3.3V) for the QREF_A2 output.  
47,  
48  
nQREF_A2,  
QREF_A2  
Differential SYSREF/clock output QREF_A2. LVDS style for SYSREF operation,  
configurable LVPECL/LVDS style and amplitude for clock operation.  
Output  
49  
50  
VDD_QREFA2  
VDD_REF  
Power  
Power  
Positive supply voltage (3.3V) for the QREF_A2 output.  
Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF  
REF, nREF  
SYSREF inverting and non-inverting differential input. Compatible with LVPECL and  
LVDS signals. REF and nREF are internally 50terminated to the VTR pin  
51, 52  
Input  
VTR  
Internal termination for the differential clock input REF, nREF. Both REF and nREF inputs  
are internally terminated 50to this pin. See input termination information in Application  
Information.  
53  
–
54  
55  
56  
VDD_REF  
RES_CAL  
VDD_CLK  
VTC  
Power  
Analog  
Power  
Positive supply voltage (3.3V) for the differential SYSREF input REF, nREF  
Connect a 2.8 k(1%) resistor to GND for output current calibration.  
Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.  
Internal termination for the differential clock input CLK, nCLK. Both CLK and nCLK inputs  
are internally 50terminated to the VTR pin. See input termination information in  
Application Information.  
57  
–
58, 59  
nCLK, CLK  
Device clock inverting and non-inverting differential clock input. Compatible with LVPECL  
and LVDS signals. CLK and nCLK are internally terminated to VTC through 50.  
Input  
60  
61  
VDD_CLK  
SDAT  
Power  
Positive supply voltage (3.3V) for the differential device clock input CLK, nCLK.  
Input/  
Output  
Serial Control Port SPI Mode Data Input and Output. 1.8V LVCMOS/LVTTL interface  
levels. 3.3V tolerant when input.  
SCLK  
nCS  
Serial Control Port SPI Mode Clock Input. 1.8V LVCMOS/LVTTL interface levels.  
3.3V-tolerant when input.  
62  
Input  
PD  
PU  
Serial Control Port SPI Chip Select Input. 1.8V LVCMOS/LVTTL interface levels and  
3.3V tolerant.  
63  
64  
Input  
Power  
Power  
VDD_SPI  
GND  
Positive supply voltage (3.3V) for the SPI interface.  
Exposed  
Pad (EP)  
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).  
[a] Internal pull-up (PU) and pull-down (PD) resistors are indicated in parentheses (see Table 22 for values).  
©2017 Integrated Device Technology, Inc.  
5
June 22, 2017  
8V79S680 Datasheet  
Principles of Operation  
Overview  
The 8V79S680 is a JESD204B Fanout Buffer with Configurable Phase Delay. The device supports the division, phase-delay and distribution of  
high-frequency clocks (input: CLK, nCLK) and the fanout and phase-delay of low-frequency synchronization (SYSREF) signals (input:  
REF/nREF). Clock and SYSREF signal paths are independent and are organized in channels, with each channel consisting of several clock  
and SYSREF outputs. Outputs are configurable with support for LVPECL, LVDS and four amplitude settings. Individual channels and unused  
circuit blocks support a powered-down state for reduced power consumption operation. The register map, accessible through a SPI interface  
with read-back capability controls the main device settings.  
Signal Flow  
The device offers four channels with the names A, B, C and D. Each channel supports individual frequency-division, phase-delay and fan-out  
functions of the input clock to a total of eight QCLK_y clock outputs; each channel also distributes the SYSREF input signal to multiple  
QREF_r outputs with individual per-output phase delay capability.  
The central clock distribution ensures low skew clock outputs within each channel; outputs are synchronous across channels (independent on  
the divider setting) on the incident rising clock edge for all outputs with equal phase delay settings.  
SYSREF output are synchronous with each other for equal phase-delay settings. QCLK_y and QREF_r outputs will be phase-locked to each  
other if the CLK and REF inputs are phase-locked. The phase-delay capability in each signal path can be used to establish repeatable and  
deterministic clock to SYSREF phase relationships at the outputs.  
The CLK and QREF signal paths are optimized for channel isolation. allowing high-speed clocks of 983.04MHz, 1474.56MHz or 1966.08MHz  
(up to 3GHz) and lower-speed SYSREF signals at e.g. 7.68MHz or 9.6MHz with a minimum of signal crosstalk and spurious signals.  
Clock Channel Divider  
Each of the four independent frequency dividers NA-ND can be individually set to the divider values ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16. The dividers  
are synchronous and have an equal propagation delay on the incident edge. See Table 2 for the supported frequency divider settings.  
Table 2. NA-D Frequency Divider Settings  
NA-D  
Clock Divider  
÷1  
000  
Divider bypass and powered down  
001  
010  
011  
100  
101  
110  
111  
÷2  
÷4  
÷6  
÷8  
÷12  
÷16  
Not defined  
©2017 Integrated Device Technology, Inc.  
6
June 22, 2017  
8V79S680 Datasheet  
Phase Delay  
Output phase delay is independently supported on each clock channel and each SYSREF output. The delay unit of the clock channel  
phase-delay circuits CLK_x is a function of the frequency fIN applied to CLK input: 1 ÷ fIN.  
The delay unit of the SYSREF phase-delay circuits REF_r is a function of an internal oscillator frequency fDCO and the DLC multiplier setting.  
The oscillator is fully self-contained and located in delay calibration block (DCB). At startup, this oscillator is calibrated with the input frequency  
f
IN as reference. After the calibration, the oscillator is turned-off to save power and to eliminate noise. See Table 3 for details on the delay unit,  
number of available steps and the delay range.  
Table 3. Delay Circuit Characteristics  
Delay Circuit  
Unit  
Steps  
Range  
[a]  
Clock channel CLK_x  
1 ÷ fIN  
256  
256 ÷ fIN  
1.017ns at fIN = 983.04MHz  
0 to 259.3ns at fIN = 983.04MHz  
[b]  
[c]  
SYSREF REF_r  
TDCB  
8
0…7 * TDCB  
DLC = 0: 131ps  
DLC = 1: 262ps  
DLC = 2: 393ps  
DLC = 3: 524ps  
DLC = 0: 0 to 0.917ns  
DLC = 1: 0 to 1.834ns  
DLC = 2: 0 to 2.751ns  
DLC = 3: 0 to 3.668ns  
[a] At fIN = 983.04MHz, the clock channel delay range is equal to 260.416ns and encompasses 32 periods of a 122.88MHz clock signal.  
[b] TDCB ~ DLC ÷ (8·fDCO). fDCO = 983.04MHz. DLC = 1, 2, 3 or 4.  
[c] SYSREF phase delay supports 8 delay stops within one input reference period for fIN = 254.76MHz to fIN = 983.04MHz.  
Delay Calibration Block (DCB)  
The DCB sets the SYSREF delay unit by providing a reference signal to the QREF_r delay circuits. Figure 3 shows the functional diagram. The  
DCB requires configuration and calibration. Verification of the calibration is optional.  
Description. The DCB consists of an internal DCO running at fDCO = 983.04±20MHz, three frequency dividers PDCB, MDCB and NDCB and a  
digital hold circuit. The DCB input frequency is the device input frequency fIN at the differential CLK, nCLK input. The input frequency acts as a  
reference to lock the oscillator to a stable and known frequency.  
The output of the DCB is the effective delay unit TDCB which is approx. one eighth of the oscillator period multiplied by the DLC multiplier. The  
DLC multiplier extends the delay unit by a factor of 1, 2, 3 or 4. For instance, at a DCO frequency of 983.04MHz, DLC = 1 sets the SYSREF  
delay unit to 131ps; DLC = 2 sets the delay unit to 262ps, etc.  
Configuration. Select a desired delay unit and corresponding DLC multiplier from Table 4. DLC[1:0] also sets the NDCB divider. Then, find a  
P
DCB and MDCB divider configuration to locate the oscillator frequency into the range of fDCO = 983.04MHz according to the formula in  
Figure 3. The DCO lock condition is f1 = f2 while both f1 and f2 must be lower than 200MHz. For instance, if fIN = 245.76MHz and the smallest  
possible SYSREF delay unit is desired, set DLC = 1 (DLC[1:0] = 00; also sets NDCB = ÷1). Then, set PDCB = ÷24 and MDCB = ÷96. As a result,  
f1 = f2 = 10.24MHz, fDCO = 983.04MHz. This example configuration results in a delay unit of measured: 131ps. Figure 5 shows more  
configuration examples.  
Calibration. Calibration requires a valid DCB configuration with the DCO locking to an input frequency. Setting DCB_CAL = 1 starts an  
automatic calibration. At the end, the DCB_CAL bit will clear, the delay unit value is stored digitally and the DCO, PDCB, MDCB and NDCB  
frequency dividers turn off. The QREF_r delay circuits now use the stored constant delay unit. The delay unit remains digitally stored until the  
next power cycle. The DCB calibration must run once as part of the device startup procedure and must be re-run after each input frequency or  
DCB configuration change.  
Verification. Verify a successful calibration by reading the DAC_CODE value. 0 < DAC_CODE< 32767 indicates a successful calibration. If  
DAC_CODE = 0 or DAC_CODE = 32767, the DCB calibration should be re-run with an alternative PDCB, MDCB setting while maintaining the  
desired MDCB · NDCB/PDCB ratio for locking the DCO to the input frequency.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Figure 3. DCB Functional Diagram  
DCB_CAL  
f
f
IN  
DCO  
N  
---------------- = ----------------------------------------  
P
M
fIN  
f1  
f2  
DCB  
DCB  
DCB  
÷PDCB  
÷MDCB  
DCO  
983.04±20MHz  
Digital  
Hold  
Delay Unit TDCB  
131ps · (1+DLC[1:0])  
÷NDCB  
f
= 983MHz 20MHz  
DCO  
DLC[1:0]  
Table 4. DCB Delay Unit at fDCO = 983.04MHz  
DLC  
TDCB  
Delay Unit (ps)  
DLC[1:0] Setting  
Numeric Value  
NDCB  
131  
262  
393  
524  
00  
01  
10  
11  
1
2
3
4
1
2
3
4
Table 5. DCB Divider Configuration Examples[a]  
TDCB  
Delay Unit in ps  
fIN (MHz)  
DLC  
PDCB  
MDCB  
131  
262  
393  
524  
131  
262  
393  
524  
131  
262  
393  
524  
1
2
3
4
1
2
3
4
1
2
3
4
24  
24  
24  
24  
48  
48  
48  
48  
96  
96  
96  
96  
96  
48  
32  
24  
96  
48  
32  
24  
96  
48  
32  
24  
245.76  
491.52  
983.04  
[a] fDCO = 983.04MHz.  
©2017 Integrated Device Technology, Inc.  
8
June 22, 2017  
8V79S680 Datasheet  
QCLK to SYSREF Phase Alignment  
To achieve an output phase alignment between the QCLK_y clock and the QREF_r SYSREF outputs, the CLK and REF input signals must be  
phase aligned or have a known, deterministic phase relationship. Figure 4 shows an example output phase alignment for aligned clock and  
SYREF inputs. The closest (smallest phase error) output alignment is achieved by setting the clock phase delay register QCLK_Y to 0x00  
(clock) and the SYSREF phase delay register QCLK_Y to 0x04. With a SYSREF phase delay setting of 0x03 or less, the QREF_r output  
phase is in advance of the QCLK_y phase, which is applicable in JESD204B application. Phase delay settings and propagation delays are  
independent on the clock and SYSREF frequencies. Table 6 shows recommended phase delay setting several device configurations.  
Figure 4. QCLK to QREF Phase Alignment  
Input Phase  
Alignment  
1017 ps  
CLK  
983.04MHz  
REF  
7.68MHz  
Output Phase  
Alignment  
tPD ~ 550ps  
QCLK_y  
QCLK_y = 0x00  
tPD ~ 900ps + (4·131)ps  
QREF_r  
REF_r = 0x04  
QREF_r in advance of QCLK_y  
QCLK_y  
QCLK_y = 0x00  
131ps  
262ps  
QREF_r  
REF_r = 0x03  
QREF_r  
REF_r = 0x02  
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8V79S680 Datasheet  
Table 6. Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment[a]  
Divider Configuration  
CLK_y  
REF_r  
N = ÷1  
0x00  
0x04  
[a] QCLK and QREF outputs are aligned on the incident edge.  
Differential Outputs  
Table 7. Output Features  
Output  
Style  
Ampl.[a]  
Disable  
Power Down  
DC Bias  
Termination  
QCLK_y[b],  
LVPECL  
50to VT  
[d]  
250-1000mV  
4 steps  
QREF_r[c]  
100differential[e]  
Yes  
Yes  
–
LVDS  
[f]  
(Clock)  
d
QREF_r  
LVPECL  
LVDS  
–
50to VT  
250-1000mV  
4 steps  
Yes  
Yes  
Yes[g]  
100differentiale f  
(SYSREF)  
[a] Amplitudes are measured single-ended. Differential amplitudes supported are 500mV, 1000mV, 1500mV and 2000mV.  
[b] y = A0, A1, A2, B0, B1, C0, C1 and D.  
[c] r = A0, A1, A2, B0, B1, C0, C1 and D.  
[d] VT = VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting), VDD_V – 2.0V (750mV amplitude setting),  
VDD_V – 2.25V (1000mV amplitude setting).  
[e] AC coupling and DC coupling supported.  
[f] See Application Information for output termination information.  
[g] In JESD204B applications, it is recommended to use QREF_r (SYSREF) outputs configured to LVDS and 500mV amplitude. AC-coupling and  
DC-coupling is supported.  
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8V79S680 Datasheet  
Table 8. Individual Clock Output (QCLK_y) Settings[a]  
STY  
LE  
PD  
EN  
A[1:0]  
Output Power  
Termination[b]  
State  
Amplitude (mV)  
100differential (LVDS) or no  
1
X
X
0
X
Off  
Off  
X
termination  
XX  
00  
01  
10  
11  
XX  
00  
01  
10  
11  
Disable[c]  
X
250  
500  
750  
1000  
X
0
1
100differential (LVDS)  
1
0
1
Enable  
Disable  
Enable  
0
On  
250  
500  
750  
1000  
50to VT (LVPECL)  
[a] Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0).  
[b] See Application Information for output termination information.  
[c] Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.  
Table 9. Individual SYSREF Output (QREF_r) Settings[a]  
Output  
Power  
PD  
STYLE Enable A[1:0]  
nBIAS  
Termination[b]  
State  
Amplitude (mV)  
100differential or no  
1
X
0
X
0
X
X
Off  
Off  
X
termination  
XX  
00  
0
0
0
1
0
0
Disable[c]  
Enabled  
X
250  
See Table 10  
01  
100differential (LVDS)  
500  
1
10  
11  
XX  
00  
01  
10  
11  
Enabled  
Disable  
750  
1000  
X
0
On  
0
1
250  
500  
750  
1000  
1
0
50to VT (LVPECL)  
Enable  
[a] Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).  
[b] See Application Information for output termination information.  
[c] Differential output is disabled in static low state: QCLK_y = L, nQCLK_y = H.  
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8V79S680 Datasheet  
Table 10. QREF_r Setting for JESD204B Applications  
QREF_r Outputs (LVDS, 500mV amplitude)  
Active Rising Edge on the  
REF Input  
nBIAS_r  
Initial  
SYSREF Completed  
Application  
BIAS_TYPE  
0
0
1
Static Low (QREF = L, nQREF_r = H)  
QREF_r DC coupled  
Static Low  
Start switching for the  
Released to static low  
(QREF = L, nQREF_r = H)  
number of received  
SYSREF pulses  
(QREF = L, nQREF_r = H)  
1
0
1
Static LVDS crosspoint level  
(QREF = nQREF_r = VOS)  
Start switching for the  
number of received  
SYSREF pulses  
Released to static LVDS  
crosspoint level  
(QREF = nQREF_r = VOS)  
QREF_r AC coupled  
Static LVDS crosspoint level (QREF = nQREF_r = VOS)  
©2017 Integrated Device Technology, Inc.  
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8V79S680 Datasheet  
Device Startup, Reset, and Synchronization  
At startup, an internal POR (power-on reset) resets the device and sets all register bits to its default value. In the default configuration the  
QCLK_y and QREF_r outputs are disabled at startup.  
Recommended configuration sequence (in order):  
1. (Optional) set the value of the CPOL register bit to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read  
accesses.  
2. Configure the channel circuits and the outputs to the desired values and configure the DCB:  
▪ Output source MUX_r, output divider NA-D, clock delay A-D; MUX-output style, amplitude and power down mode for QCLK_y and  
QREF_r outputs  
▪ For synchronization between multiple devices: Set NA-D = ÷1 and set BYP_INIT = 1)  
▪ (Optional) the global BIAS_TYPE bit and nBIAS_r for each QREF_r in preparation for JESD204B/SYSREF operation  
▪ Phase delay for REF_r values for the QREF_r outputs  
▪ Setup the DCB settings DLC, PDCB and MDCB as described in the paragraph Configuration, see Delay Calibration Block (DCB)  
3. If not already applied: apply a valid input frequency to CLK. Set the PB_CAL bit and the DCB_CAL bit to start the calibration of the precision  
bias current circuit and the DCB calibration. Both bits will auto-clear. See paragraph Configuration in section Delay Calibration Block (DCB).  
▪ (Optional): verify the success of the DCB calibration by reading the DAC_CODE value. See paragraph Verification in section Delay  
Calibration Block (DCB)  
4. Set the initialization bit INIT_CLK. This will initiate the N_x divider and CLK_x delay circuits and synchronize them to each other. The  
INIT_CLK bit will self-clear.  
5. At this point, the configuration of the registers 0x00 to 0x73 should be completed and the SPI transfer ended. Set nCS to high level.  
6. In a separate SPI write access, enable the outputs as desired by accessing the output-enable registers 0x74 and 0x76.  
Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF range.  
Changing Frequency Dividers and Phase Delay Values  
Clock Frequency Divider and Delay  
Following procedure has to be applied for a change of a clock divider and phase delay value NA-D, and CLKA-D:  
1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read  
accesses.  
2. (Optional) disable the outputs whose frequency divider or delay value is changed.  
3. Configure the NA-D dividers and the delay circuits CLKA-D to the desired new values.  
▪ For synchronization between multiple devices: Set NA-D = ÷1 and set BYP_INIT = 1)  
4. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will  
self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.  
5. (Optional) Enable the outputs whose frequency divider was changed.  
SYSREF Delay  
Following procedure has to be applied for a change of any SYSREF phase delay value REF_r:  
1. (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read  
accesses.  
2. Configure any delay circuits REF_r to their desired new values. During configuration of REF_r outputs are not stopped or interrupted.  
©2017 Integrated Device Technology, Inc.  
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8V79S680 Datasheet  
SPI Interface  
The 8V79S680 has a 3-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any  
of the internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDAT (serial data input and  
output), and nCS (chip select) pins. A data transfer consists of any integer multiple of 8 bits and is always initiated by the SPI master on the  
bus. Internal register data is organized in SPI bytes of 8 bits each. If nCS is at logic high, the SDAT data I/O is in high-impedance state and the  
SPI interface of the 8V79S680 is disabled. In a write operation, data on SDAT will be clocked in on the rising edge of SCLK. In a read  
operation, data on SDAT will be clocked out on the falling or rising edge of SCLK depending on the CPOL setting (CPOL = 0: output data  
changes on the falling edge, CPOL = 1: output data changes on the rising edge).  
Starting a data transfer requires nCS to set and hold at logic low level during the entire transfer. Setting nCS = 0 will enable the SPI interface  
with SDAT in data input mode. The master must initiate the first 8-bit transfer. The first bit presented to the slave is the direction bit R/nW (1 =  
Read,  
0 = Write) and the following seven bits are the address bits A[0:6] pointing to an internal register in the address space 0 to 127. Data is  
presented with the LSB (least significant bit) first.  
Read operation from an internal register: a read operation starts with an 8 bit transfer from the master to the slave: SDAT is clocked on the  
rising edge of SCLK. The first bit is the direction bit R/nW which must be to 1 to indicate a read transfer, followed by 7 address bits A[0:6]. After  
the first 8 bits are clocked into SDAT, the SDAT I/O changes to output: the register content addressed by A[0:6] is loaded into the shift register  
and the next 8 SCLK falling clock cycles (if CPOL = 0) will then present the loaded register data on the SDAT output and transfer these to the  
master. Transfers must be completed by de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of  
SCLKs, the SPI behavior is undefined. SPI byte (8 bit) and back-to-back read transfers of multiple registers are supported with an address  
auto-increment. During multiple transfers, nCS must stay at logic low level and SDAT will present multiple registers (A), (A+1), (A+2), etc. with  
each 8 SCLK cycles. During SPI Read operations, the user may continue to hold nCS low and provide further bytes in a single block read.  
Write operation to a 8V79S680 register: During a write transfer, a SPI master transfers one or more bytes of data into the internal registers of  
the 8V79S680. A write transfer starts by asserting nCS to low logic level. The first bit presented by the master must set the direction bit R/nW  
to 0 (Write) and the 7 address bits A[0:6] must contain the 7-bit register address. Bits D0 to D7 contain 8 bit of payload data, which is written  
into the register addressed by A[0:6] at the end of a 8-bit write transfer. Multiple, subsequent register transfers from the master to the slave are  
supported by holding nCS asserted at logic low level during write transfers. The 7 bit register address will auto-increment. Transfers must be  
completed by de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is  
undefined.  
End of transfer: After de-asserting nCS, the SPI bus is available to transfers to other slaves on the SPI bus. See also the READ diagram  
(Figure 5) and WRITE diagram (Figure 6) displaying the transfer of two bytes of data from and into registers.  
Registers 0x78 to 0xFF: Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to 0xFF  
range.  
Figure 5. Logic Diagram: READ Data from 8V79S680 Registers for CPOL = 0 and CPOL = 1  
SCLK  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
nCS  
SDAT, CPOL=0  
SDAT, CPOL=1  
Hi-Imp  
Hi-Imp  
Hi-Imp  
Hi-Imp  
1
1
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7  
A0 A1 A2 A3 A4 A5 A6  
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7  
Output Register Data  
(Address)  
Output Register Data  
(Address+1)  
Input R=1, 7-bit Address  
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8V79S680 Datasheet  
Figure 6. Logic Diagram WRITE Data into 8V79S680 Registers  
SCLK  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23  
nCS  
Hi-Imp  
Hi-Imp  
0
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7  
SDAT  
Input Register Data  
Input nW=0, 7-bit Address  
Input Register Data (Address)  
(Address+1)  
Table 11. SPI Read / Write Cycle Timing Parameters  
Symbol  
fSCLK  
Parameter  
Test Condition  
Minimum  
Maximum  
Unit  
SCLK frequency  
20  
MHz  
ns  
tS1  
Setup time, nCS (falling) to SCLK (rising)  
Setup time, SDAT (input) to SCLK (rising)  
Setup time, nCS (rising) to SCLK (rising)  
Hold time, SCLK (rising) to SDAT (input)  
Hold time, SCLK (falling) to nCS (rising)  
Propagation delay, SCLK (falling) to SDAT  
Propagation delay, SCLK (rising) to SDAT  
Propagation delay, nCS to SDAT disable  
5
5
5
5
5
tS2  
ns  
tS3  
ns  
tH1  
ns  
tH2  
ns  
tPD1F  
tPD1R  
tPD2  
CPOL = 0  
CPOL = 1  
12  
12  
12  
ns  
ns  
ns  
Figure 7. SPI Timing Diagram  
tH2  
nCS  
tS3  
tS1  
SCLK  
tS2 tH1  
SDAT  
(Input)  
tPD1F  
tPD1R  
tPD2  
SDAT  
(Output)  
High Impedance  
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8V79S680 Datasheet  
Register Descriptions  
This section contains a list of all addressable registers and a register description, sorted by function, followed for a detailed description of each  
bit field for each register. Several functional blocks with multiple instances in this device have individual registers controlling their settings, but  
since the registers have an identical format and bit meaning, they are described only once, but with an additional table to indicate their  
addresses and default values. All writable register fields will come up with a default values as indicated in the Factory Defaults column unless  
altered by values loaded from non-volatile storage during the initialization sequence.  
Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of the  
conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are Reserved.  
Reserved bit fields will be unaffected by writes and are undefined on reads.  
Table 12. Configuration Registers  
Register Address  
Register Description  
0x00–0x17  
0x18–0x1B  
0x1C–0x1F  
0x20  
Reserved  
SYSREF Control  
Reserved  
Channel A, Output Divider  
Channel A Delay CLK_A  
Channel A PD  
0x21  
0x22  
0x23  
Reserved  
0x24  
Output State QCLK_A0  
Output State QCLK_A1  
Output State QCLK_A2  
Reserved  
0x25  
0x26  
0x27  
0x28  
REF_A0 Delay, MUX, PD  
REF_A1 Delay, MUX, PD  
REF_A2 Delay, MUX, PD  
Reserved  
0x29  
0x2A  
0x2B  
0x2C  
Output State QREF_A0  
Output State QREF_A1  
Output State QREF_A2  
Reserved  
0x2D  
0x2E  
0x2F  
0x30  
Channel B, Output Divider  
Channel B Delay CLK_B  
Channel B PD  
0x31  
0x32  
0x33  
Reserved  
0x34  
Output State QCLK_B0  
Output State QCLK_B1  
Reserved  
0x35  
0x36–0x37  
0x38  
REF_B0 Delay, MUX, PD  
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8V79S680 Datasheet  
Table 12. Configuration Registers (Cont.)  
Register Address  
Register Description  
0x39  
0x3A–0x3B  
0x3C  
REF_B1 Delay, MUX, PD  
Reserved  
Output State QREF_B0  
Output State QREF_B1  
Reserved  
0x3D  
0x3E–0x3F  
0x40  
Channel C, Output Divider  
Channel C Delay CLK_C  
Channel C PD  
0x41  
0x42  
0x43  
Reserved  
0x44  
Output State QCLK_C0  
Output State QCLK_C1  
Reserved  
0x45  
0x46–0x47  
0x48  
REF_C0 Delay, MUX, PD  
REF_C1 Delay, MUX, PD  
Reserved  
0x49  
0x4A–0x4B  
0x4C  
Output State QREF_C0  
Output State QREF_C1  
Reserved  
0x4D  
0x4E–0x4F  
0x50  
Channel D, Output Divider  
Channel D Delay CLK_D  
Channel D PD  
0x51  
0x52  
0x53  
Reserved  
0x54  
Output State QCLK_D  
Reserved  
0x55–0x57  
0x58  
REF_D Delay, MUX, PD  
Reserved  
0x59–0x5B  
0x5C  
Output State QREF_D  
Reserved  
0x5D–0x6B  
0x6C–0x6D  
0x6E–0x6F  
0x70  
DAC_CODE  
General Control  
Reserved  
0x71–0x73  
0x74  
General Control  
Output State QCLK  
Reserved  
0x75  
0x76  
Output State QREF  
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8V79S680 Datasheet  
Table 12. Configuration Registers (Cont.)  
Register Address  
Register Description  
0x77  
0x78  
Reserved  
Do not use  
Do not use  
Do not use  
Do not use  
Do not use  
Do not use  
Do not use  
Do not use  
0x79  
0x7A  
0x7B  
0x7C–0x7D  
0x7E  
0x7F  
0x80–0xFF  
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8V79S680 Datasheet  
Channel and Clock Output Registers  
The content of the channel register and clock output registers set the clock divider, output style, amplitude, power down state, enable state and  
the clock phase delay.  
Table 13. Channel and Clock Output Register Bit Field Locations  
Bit Field Location  
Register Address  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0x20  
0x30  
0x40  
0x50  
N_A[2:0]  
N_B[2:0]  
N_C[2:0]  
N_D[2:0]  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0x21  
0x31  
0x41  
0x51  
CLK_A[7:0]  
CLK_B[7:0]  
CLK_C[7:0]  
CLK_D[7:0]  
0x22  
0x32  
0x42  
0x52  
PD_A  
PD_B  
PD_C  
PD_D  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0x24: QCLK_A0  
0x25: QCLK_A1  
0x26: QCLK_A2  
PD_A0  
PD_A1  
PD_A2  
STYLE_A0  
STYLE_A1  
STYLE_A2  
A_A0[1:0]  
Reserved  
Reserved  
Reserved  
Reserved  
A_A1[1:0]  
A_A2[1:0]  
Reserved  
0x34: QCLK_B0  
0x35: QCLK_B1  
PD_B0  
PD_B1  
STYLE_B0  
STYLE_B1  
A_B0[1:0]  
A_B1[1:0]  
Reserved  
0x44: QCLK_C0  
0x45: QCLK_C1  
PD_C0  
PD_C1  
STYLE_C0  
STYLE_C1  
A_C0[1:0]  
A_C1[1:0]  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0x54: QCLK_D  
0x74  
PD_D  
STYLE_D  
A_D[1:0]  
EN_QCLK_A0 EN_QCLK_A1 EN_QCLK_A2 EN_QCLK_B0 EN_QCLK_B1 EN_QCLK_C0 EN_QCLK_C1 EN_QCLK_D  
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8V79S680 Datasheet  
Table 14. Channel and Clock Output Register Descriptions[a]  
Register Description  
Default  
Bit Field Name  
Field Type  
(Binary)  
Description  
Output Frequency Divider N  
N_x[2:0]  
Frequency Divider  
000  
001  
010  
011  
100  
101  
110  
111  
÷1 (Divider bypassed and powered-down)  
÷2  
÷4  
000  
÷6  
N_x[2:0]  
R/W  
÷8  
Value: ÷1  
÷12  
÷16  
Not defined  
If N_x[2:0] = 000 (÷1), set BYP_INIT = 1 to exclude the divider from  
initialization.  
0 = Channel x is powered up  
1 = Channel x is powered down  
PD_x  
PD_y  
R/W  
R/W  
0
0
0 = Output QCLK_y is powered up  
1 = Output QCLK_y is powered down  
CLK_x Phase Delay  
CLK_x[7: Phase Delay in units of the input period: CLK_x[7:0] ÷ fIN (256 steps).  
0]  
0000 0000  
Value: 0ns  
CLK_x[7:0]  
R/W  
0000 0000  
0000 0001  
…
0ps  
1 ÷ fIN  
…
1111 1111  
255 ÷ fIN  
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8V79S680 Datasheet  
Table 14. Channel and Clock Output Register Descriptions[a]  
Register Description  
Default  
Bit Field Name  
Field Type  
(Binary)  
Description  
QCLK_y Output Amplitude  
Setting for STYLE = 0 (LVDS)  
Setting for STYLE = 1 (LVPECL)  
Termination: 50to VT  
00  
Termination: 100across  
A_y[1:0]  
R/W  
A[1:0] = 00: 250mV  
A[1:0] = 01: 500mV  
A[1:0] = 10: 750mV  
A[1:0] = 11:1000mV  
Value:  
250mV  
QCLK_y Output Format:  
0
0 = Output is LVDS (requires LVDS 100output termination)  
STYLE_y  
EN_y  
1 = Output is LVPECL (requires LVPECL 50output termination to the specified  
recommended termination voltage)  
Value: LVDS  
0
QCLK_y Output Enable:  
0 = QCLK_y Output is disabled at the logic low state  
1 = QCLK_y Output is enabled  
Value:  
disabled  
[a] x = A, B, C, D; y = A0, A1, A2, B0, B1, C0, C1, D.  
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8V79S680 Datasheet  
QREF Output State Registers  
The content of the QREF output registers selects the source signal of the QREF outputs, set the phase delay, the style, the amplitude, the  
power state, the enable state and the output bias.  
Table 15. QREF Output State Register Bit Field Locations[a]  
Bit Field Location  
Register Address  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0x28: QREF_A0  
0x29: QREF_A1  
0x2A:QREF_A2  
MUX_A0  
MUX_A1  
MUX_A2  
REF_A0[2:0]  
REF_A1[2:0]  
REF_A2[2:0]  
Reserved  
Reserved  
Reserved  
Reserved  
0x38: QREF_B0  
0x39: QREF_B1  
MUX_B0  
MUX_B1  
REF_B0[2:0]  
REF_B1[2:0]  
Reserved  
Reserved  
Reserved  
Reserved  
0x48: QREF_C0  
0x49: QREF_C1  
MUX_C0  
MUX_C1  
REF_C0[2:0]  
REF_C1[2:0]  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0x58: QREF_D  
MUX_D  
REF_D[2:0]  
0x2C: QREF_A0  
0x2D: QREF_A1  
0x2E: QREF_A2  
PD_A0  
PD_A1  
PD_A2  
nBIAS_A0  
nBIAS_A1  
nBIAS_A2  
STYLE_A0  
STYLE_A1  
STYLE_A2  
A_A0[1:0]  
Reserved  
Reserved  
A_A1[1:0]  
A_A2[1:0]  
Reserved  
Reserved  
Reserved  
Reserved  
0x3C: QREF_B0  
0x3D: QREF_B1  
PD_B0  
PD_B1  
nBIAS_B0  
nBIAS_B1  
STYLE_B0  
STYLE_B1  
A_B0[1:0]  
A_B1[1:0]  
0x4C: QREF_C0  
0x4D: QREF_C1  
PD_C0  
PD_C1  
nBIAS_C0  
nBIAS_C1  
STYLE_C0  
STYLE_C1  
A_C0[1:0]  
A_C1[1:0]  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
0x5C: QREF_D  
0x76  
PD_D  
nBIAS_D  
STYLE_D  
A_D[1:0]  
EN_QREF_A0 EN_QREF_A1 EN_QREF_A2 EN_QREF_B0 EN_QREF_B1EN_QREF_C0EN_QREF_C1 EN_QCLK_D  
[a] r = A0, A1, A2, B0, B1, C0, C1, D.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 16. QREF Output State Register Descriptions[a]  
Register Description  
Default  
(Binary)  
Bit Field Name  
Field Type  
Description  
1
0 = QREF_r output signal source is the channel’s clock signal  
1 = QREF_r output signal source is the centrally generated SYSREF signal  
MUX_r  
R/W  
Value:  
QREF =  
SYSREF  
SYSREF Phase Delay:  
QREF_r delay = REF_r[2:0] · TDCB.  
Delay values for fDCO = 983.04MHz. Delay values are a function of TDCB.  
REF_r[2: QREF_r delay in ps for a DLC[1:0] setting of:  
0]  
000  
00  
01  
10  
0
11  
REF_r[2:0]  
R/W  
000  
001  
010  
…
0
0
0
Value: 0ps  
131  
262  
…
262  
524  
…
393  
786  
…
524  
1048  
…
111  
917  
1834  
2751  
3668  
QREF_r Output Bias Voltage:  
Individual QREF_r output LVDS output bias operation. Not applicable to QREF_r  
outputs set to LVPECL mode.  
0 = Normal operation  
1 = Output is biased to the LVDS cross-point voltage if BIAS_TYPE (register 0x19, bit 7)  
is set to 1. Bit has no effect if BIAS_TYPE = 0.  
Output bias = 1 requires AC coupling and LVDS style on the corresponding output.  
BIAS_TYPE nBIAS_r  
QREF_r output operation if set to LVDS.  
0
0
1
0
1
0
QREF_r outputs are initially logic low (QREF_r = L,  
nQREF_r = H) and will start switching on the first rising  
edge of the REF input. Use in DC-coupled applications.  
nBIAS_r  
R/W  
0
Disabled with static low/high levels. During a SYSREF  
event, the output remains at static low levels (QREF_r = L,  
nQREF_r = H).  
Both QREF_r and nQREF_r outputs are initially set to the  
LVDS crosspoint level (VOS) and will start switching on  
the first rising edge of the REF input. Use in AC-coupled  
applications.  
1
1
Output is statically set to the LVDS crosspoint voltage.  
During a SYSREF event, the output remains at the LVDS  
crosspoint level (VOS).  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 16. QREF Output State Register Descriptions[a] (Cont.)  
Register Description  
Default  
Bit Field Name  
Field Type  
(Binary)  
Description  
QREF_r Output Amplitude  
Setting for STYLE = 0 (LVDS)  
Setting for STYLE = 1 (LVPECL)  
Termination: 50to VT  
00  
Termination: 100across  
A_r[1:0]  
R/W  
A[1:0] = 00: 250mV  
A[1:0] = 01: 500mV  
A[1:0] = 10: 750mV  
A[1:0] = 11:1000mV  
Value:  
250mV  
0
QREF_r Output Power Down:  
0 = Output is powered up  
PD_r  
STYLE_r  
EN_r  
R/W  
R/W  
R/W  
Value:  
Powered up  
1 = Output is powered down. STYLE, EN and A[1:0] settings have no effect  
0
QREF_r Output Format:  
0 = Output is LVDS (requires LVDS 100output termination)  
Value:  
LVDS  
1 = Output is LVPECL (requires LVPECL 50output termination of to the specified  
recommended termination voltage)  
0
QREF_r Output Enable:  
0 = Output is disabled at the logic low state  
1 = Output is enabled  
Value:  
Disabled  
[a] r = A0, A1, A2, B0, B1, C0, C1, D.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
SYSREF Control Registers  
Table 17. SYSREF Control Register Bit Field Locations  
Bit Field Location  
Register Address  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0x18  
PD_S  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
M_DCB[8]  
0x19  
0x1A  
0x1B  
BIAS_TYPE  
DLC[1:0  
Reserved  
Reserved  
Reserved  
M_DCB[7:0]  
P_DCB[6:0]  
Reserved  
Table 18. SYSREF Control Register Descriptions  
Register Description  
Default  
(Binary)  
Bit Field Name  
Field Type  
Description  
1
SYSREF Global Power-down:  
0 = SYSREF functional blocks are powered-up  
1 = SYSREF functional blocks are powered-down  
PD_S  
R/W  
Value:  
Powered  
down  
SYSREF Output Voltage Bias:  
Global to all QREF_r outputs bit to control the LVDS output operation. Not applicable to  
QREF_r outputs set to LVPECL mode.  
BIAS_TYPE nBIAS_r  
QREF_r output operation if set to LVDS.  
0
0
1
0
1
0
QREF_r outputs are initially logic low (QREF_r = L,  
nQREF_r = H) and will start switching on the first rising  
edge of the REF input. Use in DC-coupled applications.  
Disabled with static low/high levels. During a SYSREF  
event, the output remains at static low levels (QREF_r = L,  
nQREF_r = H).  
BIAS_TYPE  
R/W  
1
Both QREF_r and nQREF_r outputs are initially set to the  
LVDS crosspoint level (VOS) and will start switching on  
the first rising edge of the REF input. Use in AC-coupled  
applications.  
1
1
Output is statically set to the LVDS crosspoint voltage.  
During a SYSREF event, the output remains at the LVDS  
crosspoint level (VOS).  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 18. SYSREF Control Register Descriptions (Cont.)  
Register Description  
Default  
(Binary)  
Bit Field Name  
Field Type  
Description  
Delay Unit Multiplier:  
Effective delay unit for the SYSREF outputs is (1 + DLC[1:0]) ÷ (8 · fDCO).  
00  
DLC[1:0]  
Effective SYSREF Delay Unit for fDCO = 983.04MHz  
00  
01  
10  
11  
131ps  
262ps  
393ps  
524ps  
DLC[1:0]  
R/W  
Value:  
131ps  
0 0000  
1000  
Delay Calibration Block (DCB) DCO feedback divider. Set in conjunction with fIN and  
P_DCB to achieve a DCO frequency of 983.04±20MHz: fDCO = fIN ÷ PDCB · MDCB.  
M_DCB[8:0]  
P_DCB[6:0]  
R/W  
R/W  
Value: 8  
000 1000 Delay Calibration Block (DCB) DCO input divider. Set in conjunction with fIN and M_DCB  
to achieve DCO frequency of 983.04±20MHz: fDCO = fIN ÷ PDCB · MDCB. DCO phase  
Value: 8  
detector frequency should not exceed 200MHz.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
General Control Registers  
Table 19. General Control Register Bit Field Locations  
Bit Field Location  
D4  
Register Address  
D7  
D6  
D5  
D3  
D2  
D1  
D0  
0x6C  
Reserved  
DAC_CODE[14:8]  
0x6D  
0x6E  
0x6F  
0x70  
0x71  
0x72  
0x73  
DAC_CODE[7:0]  
Reserved  
Reserved  
Reserved  
INIT_CLK  
DCB_CAL  
PB_CAL  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PBIAS[5:0]  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
BYP_INIT  
Reserved  
Reserved  
Reserved  
CPOL  
Table 20. General Control Register Descriptions  
Register Description  
Default  
(Binary)  
Bit Field Name  
Field Type  
Description  
DAC_CODE is the result of the internal DCB calibration routine. Trigger calibration by  
setting the DCB_CAL bit.  
DAC_CODE[14:0]  
PBIAS[5:0]  
R only  
R only  
X
X
BIAS level.  
Clock divider and phase clock phase delay initialization.  
W only  
Set INIT_CLK = 1 to initialize N_x divider and CLK_x clock phase delay functions.  
Required as part of the startup procedure and after each change of a clock divider or  
clock phase delay value.  
INIT_CLK  
X
Auto-Clear  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 20. General Control Register Descriptions (Cont.)  
Register Description  
Default  
(Binary)  
Bit Field Name  
Field Type  
Description  
Precision Bias Calibration:  
Set PB_CAL to 1 starts the auto-calibration of an internal precision bias current source.  
The bias current is used as reference for outputs configured as LVDS. This bit will  
auto-clear after the calibration completed. Required to set as part of the startup  
procedure.  
W only  
PB_CAL  
X
X
Auto-Clear  
DCB Calibration:  
Setting this bit to 1 will begin the auto-calibration of the DCB. The DCB provides a  
reference for the SYSREF delay circuits. This bit will auto-clear. This bit should be set  
as part of the startup procedure. The result of the calibration routine is stored in the  
DAC_CODE register.  
W only  
DCB_CAL  
Auto-Clear  
Bypass Clock Frequency Divide Initializer:  
0 = The clock dividers NA-D are initialized when INIT_CLK = 1  
BYP_INIT  
CPOL  
R/W  
R/W  
1
0
1 = The clock dividers NA-D are excluded from the initialization. This setting is only  
applicable to NA-D dividers = ÷1 and should be used to achieve output phase alignment  
across multiple devices.  
SPI Read Operation SCLK Polarity:  
0 = Data bits on MISO are output at the falling edge of SCLK edge.  
1 = Data bits on MISO are output at the rising edge of SCLK edge.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Electrical Characteristics  
Absolute Maximum Ratings  
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.  
Functional operation of the 8V79S680 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect  
device reliability.  
Table 21. Absolute Maximum Ratings  
Item  
Rating  
Supply Voltage, VDD_V  
Inputs  
3.6V  
-0.5V to VDD_V + 0.5V  
-0.5V to VDD_V + 0.5V  
Outputs, VO (LVCMOS)  
Outputs, IO (LVPECL)  
Continuous Current  
Surge Current  
50mA  
100mA  
Outputs, IO (LVDS)  
Continuous Current  
Surge Current  
50mA  
100mA  
Input termination current, IVT  
±35mA  
Operating Junction Temperature, TJ  
125C  
Storage Temperature, TSTG  
ESD - Human Body Model[a]  
-65C to 150C  
2000V  
ESD - Charged Device Modela  
500V  
[a] According to JEDEC JS-001-2012/JESD22-C101.  
Pin Characteristics  
Table 22. Pin Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C  
Symbol  
CIN  
Parameter  
Input Capacitance  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
2
4
pF  
k  
k  
RPD  
Input Pull-Down Resistor  
Input Pull-Up Resistor  
SCLK  
nCS  
51  
51  
25  
RPU  
ROUT  
LVCMOS Output Impedance  
SDAT (when output)  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
DC Characteristics  
Table 23. Power Supply DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a]  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VDD_V  
Core Supply Voltage  
3.135  
3.3  
3.465  
V
IDD (Total) Power Supply Current  
QCLK_y and QREF_r set to LVDS,  
750mV amplitude, terminated 100,  
Nx dividers set to ÷1  
705  
mA  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
Table 24. Typical Power Supply Current Characteristics, VDD_V = 3.3V, TA = 25°C[a]  
Test Case  
Symbol  
Supply Pin Current  
1
2
3
4
5
6
Unit  
QCLK_y  
QREF_r  
Style  
LVPECL  
On  
LVPECL  
On  
LVDS  
On  
LVDS  
On  
LVDS  
On  
LVDS  
On  
State  
Amplitude  
Style  
500  
750  
500  
LVDS  
Off  
500  
750  
750  
mV  
LVDS  
Off  
LVDS  
Off  
LVDS  
On  
LVDS  
On  
LVDS  
On  
State  
Amplitude  
–
–
–
250  
250  
500  
mV  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
W
IDD_CA  
IDD_RA01  
IDD_RA2  
IDD_CB  
IDD_RB  
IDD_CC  
IDD_RC  
IDD_CD  
IDD_RD  
IDD_CLK  
IDD_REF  
IDD_SPI  
PTOT  
Current through VDD_QCLKA pin(s)  
Current through VDD_QREFA01 pin(s)  
Current through VDD_QREFA2 pin(s)  
Current through VDD_QCLKB pin(s)  
Current through VDD_QREFB pin(s)  
Current through VDD_QCLKC pin(s)  
Current through VDD_QREFC pin(s)  
Current through VDD_QCLKD pin(s)  
Current through VDD_QREFD pin(s)  
Current through VDD_CLK pin(s)  
Current through VDD_REF pin(s)  
Current through VDD_SPI pin(s)  
Total Device Power Consumption  
109.6  
1.5  
127.3  
1.5  
73.0  
1.5  
73.0  
27.0  
13.5  
48.0  
27.0  
49.0  
27.0  
29.5  
13.6  
40.2  
52.8  
13.3  
1.365  
1.365  
95.0  
26.9  
13.5  
63.0  
27.0  
63.0  
27.0  
36.4  
13.6  
40.2  
53.5  
13.4  
1.559  
1.559  
95.0  
43.0  
20.5  
63.0  
43.0  
63.0  
43.0  
36.4  
20.7  
40.1  
54.2  
13.4  
1.766  
1.766  
0.8  
0.7  
0.8  
72.4  
1.5  
83.6  
1.5  
48.0  
1.5  
76.2  
1.5  
87.7  
1.5  
49.3  
1.5  
43.8  
0.8  
49.6  
0.8  
29.5  
0.8  
40.3  
9.8  
40.2  
9.8  
39.8  
9.7  
12.8  
1.223  
1.403  
13.1  
1.377  
1.557  
12.9  
0.885  
0.885  
PTOT, SYS Total System Power Consumption[b]  
W
[a] fIN (input) = 983.04MHz, fSYSREF = 7.68MHz. Supply current is independent on the output frequency. QCLK_y outputs terminated according to amplitude  
settings. QREF_r outputs unterminated when SYSREF is turned off.  
[b] Includes total device power consumption and the power dissipated in external output termination components.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 25. LVCMOS (JESD8-7A, 1.8V) DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a] [b]  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VT+  
Positive-going SCLK, nCS, SDAT  
input threshold  
0.660  
1.365  
V
voltage  
VT-  
Negative-goin  
g input  
0.495  
0.165  
1.170  
V
threshold  
voltage  
VH  
Hysteresis  
Voltage  
V
T+ – VT-  
0.780  
150  
V
µA  
µA  
V
IIH  
Input  
High Current  
V
DD_V = 3.3V, VIN = 1.8V  
IIL  
Input  
Low Current  
V
DD_V = 3.465V, VIN = 0V  
IOH = -4mA  
-150  
1.4  
VOH  
VOL  
Output  
High Voltage  
SDAT (when output)  
Output  
Low Voltage  
IOL = 4mA  
0.45  
V
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[b] Table is valid for the SPI interface pins nCS, SCLK and SDAT. SPI inputs have hysteresis.  
Table 26. Differential Input DC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a]  
Symbol  
Parameter  
Input Resistance CLK, nCLK  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
RIN  
43.5  
50  
56.5  
REF, nREF  
RIN_DIFF Differential Input  
Resistance  
CLK, nCLK  
REF, nREF  
87  
100  
113  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 27. LVPECL DC Characteristics (QCLK_y, QREF_r, STYLE = 1), VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a]  
Symbol  
VOH  
VOL  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Output High Voltage[b]  
Output Low Voltageb  
Any Amplitude Setting  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
VDD_V - 1.10 VDD_V - 0.85 VDD_V - 0.65  
VDD_V - 1.30 VDD_V - 1.15 VDD_V - 1.10  
VDD_V - 1.55 VDD_V - 1.40 VDD_V - 1.25  
VDD_V - 1.80 VDD_V - 1.65 VDD_V - 1.50  
VDD_V - 2.10 VDD_V - 1.90 VDD_V - 1.75  
V
V
V
V
V
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[b] Outputs terminated with 50to VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting), VDD_V – 2.0V (750mV amplitude  
setting), VDD_V – 2.25V (1000mV amplitude setting).VDD_V.  
Table 28. LVDS DC Characteristics (QCLK_y, QREF_r, STYLE = 0), VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a] [b]  
Symbol  
Parameter  
Offset Voltage[c]  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOS  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
2.00  
1.80  
1.70  
1.55  
2.40  
2.23  
2.08  
1.93  
2.80  
2.60  
2.50  
2.35  
50  
V
V
V
V
VOS  
VOS Magnitude Change  
mV  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[b] Outputs are terminated 100  
[c] VOS changes with VDD_V.  
©2017 Integrated Device Technology, Inc.  
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8V79S680 Datasheet  
AC Characteristics  
Table 29. AC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a]  
Symbol  
Parameter  
Test Conditions  
Minimum Typical  
Maximum  
Units  
fIN  
Input  
CLK, nCLK  
REF, nREF  
0
0
983.04  
3000  
100  
MHz  
MHz  
Frequency[b]  
VIN  
Input Voltage  
Amplitude[c]  
CLK, nCLK  
REF, nREF  
0.15  
0.3  
1.2  
2.4  
V
V
V
VDIFF_IN Differential Input CLK, nCLK  
Voltage  
REF, nREF  
Amplitudec [d]  
VCMR  
fOUT  
Common Mode Input Voltage  
Output Frequency  
VDD_V – (VIN  
2)  
/
1.125  
QCLK, QREF (Clock), N = ÷1 to ÷16  
QREF (SYSREF)  
0
0
983.04  
3000÷N  
100  
MHz  
MHz  
%
odc  
Output Duty Cycle[e]  
QCLK, QREF (Clock), fCLK ≤ 2500MHz  
45  
50  
50  
50  
55  
QCLK, QREF (Clock),  
2500MHz < fCLK ≤ 3000MHz  
43  
45  
57  
%
QREF (SYSREF at 7.68MHz)  
QCLK, QREF (LVPECL), 20% to 80%  
QCLK, QREF (LVDS), 20% to 80%  
QREF (SYSREF, LVDS), 20% to 80%  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
250mV Amplitude Setting  
500mV Amplitude Setting  
750mV Amplitude Setting  
1000mV Amplitude Setting  
55  
%
tR / tF  
Output Rise/Fall Time  
250  
ps  
250  
ps  
250  
ps  
[f]  
VO(PP)  
LVPECL Output Voltage  
Swing, Peak-to-peak,  
983.04MHz  
260  
430  
675  
950  
520  
860  
1350  
1900  
190  
400  
625  
800  
380  
800  
1250  
1600  
300  
532  
320  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
650  
785  
920  
981  
1150  
640  
LVPECL Differential Output  
Voltage Swing, Peak-to-peak,  
983.04MHz  
600  
1064  
1570  
1962  
240  
1300  
1840  
2300  
280  
[g]  
VO(PP)  
LVDS Output Voltage Swing,  
Peak-to-peak, 983.04MHz  
500  
570  
750  
840  
1000  
480  
1160  
560  
LVDS Differential Output  
Voltage Swing, Peak-to-peak,  
983.04MHz  
1000  
1500  
2000  
1140  
1680  
2320  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 29. AC Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C[a] (Cont.)  
Symbol  
Parameter  
Test Conditions  
Minimum Typical  
Maximum  
Units  
tsk(o)  
Output Skew; NOTE[h] [i]  
All delays set to 0  
QCLK (same N divider)[j]  
100  
100  
ps  
QCLK (any N divider, incident rising  
edge)  
ps  
QREF (Clock)  
100  
100  
190  
375  
375  
850  
850  
1050  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
QREF (SYSREF)  
QCLK to QREF (QREF as clock output)j  
CLK to any QCLKj  
tsk(pp)  
Part-to-part skew  
All delays set to 0  
REF to any QREF  
CLK to QCLK_yj  
CLK to QCLK_y (divider bypass)j  
REF to QREF_r (REF_y = 0)  
CLK to QCLK_yj  
tPD  
Propagation Delayj  
300  
All delay circuits set to 0  
300  
700  
550  
900  
tPD  
Propagation delay variation  
between the clock input and  
any QCLK_y output  
-100  
+100  
ps  
Output isolation between any fQCLK_y = 983.04MHz[k]  
60  
65  
70  
dB  
dB  
dB  
QCLK-QCLK and  
QREF-QREF outputs  
fQCLK_y = 491.52MHzk  
fQCLK_y = 245.76MHzk  
Output isolation between any fQCLK_y = 983.04MHz, 491.52MHz,  
50  
dB  
QREF/QCLK outputs  
245.76MHz; fQREF_r = 7.68MHz  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[b] The CLK, nCLK input supports 0Hz if the applied static signal has a minimum amplitude as specified by VIN, VDIFF_IN.  
[c] VIL should not be less than -0.3V and VIH should not be greater than VDD_V.  
[d] Common Mode Input Voltage is defined as the cross-point voltage.  
[e] Input = 50% duty cycle.  
[f] LVPECL outputs terminated with 50to VT = VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting),  
VDD_V – 2.0V (750mV amplitude setting), VDD_V – 2.25V (1000mV amplitude setting).  
[g] LVDS outputs terminated 100across Q, nQ.  
[h] This parameter is defined in accordance with JEDEC standard 65.  
[i] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points  
[j] All frequency dividers N are in ÷1, ÷2, ÷4 or ÷8; output amplitude setting 750mV.  
[k] Output amplitudes set to 500mV or 750mV.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 30. DCB and Phase Delay Characteristics, VDD_V = 3.3V ± 5%, TA = -40°C to +85°C [a]  
Maximu  
Symbol  
Parameter  
DCO Lock Range  
Test Conditions  
Minimum Typical  
m
Units  
fDCO  
963.04  
115  
983.04  
131  
1003.04  
MHz  
TDCB  
REF_r Delay Unit Range  
fDCO = 983.04MHz  
DLC = 1 (DLC[1:0] =  
150  
300  
450  
600  
152  
304  
456  
608  
142  
284  
426  
568  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
00)  
DLC = 2 (DLC[1:0] =  
01)  
230  
345  
460  
113  
226  
339  
452  
112  
224  
336  
448  
262  
393  
524  
134  
268  
402  
536  
128  
256  
384  
DLC = 3 (DLC[1:0] =  
10)  
DLC = 4 (DLC[1:0] =  
11)  
f
DCO = 963.04MHz  
DLC = 1 (DLC[1:0] =  
00)  
(min DCO frequency)  
DLC = 2 (DLC[1:0] =  
01)  
DLC = 3 (DLC[1:0] =  
10)  
DLC = 4 (DLC[1:0] =  
11)  
f
DCO = 1003.04MHz  
DLC = 1 (DLC[1:0] =  
00)  
(max DCO frequency)  
DLC = 2 (DLC[1:0] =  
01)  
DLC = 3 (DLC[1:0] =  
10)  
DLC = 4 (DLC[1:0] =  
11)  
512  
[b]  
TIN  
CLK_x Delay Unit  
fIN = 983.04MHz  
1017  
ps  
f1, f2  
DCO Phase Detector Frequency  
Delay unit variation  
200  
+30  
MHz  
tD  
REF_r delay unit  
variation (deviation  
from nominal,  
-30  
-20  
0
0
ps  
ps  
DLC[1:0] = 00)  
CLK_y delay unit  
variation (deviation  
from nominal)  
+20  
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[b] CLK_x clock channel delay unit is equal to 1 ÷ fIN.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Additive Clock Phase Noise Characteristics  
The 8V79S680 is a buffer device, it does not filter the phase noise on the input clock source. Phase noise caused by noise sources within the  
device can add to the input signal noise, resulting in an increased noise on the outputs (additive phase noise). Phase noise from within the part  
is not correlated with the noise on the input, therefore the root-sum-square method must be used to calculate the output phase noise:  
OUT2 = IN2  DEVICE2. As a consequence, at frequency offsets where the input phase noise IN is higher than internal noise sources,  
the effect of additive phase noise is not measurable.  
Simulations of the device phase noise performance are done with an ideal input source, however, simulation models may not account for all  
possible internal noise sources. Table 31 shows the simulation results for the 8V79S680 buffer with an ideal input source. Table 33 shows  
output phase noise measured with a low-noise input source, with one column for the measured data and a second column which de-rates the  
measured data by a factor to model the process variation. Table 33 shows that the input phase noise is the dominating factor in the measured  
data up to an offset of 100kHz. Above 100kHz, the noise floor of the device dominates the characteristics.  
Table 31. Additive Clock Phase Noise Characteristics (Simulation[a]), VDD_V = 3.3V ± 5%[b]  
Symbol  
Parameter  
Test Conditions  
1kHz offset from Carrier  
25°C  
85°C, Worst Case  
Units  
N(1k)  
QCLK_y  
Phase Noise  
-146.2  
-156.6  
-161.9  
-162.4  
-162.4  
-141.6  
-152.7  
-159.2  
-159.8  
-159.9  
-134.5  
-141.4  
-155.8  
-157.2  
-157.2  
-145.5  
-155.3  
-159.6  
-160.5  
-160.5  
-141.6  
-151.6  
-157.0  
-158.1  
-158.2  
-132.0  
-141.8  
-152.6  
-155.3  
-155.8  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
245.76MH  
z
N(10k)  
N(100k)  
N(1M)  
N(10M)  
N(1k)  
10kHz offset from Carrier  
100kHz offset from Carrier  
1MHz offset from Carrier  
10MHz offset from Carrier and Noise Floor  
1kHz offset from Carrier  
491.52MH  
z
N(10k)  
N(100k)  
N(1M)  
N(10M)  
N(1k)  
10kHz offset from Carrier  
100kHz offset from Carrier  
1MHz offset from Carrier  
10MHz offset from Carrier and Noise Floor  
1kHz offset from Carrier  
983.04MH  
z
N(10k)  
N(100k)  
N(1M)  
N(10M)  
10kHz offset from Carrier  
100kHz offset from Carrier  
1MHz offset from Carrier  
10MHz offset from Carrier and Noise Floor  
[a] Ideal input signal: rectangular clock signal with a slew rate of 5V/ns and without phase noise.  
[b] Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase noise  
specifications are applicable for all outputs active, Nx not equal, process and voltage variations included.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Figure 8. Additive Clock Phase Noise Characteristics (85°C, Worst Case Simulation Model)  
983.04MHz  
491.52MHz  
245.76MHz  
Offset (Hz)  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Table 32. Additive Clock Phase Noise Characteristics (Measured), V  
= 3.3V ± 5%, TA = -40°C to +85°C [a][b]  
DD_V  
Symbol  
Parameter  
Test Conditions  
Measured[c]  
De-Rated[d]  
Units  
(1k)  
QCLK  
Phase Noise  
245.76MH 1kHz offset from Carrier  
-141.4  
-151.7  
-157.8  
-158.6  
-158.8  
-135.3  
-145.8  
-154.2  
-157.2  
-157.6  
-131.3  
-141.2  
-149.6  
-154.5  
-155.3  
-137.2  
-149.5  
-155.5  
-156.2  
-156.3  
-128.4  
-140.5  
-149.5  
-155.4  
-156.3  
-125.7  
-138.5  
-146.5  
-152.2  
-152.5  
100  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
fs  
N
z
(10k)  
10kHz offset from Carrier  
N
(100k)  
100kHz offset from Carrier  
N
(1M)  
1MHz offset from Carrier  
N
(10M)  
10MHz offset from Carrier and Noise Floor  
1kHz offset from Carrier  
N
(1k)  
N
491.52MH  
z
(10k)  
10kHz offset from Carrier  
N
(100k)  
100kHz offset from Carrier  
N
(1M)  
1MHz offset from Carrier  
N
(10M)  
10MHz offset from Carrier and Noise Floor  
1kHz offset from Carrier  
N
(1k)  
N
983.04MH  
z
(10k)  
10kHz offset from Carrier  
N
(100k)  
100kHz offset from Carrier  
N
(1M)  
1MHz offset from Carrier  
N
(10M)  
10MHz offset from Carrier and Noise Floor  
Integration Range: 1kHz - 61.44MHz  
Integration Range: 12kHz - 20MHz  
N
tjit(Ø)  
Clock RMS Phase Jitter  
(Random)  
100  
fs  
[a] Phase noise and spurious specifications apply for device operation with QREF_r outputs inactive (no SYSREF pulses generated). Phase noise  
specifications are applicable for all outputs active, Nx not equal.  
[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a  
test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached  
under these conditions.  
[c] Measured results at the max. temperature of 85°C using an input source with a phase noise characteristics of:  
• 245.76MHz: -143.7dBc/Hz (1kHz offset), -152.5dBc/Hz (10kHz), -160.8dBc/Hz (100kHz), -172.6dBc/Hz (1MHz), -179.5dBc/Hz (10MHz).  
• 491.52MHz: -137.7dBc/Hz (1kHz offset), -147.4dBc/Hz (10kHz), -156.1dBc/Hz (100kHz), -167.6dBc/Hz (1MHz), -170.1dBc/Hz (10MHz).  
• 983.04MHz: -132.5dBc/Hz (1kHz offset), -141.4dBc/Hz (10kHz), -149.9dBc/Hz (100kHz), -161.4dBc/Hz (1MHz), -164.2dBc/Hz (10MHz).  
[d] De-rating factor applied to the characterized data at 85°C to account for worst-case process variation.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Figure 9. Additive Clock Phase Noise Characteristics (Measured), fCLK = 245.76MHz  
Characterized and de-rated for process variation  
Characterized (high temperature)  
Low phase noise input source  
Offset (Hz)  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Figure 10. Additive Clock Phase Noise Characteristics (Measured), fCLK = 491.52MHz  
Characterized and de-rated for process variation  
Characterized (high temperature)  
Low phase noise input source  
Offset (Hz)  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Figure 11. Additive Clock Phase Noise Characteristics (Measured), fCLK = 983.04MHz  
Characterized and de-rated for process variation  
Characterized (high temperature)  
Low phase noise input source  
Offset (Hz)  
Symbol  
Parameter  
Test Conditions  
Typical  
Units  
(1k)  
1kHz offset from Carrier  
-146  
-152.5  
-156  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
N
15.36MHz  
(10k)  
10kHz offset from Carrier  
100kHz offset from Carrier  
1MHz offset from Carrier  
1kHz offset from Carrier  
10kHz offset from Carrier  
100kHz offset from Carrier  
1MHz offset from Carrier  
N
[a]  
(100k)  
N
(1M)  
-156  
N
QREF_r  
Phase Noise  
(1k)  
-147.5  
-153.5  
-155.5  
-155.5  
N
c
30.72MHz  
(10k)  
N
(100k)  
N
(1M)  
N
[a] Measured results with DLC[1:0] = 00 and REF_r = 3.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Application Information  
Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)  
Figure 12 shows an example termination for the QCLK_y, QREF_r LVDS outputs. In this example, the characteristic transmission line  
impedance is 50. The termination resistor R (100) is matched to the line impedance. The termination resistor must be placed at the line  
end. No external termination resistor is required if R is an internal part of the receiver circuit. The LVDS termination in Figure 12 is applicable  
for any output amplitude setting specified in Table 7.  
Figure 12. LVDS (STYLE = 0) Output Termination  
V
DD_V  
T = 50  
R = 100  
LVDS  
AC Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)  
Figure 13 and Figure 14 show example AC terminations for the QCLK_y, QREF_r LVDS outputs. In the examples, the characteristic  
transmission line impedance is 50. In Figure 13, the termination resistor R (100) is placed at the line end. No external termination resistor  
is required if R is an internal part of the receiver circuit, which is shown in Figure 14. The LVDS terminations in both Figure 13 and Figure 14  
are applicable for any output amplitude setting specified in Table 7. The receiver input should be re-biased according to its common mode  
range specifications.  
Figure 13. LVDS (STYLE = 0) AC Output Termination  
VBIAS  
V
DD_V  
0.1µF  
0.1µF  
T = 50  
R = 100  
LVDS  
Figure 14. LVDS (STYLE = 0) AC Output Termination  
V
DD_V  
0.1µF  
0.1µF  
T = 50  
LVDS  
R = 100  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Termination for QCLK_y, QREF_r LVPECL Outputs (STYLE = 1)  
Figure 15 shows an example termination for the QCLK_y, QREF_r LVPECL outputs. In this example, the characteristic transmission line  
impedance is 50 The R1 (50) and R2 (50) resistors are matched load terminations. The output is terminated to the termination voltage  
V The V must be set according to the output amplitude setting defined in Table 7. The termination resistors must be placed close at the line  
.
T
T
end.  
Figure 15. LVPECL (STYLE = 1) Output Termination  
V = V  
- 1.50V (250 mV Amplitude)  
- 1.75V (500 mV Amplitude)  
- 2.00V (750mV Amplitude)  
- 2.25V (1000mV Amplitude)  
T
DD_V  
DD_V  
DD_V  
DD_V  
V = V  
T
V = V  
T
V
V
T
V = V  
DD_V  
T
R = 50  
R = 50  
2
1
T = 50  
LVPECL  
Package Exposed Pad Thermal Release Path  
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the  
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,  
as shown in Figure 16. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the  
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB  
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.  
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder  
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be  
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and  
dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or  
testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array  
of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended  
that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking  
inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land.  
Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations  
are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s  
Thermally/Electrically Enhance Lead-frame Base Package, Amkor Technology.  
Figure 16. Assembly for Exposed Pad Thermal Release Path - Side View (Drawing not to Scale)  
SOLDER  
SOLDER  
PIN  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Thermal Characteristics  
Table 33. Thermal Resistance for 64-VFQFN-P Package[a]  
Symbol  
Thermal Parameter  
Condition  
Value  
Unit  
0 m/s air flow  
1 m/s air flow  
2 m/s air flow  
3 m/s air flow  
4 m/s air flow  
5 m/s air flow  
22.76  
19.25  
17.70  
16.87  
16.37  
16.03  
14.33  
1.1  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
JA  
Junction to ambient  
Junction to case  
Junction to board  
JC  
JB  
[a] Standard JEDEC 2S2P multilayer PCB.  
Case Temperature Considerations  
This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air. The  
printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific  
temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to the  
PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the  
junction-to-board thermal characterization parameter (Psi-JB) to calculate the junction temperature (T ) and ensure it does not exceed the  
JB  
J
maximum allowed operating junction temperature in the Absolute Maximum Rating table.  
The junction-to-board thermal characterization parameter, is calculated using the following equation:  
JB,  
T = T + x P where:  
J
CB  
JB  
D,  
o
TJ = Junction temperature at steady state condition in ( C)  
TCB = Case temperature (Bottom) at steady state condition in ( C)  
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board  
o
measured at the top surface of the board  
PD = power dissipation (W) in desired operating configuration  
T
J
T
CB  
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from the  
IC to the PCB. It’s critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case  
temperature (T ). A good connection ensures that temperature at the exposed pad (T ) and the board temperature (T ) are relatively the  
CB  
CB  
B
same. An improper connection can lead to increased junction temperature, increased power consumption and decreased electrical  
performance. In addition, there could be long-term reliability issues and increased failure rate.  
©2017 Integrated Device Technology, Inc.  
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June 22, 2017  
8V79S680 Datasheet  
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x PD  
Table 34. Thermal Resistance for 64-VFQFN-P package[a]  
Package type  
Body size (mm)  
64-VFQFN-P  
9mmx9mmx0.85mm  
6.00mm x 6.00mm  
8x8 Matrix  
ePad size (mm)  
Thermal Via  
1.1 C/W  
JB  
CB  
D
o
T
P
85 C  
[b]  
1.766 W  
[a] Standard JEDEC 2S2P multilayer PCB.  
[b] Table 24, test case 6.  
o
o
o
For the variables above, the junction temperature is T = T + x P = 85 C + 1.1 C/W x 1.766W = 86.9 C. Since this operating junction  
J
CB  
JB  
D
o
temperature is below the maximum operating junction temperature of 125 C, there are no long term reliability concerns. In addition, since the  
junction temperature at which the device was characterized using forced convection is 87.6 C, this device can function without the  
o
degradation of the specified AC or DC parameters.  
©2017 Integrated Device Technology, Inc.  
45  
June 22, 2017  
8V79S680 Datasheet  
Package Drawings  
Figure 17. Package Drawings  
©2017 Integrated Device Technology, Inc.  
46  
June 22, 2017  
8V79S680 Datasheet  
Recommended Land Pattern  
Figure 18. Recommended Land Pattern  
©2017 Integrated Device Technology, Inc.  
47  
June 22, 2017  
8V79S680 Datasheet  
Ordering Information  
Orderable Part Number  
Package  
MSL Rating  
Shipping Packaging  
Temperature  
8V79S680NLGI  
8V79S680NLGI8  
3
3
Tray  
RoHS 6/6 64-VFQFN-P  
-40°C to +85°C  
Tape and Reel  
Marking Diagram  
IDT  
8V79S680NLGI  
#YYWW$  
LOT C00  
Glossary  
Abbreviation  
Description  
Index x  
Index y  
Index r  
Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D.  
Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D.  
Denominates a QREF output and associated configuration bits. Range: A0, A1, A2, B0, B1, C0, C1, D.  
V
Denominates voltage supply pins. Range: V  
V V V V  
DD_QCLKA, DD_QREFA01, DD_QREFA2, DD_QCLKB, DD_QREFB,  
DD_V  
V
, V  
V
V
V
V
DD_QCLKC DD_QREFC, DD_QCLKD, DD_QREFD, DD_CLK, DD_REF.  
[...]  
Index brackets describe a group associated with a logical function or a bank of outputs.  
List of discrete values.  
{…}  
©2017 Integrated Device Technology, Inc.  
48  
June 22, 2017  
8V79S680 Datasheet  
Revision History  
Date  
Description of Change  
▪ Updated the description of BIAS_TYPE[1] in Table 10  
▪ Updated the Package Drawings  
June 22, 2017  
August 4, 2016  
Initial release.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.idt.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without  
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any  
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-  
lectual property rights of IDT or any third parties.  
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably  
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.  
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of  
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.  

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