8V89308ANLGI_技术文档

Jitter Attenuator & FemtoClock^®Multiplier

IDT8V89308I

DATA SHEET

General Description

Features

The IDT8V89308I is a PLL based synchronous multiplier specifically

designed for applications utilizing Broadcom PHYs and Switches.

This high performance device is optimized for Ethernet / SONET /

PDH frequency translation and clock jitter attenuation. The device

contains two internal frequency multiplication stages that are

cascaded in series. The first stage is a low bandwidth PLL that is

optimized to provide reference clock jitter attenuation. The second

stage is a FemtoClock^®frequency multiplier that provides the low

jitter, high frequency Ethernet output clock that easily meets Gigabit

and 10 Gigabit Ethernet jitter requirements. Pre-divider and output

divider multiplication ratios are selected using device selection

control pins. The multiplication ratios are optimized to support most

common clock rates used in Ethernet, SONET, PDH applications.

IDT8V89308I requires the use of an external, inexpensive

fundamental mode crystal and uses external passive loop filter

components which allows configuration of the PLL loop bandwidth

and damping characteristics. The device is packaged in a

space-saving 32-VFQFN package and supports industrial

temperature range.

ꢀ Two LVPECL output pairs

Each output supports independent frequency selection at 25MHz,

125MHz and 156.25MHz

ꢀ One differential input supports the following input types: LVPECL,

LVDS

ꢀ Accepts input frequencies 8kHz, 25MHz,125MHz and 155.52MHz

ꢀ First stage PLL bandwidth can be optimized for jitter attenuation

and reference tracking using external loop filter connection

ꢀ FemtoClock frequency multiplier provides low jitter, high

frequency output

ꢀ Absolute pull range: 50ppm

ꢀ FemtoClock VCO frequency: 625MHz

ꢀ RMS phase jitter @ 25MHz, using a 25MHz crystal

(12kHz – 5MHz): 0.238ps (typical), 0.30ps (maximum)

ꢀ RMS phase jitter @ 125MHz, using a 25MHz crystal

(12kHz – 20MHz): 0.223ps (typical), 0.30ps (maximum)

ꢀ RMS phase jitter @ 156.25MHz, using a 25MHz crystal

(12kHz – 20MHz): 0.223ps (typical), 0.30ps (maximum)

ꢀ 3.3V supply voltage

ꢀ -40°C to 85°C ambient operating temperature

ꢀ Available in lead-free (RoHS 6) package

Pin Assignment

32 31 30 29 28 27 26 25

1

2

3

4

5

LF1

VEE

24

23

22

21

20

LF0

nQB

QB

ISET

VCCO

nQA

VEE

nc

VCC

6

7

8

QA

19

18

17

RESERVED

VEE

_

ODASEL 0

VEE

9

10 11 12 13 14 15 16

IDT8V89308I

32 Lead VFQFN

5mm x 5mm x 0.925mm package body

NL Package

Top View

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Block Diagram

Loop

Filter

25MHz

Output Divider

QA

Pullup

PDSEL_[2:0]

(default)

00 = 25

nQA

01 = 5

10 = 4

Phase

Input

Pre-Divider

Detector

2

Pulldown

ODASEL_[1:0]

XTAL

Oscillator

FemtoClock PLL

625MHz

CLK1

000 = 1

Charge

Pump

nCLK1

100 = 3125

110 = 15625

111 = 19440

Output Divider

Feedback Divider

÷3125

QB

(default)

00 = 25

01 = 5

10 = 4

nQB

Jitter Attenuation PLL

2

Pulldown

ODBSEL_[1:0]

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Table 1. Pin Descriptions

Number

Name

Type

Description

Analog

Input/Output

1, 2

LF1, LF0

Loop filter connection node pins. LF0 is the output. LF1 is the input.

Charge pump current setting pin.

Analog

Input/Output

3

ISET

4, 8, 18, 24

6, 12, 27

7

V_EE

V_CC

Power

Negative supply pins.

Core supply pins.

RESERVED

Reserved

Reserved pin. Do not connect.

9,

10,

11

PDSEL_2,

PDSEL_1,

PDSEL_0

Input

Pullup

Pre-divider select pins. LVCMOS/LVTTL interface levels. See Table 3A.

13

V_CCA

Power

Input

Analog supply pin.

14,

15

ODBSEL_1,

ODBSEL_0

Frequency select pins for Bank B output. See Table 3B.

LVCMOS/LVTTL interface levels.

Pulldown

16,

17

ODASEL_1,

ODASEL_0

Frequency select pins for Bank A output. See Table 3B.

LVCMOS/LVTTL interface levels.

Input

19, 20

21

QA, nQA

V_CCO

Output

Power

Output

Differential Bank A clock outputs. LVPECL interface levels.

Output supply pin.

22, 23

QB, nQB

Differential Bank B clock outputs. LVPECL interface levels.

Pullup/

Pulldown

25

26

nCLK1

CLK1

Input

Inverting differential clock input. V_CC/2 bias voltage when left floating.

Non-inverting differential clock input.

Pulldown

30,

31

XTAL_OUT,

XTAL_IN

Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

32

V_CCX

nc

Power

Power supply pin for charge pump.

No connect.

5, 28, 29

Unused

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

4

R_PULLUP

51

k

R_PULLDOWNInput Pulldown Resistor

k

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Function Tables

Table 3A. Pre-Divider Selection Function Table

Table 3B. Output Divider Function Table

Inputs

ODxSEL_1

Inputs

PDSEL_2

PDSEL_1

PDSEL_0

Pre-Divider Value

ODxSEL_0

Output Divider Value

0

1

0

1

0

1

3125

0

1

0

1

0

25 (default)

5

4

15625

19440 (default)

Table 3C. Frequency Function Table

Input

Frequency

(MHz)

Crystal

Frequency

(MHz)

FemtoClock

Feedback

Divider Value

Pre-Divider

Value

FemtoClock VCO

Frequency (MHz)

Output Divider

Output Frequency

(MHz)

Value

25

5

0.008

25

1

25

625

25

125

1

4

156.25

25

3125

15625

19440

25

5

25

125

25

4

156.25

25

125

25

5

125

4

156.25

25

155.52

25

5

125

4

156.25

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_CC

3.63V

Inputs, V_I

XTAL_IN

0V to V_CC

Other Inputs

-0.5V to V_CC+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, _JA

33.1C/W (0 mps)

-65C to 150C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. LVPECL Power Supply DC Characteristics, V_CC= V_CCO= V_CCX= 3.3V ± 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

V_CC

Units

V

V_CC

Core Supply Voltage

V_CCA

V_CCO

V_CCX

I_EE

Analog Supply Voltage

Output Supply Voltage

Charge Pump Supply Voltage

Power Supply Current

Analog Supply Current

V_CC– 0.20

3.135

3.3

V

3.3

3.465

200

V

3.135

3.3

V

mA

I_CCA

20

Table 4B. LVCMOS/LVTTL DC Characteristics, V_CC= V_CCO= V_CCX= 3.3V ± 5%, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

V_CC+ 0.3

0.8

Units

V_IH

V_IL

Input High Voltage

2

V

Input Low Voltage

-0.3

ODASEL_[1:0],

ODBSEL_[1:0]

V

_CC= V_IN= 3.465V

V_CC= V_IN= 3.465V

_CC= 3.465V, V_IN= 0V

150

10

µA

Input

High Current

I_IH

PDSEL_[2:0]

ODASEL_[1:0],

ODBSEL_[1:0]

V

-10

Input

Low Current

I_IL

PDSEL_[2:0]

V_CC= 3.465, V_IN= 0V

-150

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Table 4C. Differential DC Characteristics, V_CC= V_CCO= V_CCX= 3.3V ± 5%, T_A= -40°C to 85°C

Symbol Parameter

I_IHInput High Current

Test Conditions

V_CC= V_IN= 3.465V

_CC= 3.465V, V_IN= 0V

Minimum

Typical

Maximum

Units

µA

V

CLK1, nCLK1

CLK1

150

V

-10

-150

0.15

V_EE

I_IL

Input Low Current

nCLK1

V_CC= 3.465V, V_IN= 0V

V_PP

Peak-to-Peak Input Voltage

1.3

V_CMR

Common Mode Input Voltage; NOTE 1

V_CC– 0.85

V

Common mode voltage is defined as the crossing point.

Table 4D. LVPECL DC Characteristics, V_CC= V_CCO= V_CCX= 3.3V ± 5%, V_EE= 0V, T_A= -40°C to 85°C

Symbol

V_OH

Parameter

Test Conditions

Minimum

V_CCO– 1.10

V_CCO– 2.0

0.6

Typical

Maximum

V_CCO– 0.75

V_CCO– 1.6

1.0

Units

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

V

V_OL

V_SWING

NOTE 1: Outputs terminated with 50 to V_CCO– 2V. See Parameter Measurement Information section, 3.3V Output Load Test Circuit.

AC Electrical Characteristics

Table 5. AC Characteristics, V_CC= V_CCO= V_CCX= 3.3V ± 5%, T_A= -40°C to 85°C

Symbol

f_IN

Parameter

Test Conditions

Minimum

0.008

25

Typical

Maximum

155.52

Units

MHz

Input Frequency

Output Frequency

f_OUT

156.25

RMS Phase Jitter, (Random),

NOTE 1

f_OUT= 25MHz, 25MHz crystal,

Integration Range: 12kHz – 5MHz

tjit(Ø)

0.238

0.223

0.3

ps

RMS Phase Jitter, (Random),

NOTE 1

f_OUT= 125MHz, 25MHz crystal,

Integration Range: 12kHz – 20MHz

RMS Phase Jitter, (Random),

NOTE 1

f_OUT= 156.25MHz, 25MHz crystal,

Integration Range: 12kHz – 20MHz

tjit(pk-pk)

tsk(o)

t_R/ t_F

odc

Peak-to-Peak Jitter

Output Skew; NOTE 2, 3

Output Rise/Fall Time

Output Duty Cycle

1e-12 BER

25

ps

%

20% to 80%

140

48

400

52

XO & FemtoClock PLL Lock

Time; NOTE 4

t_LOCK

6

S

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device

is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal

equilibrium has been reached under these conditions.

NOTE: Characterized using input frequency of 8kHz, QA/nQA and QB/nQB at the same frequency using 3^rdorder loop filter of 10Hz

bandwidth. Refer to application schematics.

NOTE 1: Refer to the Phase Noise Plot.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential

cross points.

NOTE 4: Lock Time measured from power-up to stable output frequency.

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IDT8V89308I Data Sheet

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Typical Phase Noise (25MHz)

Offset Frequency (Hz)

Typical Phase Noise (125MHz)

Offset Frequency (Hz)

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Typical Phase Noise (156.25MHz)

Offset Frequency (Hz)

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Parameter Measurement Information

2V

V

CC

V

CC,

SCOPE

V

nCLK[0:1]

CLK[0:1]

CCO

V

Qx

CCX

V_PP

V

Cross Points

CCA

V_CMR

nQx

V

EE

V_EE

-1.3V±0.165V

3.3V LVPECL Output Load AC Test Circuit

Differential Input Level

Phase Noise Plot

nQx

Qx

nQy

Qy

tsk(o)

Offset Frequency

f₁

f₂

RMS Phase Jitter =

1

*

Area Under Curve Defined by the Offset Frequency Markers

2 * * ƒ

Output Skew

RMS Phase Jitter

nQA, nQB

QA, QB

nQA, nQB

80%

t_R

t_PW

t_PERIOD

V_SWING

20%

QA, QB

t_PW

t_F

odc =

x 100%

t_PERIOD

Output Duty Cycle/Pulse Width/Period

Output Rise/Fall Time

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Parameter Measurement Information, continued

XO & FemtoClock PLL Lock Time

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

LVPECL Outputs

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

All unused LVPECL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V_REF= V_CC/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the V_REFin the center of the input voltage

swing. For example, if the input clock swing is 2.5V and V_CC= 3.3V,

R1 and R2 value should be adjusted to set V_REFat 1.25V. The values

below are for when both the single ended swing and V_CCare at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Though some

of the recommended components might not be used, the pads should

be placed in the layout. They can be utilized for debugging purposes.

The datasheet specifications are characterized and guaranteed by

using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL and other differential

signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figures 2A to 2C show interface examples for the CLK

/nCLK input with built-in 50 terminations driven by the most

common driver types. The input interfaces suggested here are

examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

3.3V

R3

125Ω

R4

125Ω

Zo = 50Ω

CLK

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

LVPECL

nCLK

Input

R1

R2

Differential

Input

50Ω

LVPECL

R1

R2

84Ω

R2

50Ω

Figure 2A. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 2B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

3.3V

Zo = 50Ω

CLK

R1

100Ω

nCLK

Zo = 50Ω

Receiver

LVDS

Figure 2C. CLK/nCLK Input Driven by a 3.3V LVDS Driver

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 3A and 3B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

3.3V

R3

125Ω

R4

125Ω

3.3V

Z

_o= 50Ω

3.3V

+

_

Z_o= 50Ω

+

_

Input

LVPECL

Z_o= 50Ω

LVPECL

Input

Z_o= 50Ω

R1

R2

50Ω

R1

84Ω

R2

84Ω

V_CC- 2V

1

RTT =

* Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

Figure 3A. 3.3V LVPECL Output Termination

Figure 3B. 3.3V LVPECL Output Termination

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 4. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Table 6. Crystal Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Fundamental

25

Maximum

Units

Mode of Oscillation

Frequency

f_N

f_T

f_S

MHz

ppm

⁰C

Frequency Tolerance

Frequency Stability

Operating Temperature Range

Load Capacitance

Shunt Capacitance

Pullability Ratio

±20

±30

85

±20

-40

C_L

10

4

12

pF

C_O

pF

C_O/ C₁

F_{L_3OVT}

220

240

3^rdOvertone F_L

200

ppm

F_{L_3OVT_spur}

3^rdOvertone F_LSpurs

s

ESR

Equivalent Series Resistance

Drive Level

Aging @ 25 ⁰C

50

1



mW

ppm

±3 per year

Application Schematic Example

Figure 5 (next page) shows an example of IDT8V89308I application

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for a wide range of noise frequencies.

This low-pass filter starts to attenuate noise at approximately 10kHz.

If a specific frequency noise component is known, such as switching

power supplies frequencies, it is recommended that component

values be adjusted and if required, additional filtering be added.

Additionally, good general design practices for power plane voltage

stability suggests adding bulk capacitance in the local area of all

devices.

schematic. In this example, the device is operated at V_CC= V_CCX

V_CCA= V_CCO= 3.3V. A 3-pole filter is used for additional spur

=

reduction. As with any high speed analog circuitry, the power supply

pins are vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The 8V89308I

provides separate power supplies to isolate any high switching noise

from coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1uF capacitor in each power pin filter should be placed on the

device side. The other components can be on the opposite side of the

PCB.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure that the logic control inputs are

properly set.

IDT8V89308ANLGI REVISION A JUNE 18, 2012

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IDT8V89308I Data Sheet

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Logic Control Input Examples

Set Logic

Input to

'1'

Set Logic

Input to

'0'

V CC

VCC

V CC

RU1

1K

RU2

Not Install

R1

125

R2

125

To Logi c

Input

pins

To L ogic

In put

pi ns

Zo = 50

CLK

RD1

Not Inst al l

RD2

1K

nCLK

LV PEC L D r iv e r

R3

84

R4

84

3. 3 V

FB1

m uRata, B LM18BB221SN1

3.3V

XTAL_OU T

C2

C4

C1

TUNE

C3

10uF

R5

13 3

R6

133

25MHz

1uF

1u F

X1, 10pF

Zo = 50 Ohm

+

-

XTA L_I N

C5

TUNE

3. 3 V

V CC

FB2

VCCO

R7

82.5

R8

82. 5

R9

10

muRata, BLM18BB 221SN1

C7

V CCX

0.1u

C8

C6

0. 1uF

C9

10 u

1uF

LVPECL

C10

Termination

0. 1 u

U1

Loop Filter

VCC = VCCO= 3.3V

R10

1

24

LF 0

LF1

LF 1

LF 0

IS ET

VEE

NC

VCC

RE SER VED

VEE

V EE

2

23

nQB

QB

nQB

QB

3

4

5

6

7

8

22

21

20

19

18

17

Rs

40 0 k

2.2M

VCCO

nQA

QA

V EE

ODA SEL_0

nQA

QA

Cp

2.2nF

C11

3.3nF

Zo = 50 Ohm

Cs

1uF

+

-

ODASE L_0

Zo = 50 Ohm

C12

0. 1u

R11

10K

R12

50

R13

50

3. 3V

F B3

muRat a, BLM18BB 221SN1

C14

C13

0. 1uF

R14

50

LVPECL

Optional

Y-Termination

10 u F

R15

10

3. 3V

VCCA

VCC

F B4

V CC

muRat a, BLM18BB221SN1

C15

0. 1 u

C16

10u

C1 8

10uF

C17

0. 1uF

C19

0. 1 u

Figure 5. IDT8V89308I Application Schematic

IDT8V89308ANLGI REVISION A JUNE 18, 2012

16

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Power Considerations

This section provides information on power dissipation and junction temperature for the IDT8V89308I.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the IDT8V89308I is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

ꢀ

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 200mA = 693mW

Power (outputs)_MAX= 31.55mW/Loaded Output pair

If all outputs are loaded, the total power is 2 * 31.55mW = 63.1mW

Total Power__MAX(3.465V, with all outputs switching) = 693mW + 63.1mW = 756.1mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device.

The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 33.1°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.756W * 33.1°C/W = 110°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance _JAfor 32 Lead VFQFN, Forced Convection

_JAby Velocity

Meters per Second

0

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

IDT8V89308ANLGI REVISION A JUNE 18, 2012

17

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.

LVPECL output driver circuit and termination are shown in Figure 6.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 6. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of

V_CCO– 2V.

ꢀ

For logic high, V_OUT= V_{OH_MAX}= V_{CCO_MAX}– 0.75V

(V_{CCO_MAX}– V_{OH_MAX}) = 0.75V

For logic low, V_OUT= V_{OL_MAX}= V_{CCO_MAX}– 1.6V

(V_{CCO_MAX}– V_{OL_MAX}) = 1.6V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V_{OH_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) = [(2V – (V_{CCO_MAX}– V_{OH_MAX}))/R_L] * (V_{CCO_MAX}– V_{OH_MAX}) =

[(2V – 0.75V)/50] * 0.75V = 18.75mW

Pd_L = [(V_{OL_MAX}– (V_{CCO_MAX}– 2V))/R_L] * (V_{CCO_MAX}– V_{OL_MAX}) = [(2V – (V_{CCO_MAX}– V_{OL_MAX}))/R_L]* (V_{CCO_MAX}– V_{OL_MAX}) =

[(2V – 1.6V)/50] * 1.6V = 12.80mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW

IDT8V89308ANLGI REVISION A JUNE 18, 2012

18

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Reliability Information

Table 8. _JAvs. Air Flow Table for a 32 Lead VFQFN

_JAvs. Air Flow

Meters per Second

0

1

3

Multi-Layer PCB, JEDEC Standard Test Boards

33.1°C/W

28.1°C/W

25.4°C/W

Transistor Count

The transistor count for IDT8V89308I is: 22,280

IDT8V89308ANLGI REVISION A JUNE 18, 2012

19

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

32 Lead VFQFN Package Outline and Package Dimensions

IDT8V89308ANLGI REVISION A JUNE 18, 2012

20

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Ordering Information

Table 9. Ordering Information

Part/Order Number

8V89308ANLGI

8V89308ANLGI8

Marking

IDT8V89308ANLGI

Package

“Lead-Free” 32 Lead VFQFN

Shipping Packaging

Tray

2500 Tape & Reel

Temperature

-40C to 85C

NOTE: Parts that are ordered with an "G" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial. and industrial temperatures. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

IDT8V89308ANLGI REVISION A JUNE 18, 2012

21

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

Revision History Sheet

Rev

Table

Page

Description of Change

Date

21

Deleted page 21, “Option 2 of NL/NLG32 package outline.” Only Option 1 is

applicable to this device.

A

6/18/2012

IDT8V89308ANLGI REVISION A JUNE 18, 2012

22

IDT8V89308I Data Sheet

JITTER ATTENUATOR & FEMTOCLOCK^®MULTIPLIER

We’ve Got Your Timing Solution

6024 Silver Creek Valley Road Sales

Technical Support

800-345-7015 (inside USA)

netcom@idt.com

San Jose, California 95138

+408-284-8200 (outside USA) +480-763-2056

Fax: 408-284-2775

www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT

product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.


型号：	8V89308ANLGI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Jitter Attenuator & FemtoClock Multiplier 衰减器 PC 电信电信集成电路
文件：	总23页 (文件大小：462K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V89308ANLGI [IDT]

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