91305AG [IDT]

Clock Driver;


型号：	91305AG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Clock Driver
文件：	总8页 (文件大小：89K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS91305

Integrated

Circuit

Systems, Inc.

High Performance Communication Buffer

General Description

Features

The ICS91305 is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the REF input with

theCLKOUTsignal. Itisdesignedtodistributehighspeed

clocks in communication systems operating at speeds

from 10 to 133 MHz.

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread

Spectrum applications.

•

Less than 200 ps Jitter between outputs

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 8 pin 150 mil SOIC & 173 mil

TSSOP packages

ICS91305 is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

theinputofthePLL. Sincetheskewbetweentheinputand

outputislessthan+/-350pS, thepartactsasazerodelay

buffer.

•

3.3V 10ꢀ operation

The ICS91305 comes in an eight pin 150 mil SOIC

package. It has five output clocks. In the absence of REF

input, will be in the power down mode. In this mode, the

PLL is turned off and the output buffers are pulled low.

Powerdownmodeprovidesthelowestpowerconsumption

for a standby condition.

Block Diagram

Pin Configuration

REF

CLK2

CLK1

GND

CLKOUT

CLK4

VDD

CLK3

8 pin SOIC & TSSOP

0092H—12/02/08

ICS91305

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

Input reference frequency, 5V tolerant input.

Buffered clock output

REF²

CLK2³

CLK1³

GND

OUT

PWR

OUT

PWR

OUT

Buffered clock output

Ground

CLK3³

Buffered clock output

VDD

Power Supply (3.3V)

CLK4³

CLKOUT³

Buffered clock output

Buffered clock output. Internal feedback on this pin

Notes:

1. Guaranteed by design and characterization. Not subject to 100ꢀ test.

2. Weakpull-down

3. Weak pull-down on all outputs

0092H—12/02/08

ICS91305

Absolute Maximum Ratings

SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to V_DD+ 0.5 V

Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V

Ambient OperatingTemperature . . . . . . . . . . 0°C to +70°C

StorageTemperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These

ratingsarestressspecificationsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsabovethose

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

Electrical Characteristics at 3.3V

V_DD= 3.0 – 3.6V, T_A= 0 –70°C unless otherwise stated

DC Characteristics

PARAMETER

Input Low Voltage

Input High Voltage

Input Low Current

Input High Current

Output Low Voltage

SYMBOL

TEST CONDITIONS

MIN

2.0

TYP

MAX

0.8

UNITS

= 0V

0.10

0.25

2.9

50.0

100.0

0.4

µA

= V

= 25mA

Output High Voltage

2.4

Power Down Supply

Current

REF = 0 MHz

0.3

50.0

40.0

µA

Unloaded oututs at 66.66 MHz

Supply Current

30.0

SEL inputs at V or GND

Notes:

1. Guaranteed by design and characterization. Not subject to 100ꢀ test.

2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.

3. Duty cycle measured at 1.4V.

4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.

0092H—12/02/08

ICS91305

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

100.00

(10)

7.5

(133)

(MHz)

Output period

With CL = 30pF

100.00

(10)

7.5

(133)

(MHz)

Input period

With CL = 30pF

Duty Cycle¹

Dt1

Dt2

Measured at 1.4V; CL = 30pF

40.0

ꢀ

Measured at VDD/2 Fout <66.6MHz

Measured between 0.8V and 2.0V:

CL=30pF

Rise Time¹

Fall Time¹

Rise Time¹

Fall Time¹

tr1

tf1

tr1

tf1

1.2

1.5

Measured between 2.0V and 0.8V;

CL=30pF

Measured between 0.8V and 2.0V:

CL=5pF

Measured between 2.0V and 0.8V;

CL=5pF

Delay, REF Rising

Edge to CLKOUT

Rising Edge^{1, 2}

Dr1

Measured at 1.4V

350

Output to Output

Skew¹

All outputs equally loaded,

CL = 20pF

Tskew

250

700

200

1.0

100

Device to Device

Skew¹

Measured at VDD/2 on the CLKOUT pins

of devices

Tdsk-Tdsk

Cycle to Cycle

Jitter¹

Tcyc-Tcyc Measured at 66.66 MHz, loaded outputs

Stable power supply, valid clock presented

on REF pin

PLL Lock Time¹

tLOCK

Jitter; Absolute

Jitter¹

@ 10,000 cycles

Tjabs

-100

CL = 30pF

@ 10,000 cycles

CL = 30pF

Jitter; 1 - Sigma¹

Tj1s

Notes:

1. Guaranteed by design and characterization. Not subject to 100ꢀ test.

2. REF input has a threshold voltage of 1.4V

3. All parameters expected with loaded outputs

0092H—12/02/08

ICS91305

Output to Output Skew

The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL.Since CLKOUT is one

of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,

zero phase difference will maintained from REF to all outputs.

If applications requiring zero output-output skew, all the outputs must equally loaded.

If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it;and if the CLK(1-4) is more loaded

than CLKOUT, CLK(1-4) will lag the CLKOUT.

Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause

them to have different rise times and different times crossing the measurement thresholds.

REF input and

all outputs

loadedEqually

REF input and CLK(1-4)

outputsloadedequally,with

CLKOUT loaded More.

REF input and CLK(1_4)

outputsloadedequally,with

CLKOUT loaded Less.

Timing diagrams with different loading configurations

0092H—12/02/08

ICS91305

150 mil (Narrow Body) SOIC

In Millimeters

In Inches

SYMBOL

COMMON DIMENSIONS COMMON DIMENSIONS

MIN

1.35

0.10

0.33

0.19

MAX

1.75

0.25

0.51

0.25

MIN

MAX

.0688

.0098

.020

.0532

.0040

.013

.0075

SEE VARIATIONS

INDEX

AREA

.0098

SEE VARIATIONS

3.80

4.00

.1497

0.050 BASIC

.1574

1.27 BASIC

h x 45°

5.80

0.25

0.40

6.20

0.50

1.27

.2284

.010

.016

.2440

.020

.050

SEE VARIATIONS

0°

8°

0°

8°

SEATING

PLANE

VARIATIONS

D mm.

D (inch)

MIN

4.80

MAX

5.00

MIN

MAX

.1968

.10 (.004)

.1890

Reference Doc.: JEDEC Publication 95, MS-012

10-0030

150 mil (Narrow Body) SOIC

Ordering Information

91305yMLFT

Example:

XXXX y M LF T

Designation for tape and reel packaging

Lead Free, ROHS Compliant (Optional)

Package Type

M = SOIC

Revision Designator (will not correlate with datasheet revision)

Device Type

0092H—12/02/08

ICS91305

4.40 mm. Body, 0.65 mm. Pitch TSSOP

(173 mil) (25.6 mil)

In Millimeters

COMMON DIMENSIONS

In Inches

COMMON DIMENSIONS

SYMBOL

MIN

0.05

0.80

0.19

0.09

MAX

1.20

0.15

1.05

0.30

0.20

MIN

.002

.032

.007

.0035

MAX

.047

.006

.041

.012

.008

INDEX

AREA

SEE VARIATIONS

6.40 BASIC

SEE VARIATIONS

0.252 BASIC

4.30

0.65 BASIC

0.45

SEE VARIATIONS

0°

4.50

.169

.177

0.0256 BASIC

.030

SEE VARIATIONS

0.75

.018

8°

0.10

0°

8°

.004

aaa

VARIATIONS

D mm.

D (inch)

MIN

2.90

MAX

3.10

MIN

.114

MAX

.122

Reference Doc.: JEDEC Publication 95, MO-153

10-0035

- C -

SEATING

PLANE

aaa

Ordering Information

91305yGLFT

Example:

XXXX y G LF T

Designation for tape and reel packaging

Lead Free, RoHS Compliant (Optional)

Package Type

G = TSSOP

Revision Designator (will not correlate with datasheet revision)

Device Type

0092H—12/02/08

ICS91305

Revision History

Rev. Issue Date Description

Page #

6-7

8/6/2007 Updated Rise/Fall Time.

12/2/2008 Removed ICS prefix from ordering information

0092H—12/02/08

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