9248BF-102LF [IDT]
Clock Generator;
| 型号： | 9248BF-102LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总10页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-102
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6
Recommended Application:
Pin Configuration
Motherboard Single chip clock solution for Pentium II/III and
K6 processors, using SIS540/SIS630 style chipset
Output Features:
•
•
•
•
•
3- CPUs @ 2.5/3.3V, up to 166MHz.
14 - SDRAM @ 3.3V, up to166MHz.
7- PCI @3.3V,
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz).
•
2- REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I2C read back.
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I2C programming.
•
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
•
Uses external 14.318MHz crystal
Skew Specifications:
•
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Block Diagram
Functionality
CPU
(MHz)
66.82
100.23
150.34
133.64
66.82
100.23
100.23
133.64
66.82
83.33
90.00
95.00
95.00
112.01
166.00
166.00 166.50
SDRAM PCICLK
REF
FS3 FS2 FS1 FS0
(MHz)
100.20
100.00
100.00
100.00
133.00
133.33
150.00
133.10
66.75
(MHz)
33.41
33.41
37.59
33.41
33.41
33.41
37.59
33.41
33.41
27.78
30.00
31.67
31.67
37.34
27.67
27.67
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
83.30
90.00
95.00
126.67
112.00
111.00
0317A—03/20/02
ICS9248-102
General Description
Power Groups
VDDREF = REF [1:0], X1, X2
The ICS9248-102 is the single chip clock solution for
Desktop/Notebook designs using the SIS 540/630 style
chipset. It provides all necessary clock signals for such a
system.
VDDPCI = PCICLK_F, PCICLK [9:0]
VDDSDR = SDRAM [11:0], supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLIOAPIC = IOAPIC_F
VDDLCPU = CPUCLK_F [2:1]
SpreadspectrummaybeenabledthroughI2Cprogramming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
102
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
SerialprogrammingI2Cinterfaceallowschangingfunctions,
stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 6, 15, 19, 27,
30, 36, 42
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
14.318 MHz reference clock.
VDD
PWR
REF0
FS3
OUT
IN
2
Frequency select pin.
3, 10, 16, 22, 33,
GND
PWR
Ground pin for 3V outputs.
39, 44
4
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
5
OUT
IN
FS1
7
PCICLK0
FS2
OUT
IN
PCI clock outputs.
Frequency select pin.
8
PCICLK1
PCICLK [2:6]
OUT
OUT
PCI clock outputs.
9, 11, 12, 13, 14
41, 40, 38, 37,
35, 34, 32, 31,
29, 28, 21, 20,
18, 17
PCI clock outputs.
SDRAM
OUT
SDRAM clock outputs
23
SDATA
SCLK
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Voltage select 2.5V when high - 3.3V when low
Clock output for super I/O/USB default is 24MHz
Frequency select pin.
24
CPU2.5_3.3#
24_48MHz
FS0
IN
25
OUT
IN
26
48MHz
OUT
OUT
PWR
OUT
48MHz output clock
46, 45, 43
CPUCLK [0:2]
VDDLCPU
REF0
CPU clock outputs.
47
48
Power pin for the CPUCLKs. 2.5V
14.318 MHz reference clock.
2
ICS9248-102
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
D3(H)
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
3
ICS9248-102
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPU
PWD
Bit7 Bit2 Bit6 Bit5 Bit4
SDRAM
100.20
100.00
100.00
100.00
133.00
133.33
150.00
133.10
66.75
PCI
SS%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
0 to-0.5%
0 to-0.5%
±0.25%
0 to-0.5%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.82
100.23
150.34
133.64
66.82
100.23
100.23
133.64
66.82
33.41
33.41
37.59
33.41
33.41
33.41
37.59
33.41
33.41
27.78
30.00
31.67
31.67
37.34
27.67
27.67
35.33
33.33
32.08
33.33
37.50
31.25
35.00
33.3
83.33
90.00
95.00
83.30
90.00
95.00
95.00
126.67
112.00
111.00
166.50
100.00
100.00
96.25
112.01
166.00
166.00
66.66
100.00
96.25
00001
Note1
Bit 7, 2,
Bit 6:4
133.33
75.00
83.34
100.00
100.00
125.01
140.00
133.33
147.00
153.36
120.00
138.01
140.00
145.05
147.59
160.01
105.00
133.33
110.25
115.02
120.00
138.01
140.00
145.05
147.59
160.01
36.75
38.34
30.00
34.50
35.00
36.26
36.90
26.67
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 7, 2, 6:4
0 - Normal
Bit 3
Bit 1
Bit 0
0
1
0
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback for Bits 7, 2, 6:4 indicate the revision code.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
4
ICS9248-102
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
(CPU2.5_3.3#)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
SEL24_48#
Bit 7
-
1
(48MHz when set to 0)
(24MHz when set to 1)
Reserved
Reserved
Reserved
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Reserved
14
13
12
11
9
8
7
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
43
45
46
-
1
1
1
1
1
1
1
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
24_48MHz
48MHz
SDRAM13
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM 7 (Act/Inact)
SDRAM 6 (Act/Inact)
SDRAM 5 (Act/Inact)
SDRAM 4 (Act/Inact)
SDRAM 3 (Act/Inact)
SDRAM 2 (Act/Inact)
SDRAM 1 (Act/Inact)
SDRAM 0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
25
26
41
40
38
37
35
34
1
1
1
1
1
1
1
1
32
31
29
28
21
20
18
17
1
1
1
1
1
1
1
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
Reserved
Reserved
FS3#
FS2#
FS1#
FS0#
REF1 (Act/Inact)
REF0 (Act/Inact)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
48
2
1
1
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2.Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
5
ICS9248-102
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
102 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
6
ICS9248-102
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature. . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Supply Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
V
IDD
180
mA
mA
MHz
pF
IDDL
Fi
CL = 0 pF; Select @ 66M
VDD = 3.3 V;
30
Input frequency
Input Capacitance1
CIN
Logic Inputs
5
45
3
CINX
Ttrans
Ts
X1 & X2 pins
27
1
ps
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From = 3.3 V to 1% target Freq
ms
ms
ms
ns
TSTAB
3
4
TCPU-PCI VT = 1.5 V;
2.58
1Guaranteed by design, not 100% tested in production.
7
ICS9248-102
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
10
2
TYP MAX UNITS
RDSP2A VO = VDD*(0.5) Output P
RDSN2A VO = VDD*(0.5) Output P
VOH2B IOH = -12.0 mA
20
20
Ω
Ω
V
VOL2B IOL = 12 mA
0.4
-19
V
IOH2B
IOL2B
tr2A
VOH = 1.7 V
mA
mA
ns
ns
%
VOL = 0.7 V
19
0.4
0.4
45
VOL =0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.25 V
1.17
2
2
Fall Time
tf2A
1.515
Duty Cycle
dt2A
51.15 55
69.5 175
Skew(Window)
tsk2A
jitter
VT = 1.25 V
ps
ps
Jitter
190
250
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 24M, 48M, REF 1
TA = 0 - 70C; VDD = VDDL = 3.3 V +/- 5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP
MAX UNITS
RDSP5 VO = VDD*(0.5)
RDSN5 VO = VDD*(0.5)
VOH5 IOH = -14 mA
VOL5 IOL = 6.0 mA
IOH5 VOH = 2.0 V
60
60
Ω
Ω
20
2.4
V
0.4
-20
V
mA
mA
ns
ns
%
IOL5
tr5
VOL = 0.8 V
10
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.25
2.19
50.3
4
4
Fall Time
tf5
Duty Cycle
dt5
tj1s5
55
250
800
Jitter (cyc to cyc)
VT = 1.5 V
ps
ps
tjabs5 VT = 1.5 V
Jitter abs
715
1Guarenteed by design, not 100% tested in production.
8
ICS9248-102
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
RDSP1 VO = VDD*(0.5)
RDSN1 VO = VDD*(0.5)
55
55
Ω
Ω
12
Output High Voltage VOH1 IOH = -18 mA
2.4
V
Output Low Voltage
Output High Current
Output Low Current
Rise Time
VOL1 IOL = 9.4 mA
IOH1 VOH = 2.0 V
IOL1 VOL = 0.8 V
0.4
-22
V
mA
mA
ns
ns
%
25
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
1.925
1.66
49.4
74.5
2
Fall Time
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
Duty Cycle
dt1
55
Skew Window
Jitter
tsk1 VT = 1.5 V
tj1s1 VT = 1.5 V
tjabs1 VT = 1.5 V
250
150
500
ps
ps
ps
150
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX
UNITS
Ω
RDSP2A VO = VDD*(0.5)
RDSN2A VO = VDD*(0.5)
20
20
10
Ω
V
VOH2A
VOL2A
IOH2A
IOL2A
tr2A
IOH = -28 mA
2.4
IOL = 19 mA
0.4
-42
V
VOH = 2.0 V
mA
mA
ns
VOL = 0.8 V
33
0.5
0.5
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL= 0.4 V
VT = 1.5 V
1.08
1.26
49.85
203
2
2
Fall Time
tf2A
ns
Duty Cycle
Skew Window
dt2A
tsk2A
55
250
%
ps
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
9
ICS9248-102
Pin 1
.093
DIA. PIN (Optional)
D/2
Index
Area
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-e-
B
A2
c
A
C
.004
SEE
DETAIL “A”
-E-
SEATING
PLANE
-D-
-C-
END VIEW
A1
SIDE VIEW
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.087
.008
.005
NOM.
MAX.
.110
MIN.
.620
NOM.
.625
MAX.
.630
A
A1
A2
B
.102
AC
48
.012
.016
.090
.094
-
-
.0135
.010
c
D
E
See Variations
.291
.295
.299
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
e
0.025 BSC
H
h
.395
.010
.020
-
.420
.016
.040
.013
L
-
N
See Variations
0°
-
8°
48 Pin 300 mil SSOP Package
Ordering Information
ICS9248yF-102-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
PackageType
F=SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
10
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