9248BF-138 [IDT]
Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48;
| 型号： | 9248BF-138 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 166.67MHz, PDSO48, 0.300 INCH, MO-118, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-138
Integrated
Circuit
Systems, Inc.
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Pin Configuration
810/810E and Solano type chipset.
1*SEL24_48#/REF0
VDDREF
X1
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC1
Output Features:
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
•
•
•
•
•
•
•
•
2- CPUs @ 2.5V
X2
9 - SDRAM @ 3.3V, including 1 free running
7 - PCICLK @ 3.3V
GNDREF
GND3V66
3V66-0
3V66-1
3V66-2
1 - IOAPIC @ 2.5V,
3 - 3V66MHz @ 3.3V
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I2C
1 - REF @v3.3V, 14.318MHz.
VDD3V66
VDDPCI
1*FS0/PCICLK0
1**FS1/PCICLK1
GNDPCI
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
GNDPCI
PD#
Features:
•
•
Up to 200MHz frequency support
Support FS0-FS4 strapping status bit for I2C read
back.
•
Support power management: Through Power down
Mode from I2C programming.
24_48MHz/FS2**
48MHz/FS3*
48MHz/FS4*1
VDD48
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
SCLK
SDATA
Skew Specifications:
•
•
•
•
•
CPU – CPU: <175ps
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
1 These are double strength.
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
For group skew specifications, please refer to group
timing relationship.
Block Diagram
Functionality
CPU
(MHz)
66.67
66.87
68.67
SDRAM
(MHz)
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
3V66
(MHz)
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
PCICLK
(MHz)
33.33
33.43
34.33
35.66
33.33
33.43
34.33
35.66
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
IOAPIC
(MHz)
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
FS4 FS3 FS2 FS1 FS0
PLL2
48MHz [1:0]
24_48MHz
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
/ 2
X1
X2
XTAL
OSC
REF0
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
PLL1
Spread
Spectrum
CPU
DIVDER
CPUCLK [1:0]
2
8
SDRAM
DIVDER
SDRAM [7:0]
SDRAM_F
IOAPIC
SEL24_48#
IOAPIC
DIVDER
Control
Logic
SDATA
SCLK
PCI
DIVDER
PCICLK [6:0]
3V66 [2:0]
7
FS[4:0]
PD#
Config.
Reg.
3V66
DIVDER
3
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
160.00
160.00
166.67
166.67
160.00
120.00
166.67
125.00
80.00
80.00
83.34
83.34
40.00
40.00
41.67
41.67
20.00
20.00
20.84
20.84
AdditionalfrequenciesselectablethroughI2Cprogramming.
0342C—08/26/03
ICS9248-138
General Description
The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides
all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Logic inputs frequency select I/O/USB output,
When a "0" is latched, output frequency = 48MHz
When a "1" is latched, output frequency = 24MHz
14.318 MHz reference clock.
SEL24_48MHz#
IN
1
REF0
VDD
OUT
PWR
2, 10, 11, 18, 25,
3.3V Power supply for SDRAM output buffers, PCI output buffers, reference
output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
30, 38
3
X1
X2
IN
4
5, 6, 14, 21, 29, 34,
42
OUT
Crystal output, nominally 14.318MHz.
GND
PWR
Ground pin for 3V outputs.
9, 8, 7
3V66 [2:0]
FS0
OUT
IN
3.3V Clocks
Frequency select pin.
PCI clock output
Frequency select pin.
PCI clock output
12
PCICLK0
FS1
OUT
IN
13
PCICLK1
PCICLK [6:2]
OUT
OUT
20, 19, 17, 16, 15
PCI clock outputs.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Clock input of I2C input, 5V tolerant input
PD#
IN
22
SCLK
SDATA
FS4
IN
IN
23
24
Data input for I2C serial input, 5V tolerant input
Frequency select pin.
IN
26
48MHz
FS3
OUT
IN
48MHz output clocks
Frequency select pin.
27
48MHz
OUT
IN
48MHz output clocks
Frequency select pin.
FS2
24_48MHz
28
31
OUT
24 or 48MHz output
SDRAM_F
OUT
Free running SDRAM - used for feed back to chipset, should remain on always.
32, 33, 35, 36, 37,
39, 40, 41,
43
SDRAM [7:0]
OUT
SDRAM clock outputs
GNDLCPU
CPUCLK [1:0]
VDDLCPU
IOAPIC
PWR
OUT
PWR
OUT
PWR
Ground pin for the CPU clocks.
CPU clock outputs.
44, 45
46
Power pin for the CPUCLKs. 2.5V
2.5V clock output
47
48
VDDLAPIC
Power pin for the IOAPIC. 2.5V
0342C—08/26/03
2
ICS9248-138
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
SDRAM 3V66 PCICLK IOAPIC
PWD
CPUCL-
K
(MHz)
bit2 bit7 bit6 bit5 bit4
FS4 FS3 FS2 FS1 FS0
Spread Precentage
(MHz)
(MHz)
(MHz)
(MH)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
100.00
100.30
103.00
107.00
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
100.00
100.30
103.00
90.00
66.67
66.87
68.67
71.34
66.67
66.87
68.67
71.34
66.67
66.87
68.67
60.00
66.67
66.87
68.67
60.00
68.00
70.00
71.34
72.67
68.00
70.00
71.34
72.67
73.34
76.67
80.00
83.34
73.34
80.00
83.34
66.67
33.33
33.43
34.33
35.67
33.33
33.43
34.33
35.67
33.33
33.43
34.33
30.00
33.33
33.43
34.33
30.00
34.00
35.00
35.67
36.33
34.00
35.00
35.67
36.33
36.67
38.33
40.00
41.67
36.67
40.00
41.67
33.33
16.67
16.72
17.16
17.83
16.67
16.72
17.17
17.84
16.67
16.72
17.17
15.00
16.67
16.72
17.17
15.00
17.00
17.50
17.84
18.17
17.00
17.50
17.84
18.17
18.34
19.17
20.00
20.84
18.34
20.00
20.84
16.67
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
0 to -0.5% Down Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
± 0.25% Center Spread
66.87
68.67
71.34
100.00
100.30
103.00
107.00
133.33
133.73
137.33
120.00
133.33
133.73
137.33
120.00
136.00
140.00
142.67
145.33
136.00
140.00
142.67
145.33
146.67
153.33
160.00
166.67
146.67
160.00
166.67
200.00
(0,0001)
Bit
2, 7:4
136.00
140.00
142.67
145.33
102.00
105.00
107.00
109.00
146.67
153.33
160.00
166.67
110.00
120.00
125.00
200.00
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
Bit 3
Bit 1
Bit 0
0
0
0
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I2C is a trademark of Philips Corporation
0342C—08/26/03
3
ICS9248-138
Byte 1: SDRAM Control Register
(1= enable, 0 = disable)
Byte 2: PCI, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS0#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
X
1
1
1
1
1
1
FS2#
20
19
17
16
15
13
12
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
FS1#
31
32
33
35
36
37
SDRAM_F
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
Byte 3: 3V66, Control Register
(1= enable, 0 = disable)
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
1
1
1
1
1
1
1
FS4#
Reserved
Reserved
Reserved
Reserved
48MHz-0
48MHz-1
24_48MHz
Reserved
Reserved
Reserved
Reserved
3V66-0
-
-
-
-
-
-
27
26
28
7
8
9
3V66-1
3V66-2
Byte 5: Control Register
(1= enable, 0 = disable)
Byte 6: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved (Note)
BIT PIN# PWD
DESCRIPTION
(SEL24_48#)#
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
X
1
1
1
1
1
1
1
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
1
REF0
47
44
45
39
40
41
IOAPIC
CPUCLK1
CPUCLK0
SDRAM2
SDRAM1
SDRAM0
Notes:
Note: Don’t write into this register, writing into this
register can cause malfunction.This Byte
becomes the Byte Count for Readback, so it
cannot be seen as data.
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
0342C—08/26/03
4
ICS9248-138
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 5.5 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature. . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset Tolerance Offset Tolerance Offset Tolerance
Offset
3.75ns
0.0ns
Tolerance
CPU to SDRAM 2.5ns
CPU to 3V66 7.5ns
SDRAM to 3V66 0.0ns
500ps
500ps
500ps
5.0ns
5.0ns
0.0ns
500ps
500ps
500ps
0.0ns
0.0ns
0.0ns
500ps
500ps
500ps
500ps
500ps
500ps
500ps
1.0ns
N/A
3.75ns
1.5 -3.5ns
0.0ns
3V66 to PCI
PCI to PCI
USB & DOT
1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps
0.0ns
1.0ns
N/A
0.0ns
1.0ns
N/A
0.0ns
1.0ns
N/A
Asynch
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
TYP
MAX
UNITS
V
2
VSS - 0.3
-5
VDD + 0.3
VIL
0.8
5
V
IIH
VIN = VDD
mA
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP CL = 0 pF; Select @ 66M
100
600
Supply Current
Power Down
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
mA
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Fi
Lpin
VDD = 3.3 V;
14.318
MHz
nH
pF
7
5
CIN
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
PLZ,tPZH
1
1
10
10
t
output disable delay (all outputs)
nS
1Guaranteed by design, not 100% tested in production.
0342C—08/26/03
5
ICS9248-138
Electrical Characteristics - CPU
TA = 0 - 70°C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
13.5
13.5
2
TYP
MAX UNITS
1
RDSP2B
45
45
Ω
Ω
1
RDSN2B
VO = VDD*(0.5)
VOH2B
VOL2B
IOH2B
IOL2B
IOH = -1 mA
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
1
Skew
tsk2B
VT = 1.25 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Ω
Ω
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
12
12
55
55
1
RDSN1
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
-33
30
mA
mA
ns
ns
%
1
tr1
0.5
0.5
45
2
1
Fall Time
tf1
VOH = 2.4 V, VOL = 0.4 V
2
1
Duty Cycle
dt1
VT = 1.5 V
55
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
175
500
ps
ps
tjcyc-cyc
Jitter
1Guaranteed by design, not 100% tested in production.
0342C—08/26/03
6
ICS9248-138
Electrical Characteristics - IOAPIC
TA = 0 - 70°C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
9
TYP
MAX UNITS
1
RDSP4B
30
30
Ω
Ω
1
RDSN4B
VO = VDD*(0.5)
9
VOH4\B
VOL4B
IOH4B
IOL4B
IOH = -5.5 mA
2
V
IOL = 9.0 mA
0.4
-27
30
V
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
1
Skew
tsk4
250
500
ps
ps
tjcyc-cyc
VT = 1.25 V
Jitter
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
10
TYP
MAX UNITS
1
Ω
Ω
RDSP3
24
24
1
RDSN3
VO = VDD*(0.5)
10
VOH3
VOL3
IOH3
IOL3
IOH = -1 mA
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
tjcyc-cyc VT = 1.5 V
Jitter
1Guaranteed by design, not 100% tested in production.
0342C—08/26/03
7
ICS9248-138
Electrical Characteristics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
12
TYP
MAX UNITS
1
Ω
Ω
RDSP1
55
55
1
RDSN1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
VOH1
VOL1
IOH1
IOL1
2.4
V
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
tjcyc-cyc
Jitter
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70°C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
VO = VDD*(0.5)
MIN
20
TYP
MAX UNITS
1
RDSP5
60
60
Ω
Ω
1
RDSN5
VO = VDD*(0.5)
IOH = 1 mA
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V -29
mA
mA
ns
ns
%
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
29
45
1
tr5
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
55
Skew
Tsk
VT = 1.5 V
250
500
1000
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
Jitter
1
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0342C—08/26/03
8
ICS9248-138
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
0342C—08/26/03
9
ICS9248-138
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
138 serve as dual signal functions to the device. During
initial power-up, they act as input pins. The logic level
(voltage) that is present on these pins at this time is read
and stored into a 5-bit internal data latch. At the end of
Power-On reset, (see AC characteristics for timing values),
the device changes the mode of operations for these pins
to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Fig. 1
0342C—08/26/03
10
ICS9248-138
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD#
is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down
the clock synthesizer.
Internal clocks are not running after the device is put in power down.When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The
power down latency should be as short as possible but conforming to the sequence requirements shown below.The REF
and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic,
stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
3V66
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist.This signal is synchronized inside this part.
4.The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0342C—08/26/03
11
ICS9248-138
300 mil SSOP
In Millimeters
COMMON DIMENSIONS
c
N
In Inches
COMMON DIMENSIONS
SYMBOL
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
SEE VARIATIONS
.395
.291
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
10.03
7.40
10.68
7.60
.420
.299
0.635 BASIC
0.025 BASIC
1
22
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
α
hh xx 4455°°
D
N
a
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
A
N
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
A1
- CC --
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
e
SEATING
PLANE
b
.10 ((..000044)) CC
Ordering Information
ICS9248yF-138
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
DeviceType (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0342C—08/26/03
12
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9248-138 (Desktop Chipsets)
Description
810/810E and Solano type chipset.
Market Group
PC CLOCK
Additional Info
810 and Solano chipset - The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. • 2- CPUs
@ 2.5V • 9 - SDRAM @ 3.3V, including 1 free running • 7 - PCICLK @ 3.3V • 1 - IOAPIC @ 2.5V, • 3 - 3V66MHz @ 3.3V • 2 - 48MHz, @ 3.3V
fixed. • 1 - 24/48MHz, @3.3V selectable by I2C • 1 - REF @v3.3V, 14.318MHz.
Related Orderable Parts
Attributes
9248BF-138
9248BF-138LF
9248BF-138LFT
9248BF-138T
3.3 V (PV48)
3.3 V (PVG48)
3.3 V (PVG48)
3.3 V (PV48)
SSOP 48
NA
Voltage
Package
Speed
SSOP 48
NA
SSOP 48
NA
SSOP 48
NA
C
C
C
C
Temperature
Active
Yes
90
Active
Yes
90
Active
No
Active
No
Status
Sample
1000
1000
1000
Minimum Order Quantity
Factory Order Increment
30
30
1000
Related Documents
Type
Title
Size
Revision Date
Datasheet
Model - IBIS
9248-138 Datasheet
9248-138 IBIS Model
115 KB
280 KB
03/23/2006
03/23/2006
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