92HD81B1C5NLGXUAX_技术文档

DATASHEET

SINGLE CHIP PC AUDIO SYSTEM

CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

92HD81

•

Full ECR15B low power support

Description

•

Audio inactivity transitions codec from D0 to D3 low

The 92HD81 single-chip audio system is a low power

optimized, high fidelity, 4-channel audio codec with

integrated speaker amplifier, capless headphone amplifier,

and low drop out voltage regulator. The high integration of

the 92HD81 enables the smallest PCB footprint with the

lowest system BOM count and cost. The 92HD81 provides

high quality HD Audio capability to notebook and business

desktop PC applications.

power mode

•

Resume from D3 to D0 with audio activity in < 10 msec

D3 to D0 transition with < -65dB pop/click

Port presence detect in D3 with or without bit clock

Optional analog PC beep in D3

Additional vendor specific modes for even lower power

•

Microsoft WLP 3/4/5 premium logo compliant, as

defined in WLP 3.9

Dual SPDIF for WLP compliant support of

simultaneous HDMI and SPDIF output

Features

•

4 Channels (2 stereo DACs and 2 stereo ADCs) with

•

Support for 1.5V and 3.3V HDA signaling

24-bit resolution

Two digital microphone inputs (mono, stereo, or

quad microphones)

•

Supports full-duplex stereo audio and simultaneous VoIP

Provides a mono output

•

2W/channel stereo speaker amplifier @ 4 ohms and

4.75V

•

High performance analog mixer

2 adjustable VREF Out pins for analog microphone

bias

Two headphone amplifiers

•

One capless and one non-capless retaskable

Internal core voltage regulator

1.5V to 1.8V or 3.3V digital power supply options

+5 V analog power supply option

•

6 analog ports with port presence detect (5 single

ended, 1 BTL)

•

Analog and digital PC Beep support

Aux Audio Mode ^{(see orderable part numbers for support)}

48-pad QFN RoHS packages

Block Diagram

Port A (HP)

Port B (cap-less HP/LO)

Port C

X

Port D (BTL)

Port E

Port F

SPDIF Out 0

SPDIF Out 1

DUAL SPDIF

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92HD81

V 0.987 11/09

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

Software Support

•

Intuitive graphical user interface that allows configurability and preference settings

SKPI (Kernel Processing Interface)

Enables plug-ins that can operate globally on all audio streams of the system

12 band fully parametric equalizer (SKPI plug-in)

•

Constant, system-level effects tuned to optimize a particular platform can be combined with

user-mode “presets” tailored for specific acoustical environments and applications

System-level effects automatically disabled when external audio connections made

•

Dynamics Processing (SKPI plug-in)

•

Enables improved voice articulation

Compressor/limiter allows higher average noise level without resonances or damage to

speakers.

IDT Vista APO wrapper

Enables multiple APOs to be used with the IDT Driver

•

Microphone Beam Forming, Acoustic Echo Cancellation, and Noise Suppression

Dynamic Stream Switching

•

Improved multi-streaming user experience with less support calls

•

Dolby PC Entertainment Experience Logo Program

•

Dolby Home Theater™ (HT)

Dolby Sound Room™ (SR)

Dolby Technologies

•

Dolby Headphone™, Dolby Virtual Speaker™

Dolby ProLogic II™, Dolby ProLogic IIx™

•

Dolby Digital Live™ (DDL)

•

Maxx Player™ from Waves

TM

WOW and Tru Surround from SRS

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

TABLE OF CONTENTS

1. DESCRIPTION ........................................................................................................................ 11

1.1. Overview ..........................................................................................................................................11

1.2. Orderable Part Numbers ..................................................................................................................11

1.3. Block Diagram .................................................................................................................................12

2. DETAILED DESCRIPTION ..................................................................................................... 13

2.1. Port Functionality .............................................................................................................................13

2.1.1. Port Characteristics ............................................................................................................15

2.1.2. Vref_Out .............................................................................................................................15

2.1.3. Jack Detect ........................................................................................................................15

2.1.4. SPDIF Output .....................................................................................................................16

2.2. Mono Output ....................................................................................................................................18

2.3. Analog Mixer ....................................................................................................................................19

2.4. ADC Multiplexers .............................................................................................................................19

2.5. Power Management .........................................................................................................................19

2.6. AFG D0 ............................................................................................................................................20

2.7. AFG D1 ............................................................................................................................................20

2.8. AFG D2 ............................................................................................................................................20

2.9. AFG D3 ............................................................................................................................................21

2.9.1. AFG D3cold .......................................................................................................................21

2.10. Vendor Specific Function Group Power States D4/D5 ..................................................................22

2.11. Low-voltage HDA Signaling ...........................................................................................................22

2.12. Multi-channel capture ....................................................................................................................22

2.13. Digital Microphone Support ...........................................................................................................24

2.14. Analog PC-Beep ............................................................................................................................29

2.15. Digital PC-Beep .............................................................................................................................29

2.16. Headphone Drivers ........................................................................................................................29

2.17. EAPD .............................................................................................................................................30

2.18. BTL Amplifier .................................................................................................................................33

2.19. GPIO ..............................................................................................................................................34

2.19.1. GPIO Pin mapping and shared functions .........................................................................34

2.19.2. SPDIF/Digital Microphone/GPIO Selection ......................................................................34

2.19.3. Digital Microphone/GPIO Selection .................................................................................34

2.20. HD Audio ECR 15b support ...........................................................................................................35

2.21. Digital Core Voltage Regulator ......................................................................................................35

2.22. Aux Audio Support .........................................................................................................................36

2.22.1. General conditions in Aux Audio Mode: ...........................................................................36

2.22.2. “Playback Path” Port Behavior .........................................................................................36

2.22.3. “Record Path” Port Behavior ............................................................................................38

2.22.4. EAPD ...............................................................................................................................39

2.22.5. Analog PC_Beep .............................................................................................................39

2.22.6. Firmware/Software Requirements: ...................................................................................39

3. CHARACTERISTICS ............................................................................................................... 40

3.1. Electrical Specifications ...................................................................................................................40

3.1.1. Absolute Maximum Ratings ...............................................................................................40

3.1.2. Recommended Operating Conditions ................................................................................40

3.2. 92HD81 Analog Performance Characteristics (PRELIMINARY) .....................................................41

3.3. AC Timing Specs .............................................................................................................................46

3.3.1. HD Audio Bus Timing .........................................................................................................46

3.3.2. SPDIF Timing .....................................................................................................................46

3.3.3. Digital Microphone Timing .................................................................................................47

3.3.4. Class-AB BTL Amplifier Performance ...............................................................................48

3.3.5. Capless Headphone Supply Characteristics ......................................................................48

4. FUNCTIONAL BLOCK DIAGRAMS ....................................................................................... 49

5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS ....................................... 50

6. PORT CONFIGURATIONS ..................................................................................................... 51

6.1. Suggested Desktop Configurations .................................................................................................51

6.2. Suggested Mobile Port Configurations ............................................................................................52

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

6.3. Pin Configuration Default Register Settings .....................................................................................53

7. WIDGET INFORMATION ........................................................................................................ 54

7.1. Widget List .......................................................................................................................................54

7.2. Reset Key ........................................................................................................................................56

7.3. Root (NID = 00h): VendorID ............................................................................................................56

7.3.1. Root (NID = 00h): RevID ....................................................................................................57

7.3.2. Root (NID = 00h): NodeInfo ...............................................................................................57

7.4. AFG (NID = 01h): NodeInfo .............................................................................................................58

7.4.1. AFG (NID = 01h): FGType .................................................................................................59

7.4.2. AFG (NID = 01h): AFGCap ................................................................................................59

7.4.3. AFG (NID = 01h): PCMCap ...............................................................................................60

7.4.4. AFG (NID = 01h): StreamCap ............................................................................................62

7.4.5. AFG (NID = 01h): InAmpCap .............................................................................................62

7.4.6. AFG (NID = 01h): PwrStateCap .........................................................................................63

7.4.7. AFG (NID = 01h): GPIOCnt ...............................................................................................64

7.4.8. AFG (NID = 01h): OutAmpCap ..........................................................................................65

7.4.9. AFG (NID = 01h): PwrState ...............................................................................................66

7.4.10. AFG (NID = 01h): UnsolResp ..........................................................................................67

7.4.11. AFG (NID = 01h): GPIO ...................................................................................................67

7.4.12. AFG (NID = 01h): GPIOEn ...............................................................................................68

7.4.13. AFG (NID = 01h): GPIODir ..............................................................................................69

7.4.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................69

7.4.15. AFG (NID = 01h): GPIOUnsol ..........................................................................................70

7.4.16. AFG (NID = 01h): GPIOSticky .........................................................................................71

7.4.17. AFG (NID = 01h): SubID ..................................................................................................71

7.4.18. AFG (NID = 01h): GPIOPlrty ............................................................................................72

7.4.19. AFG (NID = 01h): GPIODrive ...........................................................................................73

7.4.20. AFG (NID = 01h): DMic ....................................................................................................74

7.4.21. AFG (NID = 01h): DACMode ...........................................................................................75

7.4.22. AFG (NID = 01h): ADCMode ...........................................................................................76

7.4.23. AFG (NID = 01h): EAPD ..................................................................................................76

7.4.24. AFG (NID = 01h): PortUse ...............................................................................................78

7.4.25. AFG (NID = 01h): VSPwrState .........................................................................................79

7.4.26. AFG (NID = 01h): AnaPort ...............................................................................................80

7.4.27. AFG (NID = 01h): AnaBeep .............................................................................................81

7.4.28. AFG (NID = 01h): AnaBTL YC and YD Revisions ...........................................................81

7.4.29. AFG (NID = 01h): AnaBTL UA and TA Revisions ............................................................83

7.4.30. AFG (NID = 01h): AnaCapless .........................................................................................87

7.4.31. AFG (NID = 01h): Reset ...................................................................................................89

7.4.32. AFG (NID = 01h): AuxAudio .............................................................................................90

7.5. PortA (NID = 0Ah): WCap ................................................................................................................91

7.5.1. PortA (NID = 0Ah): PinCap ................................................................................................92

7.5.2. PortA (NID = 0Ah): ConLst .................................................................................................94

7.5.3. PortA (NID = 0Ah): ConLstEntry0 ......................................................................................94

7.5.4. PortA (NID = 0Ah): InAmpLeft ............................................................................................95

7.5.5. PortA (NID = 0Ah): InAmpRight .........................................................................................95

7.5.6. PortA (NID = 0Ah): ConSelectCtrl ......................................................................................96

7.5.7. PortA (NID = 0Ah): PwrState .............................................................................................96

7.5.8. PortA (NID = 0Ah): PinWCntrl ............................................................................................97

7.5.9. PortA (NID = 0Ah): UnsolResp ..........................................................................................98

7.5.10. PortA (NID = 0Ah): ChSense ...........................................................................................98

7.5.11. PortA (NID = 0Ah): EAPDBTLLR .....................................................................................99

7.5.12. PortA (NID = 0Ah): ConfigDefault ....................................................................................99

7.6. PortB (NID = 0Bh): WCap ..............................................................................................................102

7.6.1. PortB (NID = 0Bh): PinCap ..............................................................................................104

7.6.2. PortB (NID = 0Bh): ConLst ...............................................................................................105

7.6.3. PortB (NID = 0Bh): ConLstEntry0 ....................................................................................106

7.6.4. PortB (NID = 0Bh): ConSelectCtrl ....................................................................................107

7.6.5. PortB (NID = 0Bh): PwrState ...........................................................................................107

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.6.6. PortB (NID = 0Bh): PinWCntrl ..........................................................................................108

7.6.7. PortB (NID = 0Bh): UnsolResp ........................................................................................109

7.6.8. PortB (NID = 0Bh): ChSense ...........................................................................................109

7.6.9. PortB (NID = 0Bh): EAPDBTLLR .....................................................................................110

7.6.10. PortB (NID = 0Bh): ConfigDefault ..................................................................................110

7.7. PortC (NID = 0Ch): WCap .............................................................................................................113

7.7.1. PortC (NID = 0Ch): PinCap ..............................................................................................114

7.7.2. PortC (NID = 0Ch): ConLst ..............................................................................................116

7.7.3. PortC (NID = 0Ch): ConLstEntry0 ....................................................................................116

7.7.4. PortC (NID = 0Ch): InAmpLeft .........................................................................................117

7.7.5. PortC (NID = 0Ch): InAmpRight .......................................................................................117

7.7.6. PortC (NID = 0Ch): ConSelectCtrl ...................................................................................118

7.7.7. PortC (NID = 0Ch): PwrState ...........................................................................................118

7.7.8. PortC (NID = 0Ch): PinWCntrl .........................................................................................119

7.7.9. PortC (NID = 0Ch): UnsolResp ........................................................................................120

7.7.10. PortC (NID = 0Ch): ChSense .........................................................................................121

7.7.11. PortC (NID = 0Ch): EAPDBTLLR ...................................................................................121

7.7.12. PortC (NID = 0Ch): ConfigDefault ..................................................................................122

7.8. PortD (NID = 0Dh): WCap .............................................................................................................124

7.8.1. PortD (NID = 0Dh): PinCap ..............................................................................................126

7.8.2. PortD (NID = 0Dh): ConLst ..............................................................................................127

7.8.3. PortD (NID = 0Dh): ConLstEntry0 ....................................................................................128

7.8.4. PortD (NID = 0Dh): ConSelectCtrl ...................................................................................129

7.8.5. PortD (NID = 0Dh): PwrState ...........................................................................................129

7.8.6. PortD (NID = 0Dh): PinWCntrl .........................................................................................130

7.8.7. PortD (NID = 0Dh): EAPDBTLLR .....................................................................................130

7.8.8. PortD (NID = 0Dh): ConfigDefault ....................................................................................131

7.9. PortE (NID = 0Eh): WCap ..............................................................................................................134

7.9.1. PortE (NID = 0Eh): PinCap ..............................................................................................135

7.9.2. PortE (NID = 0Eh): ConLst ...............................................................................................137

7.9.3. PortE (NID = 0Eh): ConLstEntry0 ....................................................................................137

7.9.4. PortE (NID = 0Eh): InAmpLeft ..........................................................................................138

7.9.5. PortE (NID = 0Eh): InAmpRight .......................................................................................138

7.9.6. PortE (NID = 0Eh): ConSelectCtrl ....................................................................................139

7.9.7. PortE (NID = 0Eh): PwrState ...........................................................................................139

7.9.8. PortE (NID = 0Eh): PinWCntrl ..........................................................................................140

7.9.9. PortE (NID = 0Eh): UnsolResp ........................................................................................141

7.9.10. PortE (NID = 0Eh): ChSense .........................................................................................141

7.9.11. PortE (NID = 0Eh): EAPDBTLLR ...................................................................................142

7.9.12. PortE (NID = 0Eh): ConfigDefault ..................................................................................142

7.10. PortF (NID = 0Fh): WCap ............................................................................................................145

7.10.1. PortF (NID = 0Fh): PinCap .............................................................................................146

7.10.2. PortF (NID = 0Fh): ConLst .............................................................................................148

7.10.3. PortF (NID = 0Fh): ConLstEntry0 ...................................................................................148

7.10.4. PortF (NID = 0Fh): InAmpLeft ........................................................................................149

7.10.5. PortF (NID = 0Fh): InAmpRight ......................................................................................149

7.10.6. PortF (NID = 0Fh): ConSelectCtrl ..................................................................................150

7.10.7. PortF (NID = 0Fh): PwrState ..........................................................................................150

7.10.8. PortF (NID = 0Fh): PinWCntrl ........................................................................................151

7.10.9. PortF (NID = 0Fh): UnsolResp .......................................................................................152

7.10.10. PortF (NID = 0Fh): ChSense ........................................................................................153

7.10.11. PortF (NID = 0Fh): EAPDBTLLR .................................................................................153

7.10.12. PortF (NID = 0Fh): ConfigDefault .................................................................................154

7.11. MonoOut (NID = 10h): WCap ......................................................................................................157

7.11.1. MonoOut (NID = 10h): PinCap .......................................................................................158

7.11.2. MonoOut (NID = 10h): ConLst .......................................................................................159

7.11.3. MonoOut (NID = 10h): ConLstEntry0 .............................................................................160

7.11.4. MonoOut (NID = 10h): PwrState ....................................................................................160

7.11.5. MonoOut (NID = 10h): PinWCntrl ..................................................................................161

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7.11.6. MonoOut (NID = 10h): ConfigDefault .............................................................................162

7.12. DMic0 (NID = 11h): WCap ...........................................................................................................164

7.12.1. DMic0 (NID = 11h): PinCap ...........................................................................................166

7.12.2. DMic0 (NID = 11h): InAmpLeft .......................................................................................167

7.12.3. DMic0 (NID = 11h): InAmpRight ....................................................................................167

7.12.4. DMic0 (NID = 11h): PwrState .........................................................................................168

7.12.5. DMic0 (NID = 11h): PinWCntrl .......................................................................................169

7.12.6. DMic0 (NID = 11h): UnsolResp ......................................................................................169

7.12.7. DMic0 (NID = 11h): ChSense ........................................................................................170

7.12.8. DMic0 (NID = 11h): ConfigDefault .................................................................................170

7.13. DMic1Vol (NID = 12h): WCap ......................................................................................................173

7.13.1. DMic1Vol (NID = 12h): ConLst .......................................................................................174

7.13.2. DMic1Vol (NID = 12h): ConLstEntry0 ............................................................................175

7.13.3. DMic1Vol (NID = 12h): InAmpLeft ..................................................................................175

7.13.4. DMic1Vol (NID = 12h): InAmpRight ...............................................................................175

7.13.5. DMic1Vol (NID = 12h): PwrState ...................................................................................176

7.14. DAC0 (NID = 13h): WCap ............................................................................................................177

7.14.1. DAC0 (NID = 13h): Cnvtr ...............................................................................................178

7.14.2. DAC0 (NID = 13h): OutAmpLeft .....................................................................................179

7.14.3. DAC0 (NID = 13h): OutAmpRight ..................................................................................180

7.14.4. DAC0 (NID = 13h): PwrState .........................................................................................180

7.14.5. DAC0 (NID = 13h): CnvtrID ............................................................................................181

7.14.6. DAC0 (NID = 13h): EAPDBTLLR ...................................................................................182

7.15. DAC1 (NID = 14h): WCap ............................................................................................................182

7.15.1. DAC1 (NID = 14h): Cnvtr ...............................................................................................184

7.15.2. DAC1 (NID = 14h): OutAmpLeft .....................................................................................185

7.15.3. DAC1 (NID = 14h): OutAmpRight ..................................................................................185

7.15.4. DAC1 (NID = 14h): PwrState .........................................................................................186

7.15.5. DAC1 (NID = 14h): CnvtrID ............................................................................................187

7.15.6. DAC1 (NID = 14h): EAPDBTLLR ...................................................................................187

7.16. DAC2 (NID = 22h): WCap ............................................................................................................188

7.16.1. DAC2 (NID = 22h): Cnvtr ...............................................................................................189

7.16.2. DAC2 (NID = 22h): OutAmpLeft .....................................................................................190

7.16.3. DAC2 (NID = 22h): OutAmpRight ..................................................................................191

7.16.4. DAC2 (NID = 22h): PwrState .........................................................................................191

7.16.5. DAC2 (NID = 22h): CnvtrID ............................................................................................192

7.16.6. DAC2 (NID = 22h): EAPDBTLLR ...................................................................................193

7.17. ADC0 (NID = 15h): WCap ............................................................................................................193

7.17.1. ADC0 (NID = 15h): ConLst ............................................................................................195

7.17.2. ADC0 (NID = 15h): ConLstEntry0 ..................................................................................195

7.17.3. ADC0 (NID = 15h): Cnvtr ...............................................................................................196

7.17.4. ADC0 (NID = 15h): ProcState ........................................................................................197

7.17.5. ADC0 (NID = 15h): PwrState .........................................................................................197

7.17.6. ADC0 (NID = 15h): CnvtrID ............................................................................................198

7.18. ADC1 (NID = 16h): WCap ............................................................................................................199

7.18.1. ADC1 (NID = 16h): ConLst ............................................................................................200

7.18.2. ADC1 (NID = 16h): ConLstEntry0 ..................................................................................201

7.18.3. ADC1 (NID = 16h): Cnvtr ...............................................................................................201

7.18.4. ADC1 (NID = 16h): ProcState ........................................................................................203

7.18.5. ADC1 (NID = 16h): PwrState .........................................................................................203

7.18.6. ADC1 (NID = 16h): CnvtrID ............................................................................................204

7.19. ADC0Mux (NID = 17h): WCap .....................................................................................................204

7.19.1. ADC0Mux (NID = 17h): ConLst ......................................................................................206

7.19.2. ADC0Mux (NID = 17h): ConLstEntry4 ...........................................................................206

7.19.3. ADC0Mux (NID = 17h): ConLstEntry0 ...........................................................................207

7.19.4. ADC0Mux (NID = 17h): OutAmpCap .............................................................................207

7.19.5. ADC0Mux (NID = 17h): OutAmpLeft ..............................................................................208

7.19.6. ADC0Mux (NID = 17h): OutAmpRight ...........................................................................209

7.19.7. ADC0Mux (NID = 17h): ConSelectCtrl ...........................................................................209

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7.19.8. ADC0Mux (NID = 17h): PwrState ..................................................................................210

7.19.9. ADC0Mux (NID = 17h): EAPDBTLLR ............................................................................210

7.20. ADC1Mux (NID = 18h): WCap .....................................................................................................211

7.20.1. ADC1Mux (NID = 18h): ConLst ......................................................................................212

7.20.2. ADC1Mux (NID = 18h): ConLstEntry4 ...........................................................................213

7.20.3. ADC1Mux (NID = 18h): ConLstEntry0 ...........................................................................213

7.20.4. ADC1Mux (NID = 18h): OutAmpCap .............................................................................214

7.20.5. ADC1Mux (NID = 18h): OutAmpLeft ..............................................................................215

7.20.6. ADC1Mux (NID = 18h): OutAmpRight ...........................................................................215

7.20.7. ADC1Mux (NID = 18h): ConSelectCtrl ...........................................................................216

7.20.8. ADC1Mux (NID = 18h): PwrState ..................................................................................216

7.20.9. ADC1Mux (NID = 18h): EAPDBTLLR ............................................................................217

7.21. MonoMux (NID = 19h): WCap .....................................................................................................217

7.21.1. MonoMux (NID = 19h): ConLst ......................................................................................219

7.21.2. MonoMux (NID = 19h): ConLstEntry0 ............................................................................219

7.21.3. MonoMux (NID = 19h): ConSelectCtrl ...........................................................................220

7.21.4. MonoMux (NID = 19h): PwrState ...................................................................................220

7.22. MonoMix (NID = 1Ah): WCap ......................................................................................................221

7.22.1. MonoMix (NID = 1Ah): ConLst .......................................................................................223

7.22.2. MonoMix (NID = 1Ah): ConLstEntry0 .............................................................................223

7.22.3. MonoMix (NID = 1Ah): PwrState ....................................................................................224

7.23. Mixer (NID = 1Bh): WCap ............................................................................................................225

7.23.1. Mixer (NID = 1Bh): InAmpCap .......................................................................................226

7.23.2. Mixer (NID = 1Bh): ConLst .............................................................................................227

7.23.3. Mixer (NID = 1Bh): ConLstEntry4 ..................................................................................228

7.23.4. Mixer (NID = 1Bh): ConLstEntry0 ..................................................................................228

7.23.5. Mixer (NID = 1Bh): InAmpLeft0 ......................................................................................229

7.23.6. Mixer (NID = 1Bh): InAmpRight0 ...................................................................................229

7.23.7. Mixer (NID = 1Bh): InAmpLeft1 ......................................................................................230

7.23.8. Mixer (NID = 1Bh): InAmpRight1 ...................................................................................230

7.23.9. Mixer (NID = 1Bh): InAmpLeft2 ......................................................................................231

7.23.10. Mixer (NID = 1Bh): InAmpRight2 .................................................................................231

7.23.11. Mixer (NID = 1Bh): InAmpLeft3 ....................................................................................232

7.23.12. Mixer (NID = 1Bh): InAmpRight3 .................................................................................232

7.23.13. Mixer (NID = 1Bh): InAmpLeft4 ....................................................................................233

7.23.14. Mixer (NID = 1Bh): InAmpRight4 .................................................................................233

7.23.15. Mixer (NID = 1Bh): InAmpLeft5 ....................................................................................234

7.23.16. Mixer (NID = 1Bh): InAmpRight5 .................................................................................234

7.23.17. Mixer (NID = 1Bh): PwrState ........................................................................................235

7.24. MixerOutVol (NID = 1Ch): WCap .................................................................................................235

7.24.1. MixerOutVol (NID = 1Ch): ConLst ..................................................................................237

7.24.2. MixerOutVol (NID = 1Ch): ConLstEntry0 .......................................................................237

7.24.3. MixerOutVol (NID = 1Ch): OutAmpCap .........................................................................238

7.24.4. MixerOutVol (NID = 1Ch): OutAmpLeft ..........................................................................239

7.24.5. MixerOutVol (NID = 1Ch): OutAmpRight .......................................................................239

7.24.6. MixerOutVol (NID = 1Ch): PwrState ..............................................................................240

7.25. SPDIFOut0 (NID = 1Dh): WCap ..................................................................................................241

7.25.1. SPDIFOut0 (NID = 1Dh): PCMCap ................................................................................242

7.25.2. SPDIFOut0 (NID = 1Dh): StreamCap ............................................................................244

7.25.3. SPDIFOut0 (NID = 1Dh): OutAmpCap ...........................................................................244

7.25.4. SPDIFOut0 (NID = 1Dh): Cnvtr ......................................................................................245

7.25.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft ...........................................................................246

7.25.6. SPDIFOut0 (NID = 1Dh): OutAmpRight .........................................................................247

7.25.7. SPDIFOut0 (NID = 1Dh): PwrState ...............................................................................247

7.25.8. SPDIFOut0 (NID = 1Dh): CnvtrID ..................................................................................248

7.25.9. SPDIFOut0 (NID = 1Dh): DigCnvtr ................................................................................249

7.26. SPDIFOut1 (NID = 1Eh): WCap ..................................................................................................250

7.26.1. SPDIFOut1 (NID = 1Eh): PCMCap ................................................................................251

7.26.2. SPDIFOut1 (NID = 1Eh): StreamCap ............................................................................253

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7.26.3. SPDIFOut1 (NID = 1Eh): OutAmpCap ...........................................................................253

7.26.4. SPDIFOut1 (NID = 1Eh): Cnvtr ......................................................................................254

7.26.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft ...........................................................................255

7.26.6. SPDIFOut1 (NID = 1Eh): OutAmpRight .........................................................................256

7.26.7. SPDIFOut1 (NID = 1Eh): PwrState ................................................................................256

7.26.8. SPDIFOut1 (NID = 1Eh): CnvtrID ..................................................................................257

7.26.9. SPDIFOut1 (NID = 1Eh): DigCnvtr .................................................................................258

7.27. Dig0Pin (NID = 1Fh): WCap ........................................................................................................259

7.27.1. Dig0Pin (NID = 1Fh): PinCap .........................................................................................260

7.27.2. Dig0Pin (NID = 1Fh): ConLst .........................................................................................261

7.27.3. Dig0Pin (NID = 1Fh): ConLstEntry0 ...............................................................................262

7.27.4. Dig0Pin (NID = 1Fh): PwrState ......................................................................................262

7.27.5. Dig0Pin (NID = 1Fh): PinWCntrl ...................................................................................263

7.27.6. Dig0Pin (NID = 1Fh): UnsolResp ...................................................................................264

7.27.7. Dig0Pin (NID = 1Fh): ChSense ......................................................................................264

7.27.8. Dig0Pin (NID = 1Fh): ConfigDefault ...............................................................................265

7.28. Dig1Pin (NID = 20h): WCap .........................................................................................................267

7.28.1. Dig1Pin (NID = 20h): PinCap .........................................................................................269

7.28.2. Dig1Pin (NID = 20h): ConLst .........................................................................................270

7.28.3. Dig1Pin (NID = 20h): ConLstEntry0 ..............................................................................271

7.28.4. Dig1Pin (NID = 20h): PwrState ......................................................................................271

7.28.5. Dig1Pin (NID = 20h): PinWCntrl .....................................................................................272

7.28.6. Dig1Pin (NID = 20h): UnsolResp ...................................................................................273

7.28.7. Dig1Pin (NID = 20h): ChSense ......................................................................................273

7.28.8. Dig1Pin (NID = 20h): ConfigDefault ...............................................................................274

7.29. DigBeep (NID = 21h): WCap .......................................................................................................276

7.29.1. DigBeep (NID = 21h): OutAmpCap ................................................................................277

7.29.2. DigBeep (NID = 21h): OutAmpLeft ................................................................................278

7.29.3. DigBeep (NID = 21h): PwrState .....................................................................................278

7.29.4. DigBeep (NID = 21h): Gen .............................................................................................279

8. PINOUTS ............................................................................................................................... 281

8.1. Pin Assignment ..............................................................................................................................281

8.2. Pin Table for 48-pin QFN ...............................................................................................................282

9. PACKAGE OUTLINE AND PACKAGE DIMENSIONS ......................................................... 284

9.1. 48-Pad QFN Package ...................................................................................................................284

9.2. Standard Reflow Profile Data ........................................................................................................285

10. DISCLAIMER ....................................................................................................................... 286

11. DOCUMENT REVISION HISTORY .................................................................................... 287

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LIST OF TABLES

Table 1. Port Functionality .............................................................................................................................13

Table 2. Analog Output Port Behavior ...........................................................................................................15

Table 3. SPDIF OUT 0 Behavior ....................................................................................................................16

Table 4. SPDIF OUT 1 Behavior ....................................................................................................................17

Table 5. Power Management .........................................................................................................................19

Table 6. Example channel mapping ...............................................................................................................23

Table 8. BTL Amp Status ...............................................................................................................................31

Table 9. Headphone Amp Enable Configuration ............................................................................................31

Table 10. EAPD Low Power Behavior ...........................................................................................................31

Table 11. EAPD Behavior ..............................................................................................................................32

Table 12. Electrical Specification: Maximum Ratings ...................................................................................40

Table 13. Recommended Operating Conditions ............................................................................................40

Table 14. 92HD81 Analog Performance Characteristics ...............................................................................41

Table 15. HD Audio Bus Timing .....................................................................................................................46

Table 16. SPDIF Timing .................................................................................................................................46

Table 17. Digital Mic timing ............................................................................................................................47

Table 18. Class-AB BTL Amplifier Performance ............................................................................................48

Table 19. Capless Headphone Supply ..........................................................................................................48

Table 20. Pin Configuration Default Settings .................................................................................................53

Table 21. Command Format for Verb with 4-bit Identifier ..............................................................................54

Table 22. Command Format for Verb with 12-bit Identifier ............................................................................54

Table 23. Solicited Response Format ............................................................................................................54

Table 24. Unsolicited Response Format ........................................................................................................54

Table 25. High Definition Audio Widget .........................................................................................................54

Table 26. Pin Table ......................................................................................................................................282

Table 27. Standard Reflow Profile ...............................................................................................................285

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LIST OF FIGURES

Figure 1. 92HD81 Block Diagram ..................................................................................................................12

Figure 2. System Diagram ............................................................................................................................12

Figure 3. Multi-channel capture ......................................................................................................................23

Figure 4. Multi-channel timing diagram ..........................................................................................................23

Figure 5. Single Digital Microphone (data is ported to both left and right channels .......................................26

Figure 6. Stereo Digital Microphone Configuration ........................................................................................27

Figure 7. Quad Digital Microphone Configuration ..........................................................................................28

Figure 8. HP EAPD Example to be replaced by single pin for internal amp ..................................................33

Figure 9. HD Audio Bus Timing ......................................................................................................................46

Figure 10. Functional Block Diagram .............................................................................................................49

Figure 11. Widget Diagram ............................................................................................................................50

Figure 12. Desktop Port Configurations .........................................................................................................51

Figure 13. Port Configuration .........................................................................................................................52

Figure 14. Pin Assignment ...........................................................................................................................281

Figure 15. 48QFN Package Diagram ...........................................................................................................284

Figure 16. Solder Reflow Profile ..................................................................................................................285

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

1. DESCRIPTION

1.1. Overview

The 92HD81 is a high fidelity, 4-channel audio codec compatible with the Intel High Definition (HD)

Audio Interface. The 92HD81 codec provides high quality, HD Audio capability notebooks and busi-

ness desktops.

The 92HD81 is designed to meet or exceed premium logo requirements for Microsoft’s Windows

Logo Program (WLP) 3.09 and revisions 4/5 as indicated in WLP 3.09.

The 92HD81 provides stereo 24-bit, full duplex resolution supporting sample rates up to 192kHz by

the DAC and ADC. 92HD81 SPDIF outputs support sample rates of 192kHz, 176.4kHz, 96kHz,

88.2kHz, 48kHz, and 44.1kHz. 92HD81 SPDIF input supports sample rates of 96kHz, 88.2kHz,

48kHz, and 44.1kHz. Additional sample rates are supported by the driver software.

The 92HD81 supports a wide range of notebook and business desktop 4-channel configurations.

The 2 independent SPDIF output interfaces provides connectivity to Consumer Electronic equipment

like Dolby Digital decoders, powered speakers, mini disk drives or to a home entertainment system.

Simultaneous HDMI and SPDIF output is possible.

An integrated BTL stereo amplifier is ideal for driving integrated speakers in mobile and ultra-mobile

computers. For desktop computers or mobile computers using only one speaker, the BTL output

stage may be configured to support a single mono speaker.

MIC inputs can be programmed with 0/10/20/30dB boost. For more advanced configurations, the

92HD81 has 3 General Purpose I/O (GPIO).

The port presence detect capabilities allow the codecs to detect when audio devices are connected

to the codec. Load impedance sensing helps identify attached peripherals for easy set-up and a bet-

ter user experience. The fully parametric IDT SoftEQ can be initiated upon headphone jack insertion

and removal for protection of notebook speakers.

The 92HD81 operates with a 1.5V, 1.8V or 3.3V digital supply and a 5V analog supply. It can also

work with 1.5V and 3.3V HDA signaling; the correct signalling level is selected dynamically based on

the power supply voltage on the DVDD-IO pin.

The 92HD81 is available in a 48-pin QFN Environmental (ROHS) package.

1.2. Orderable Part Numbers

92HD81B1X5NLGXyyX

92HD81B1C5NLGXyyX

5V Analog, Aux Audio mode enabled

5V Analog

Contact IDT if interested in 3.3V Analog.

yy = silicon stepping/revision, contact sales for current data.

Add an “8” to the end for tape and reel delivery. Min/Mult order quantity 2ku.

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

1.3. Block Diagram

Figure 1. 92HD81 Block Diagram

Port A (HP)

Port B (cap-less HP/LO)

Port C

X

Port D (BTL)

Port E

Port F

SPDIF Out 0

SPDIF Out 1

DUAL SPDIF

Figure 2. System Diagram

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

2. DETAILED DESCRIPTION

2.1. Port Functionality

Multi-function (Input / output) ports allow for the highest possible flexibility. 3 or 4 bi-directional ports,

2 headphone ports, and a high power BTL amplifier support a wide variety of consumer desktop and

mobile system use models.

For the 92HD81 codec the port capabilities are as follows

•

Port A supports

•

Headphone

Line Out

Line Input

Mic with 0/10/20/30 dB Boost and Vref_Out

•

Port B supports

•

Capless Headphone Out

Capless Line Out

Port C supports

•

Line Out (not supported on TA revision, if Lineout is needed, please use YD or UA revision)

Line In

Mic with 0/10/20/30 dB boost and Vref_Out

•

Port D supports

•

BTL stereo output

BTL (L+/L-) mono out

Port E supports

•

Line Out

Line In

Mic with 0/10/20/30 dB boost

•

Port F supports

•

Line Out

Line In

Mic with 0/10/20/30 dB boost

•

Mono Out supports

•

Line Out

Pins

Port

Input

Output

Headphone

BTL

Mic Bias

(Vref pin)

Input

boost amp

28/29

31/32

19/20

A

B

C

Yes

(YD/UA

revisions)

40/41/43/44

15/16

D

E

F

Yes

17/18

Table 1. Port Functionality

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

Pins

Port

Input

Output

Headphone

BTL

Mic Bias

(Vref pin)

Input

boost amp

27

48

46

Mono Out

Yes

SPDIF_OUT0

SPDIF_OUT1

DMIC1 (CLK=2)

Yes

4 (CLK=2)

DMIC0

Table 1. Port Functionality

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92HD81

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

2.1.1.

Port Characteristics

Universal (Bi-directional) jacks are supported on ports C (YD and UA revisions only), E, and F. Port

A is birdirectional also. Ports A and B are designed to drive 32 ohm (nominal) headphones or a 10K

(nominal) load. Line Level outputs are intended to drive an external 10K load (nominal) and an on

board shunt resistor of 20-47K (nominal). However, applications may support load impedances of 5K

ohms and above. Input ports are 50K (nominal) at the pin.

DAC full scale outputs and intended full scale input levels are 1V rms at 5V. Line output ports and

Headphone output ports on the 92HD81 codec may be configured for +3dBV full scale output levels

by using a vendor specific verb.

Output ports are always on to prevent pops/clicks associated with charging and discharging output

coupling capacitors. This maintains proper bias on output coupling caps even in power state D3 as

long as AVDD is available. Unused ports should be left unconnected. When updating existing

designs to use the 92HD81 codec, ensure that there are no conflicts between the output ports on the

92HD81 codec and existing circuitry.

AFG Power State Input Enable

Output Enable

Port Behavior

D0-D2

1

Not allowed. Port is active as output. Input path is

mute.

1

0

1

0

Active - Port enabled as input

Active - Port enabled as output

Inactive -port is powered on (low output impedance) but

drives silence only.

D3

-

0

Inactive (lower power) - Port keeps output coupling caps

charged if port uses caps.

-

1

-

Low power state. If enabled, Beep will output from the port

Inactive (lower power) - Port keeps output coupling caps

charged if port uses caps.

Inactive (lower power) - Port keeps output coupling caps

charged if port uses caps.

D3cold

D4

-

D5

Off - Charge on coupling caps (if used) will not be

maintained.

Table 2. Analog Output Port Behavior

2.1.2.

2.1.3.

Vref_Out

Ports C & A support Vref_Out pins for biasing electret cartridge microphones. Settings of 80%

AVDD, 50% AVDD, GND, and Hi-Z are supported. Attempting to program a pin widget control with a

reserved or unsupported value will cause the associated Vref_Out pin to assume a Hi-Z state and

the pin widget control Vref_En field will return a value of ‘000’ (Hi-Z) when read.

Jack Detect

Plugs inserted to a jack on Ports A, B, C & SPDIFOUT0 are detected using SENSE_A. Plugs

inserted to a jack on Ports E,F, DMIC0, & SPDIFOUT1 are detected using SENSE_B. Per ECR15-B,

the detection circuit operates when the CODEC is in D0 - D3 and can also operate if both the

CODEC and Controller are in D3 (no bus clock.) Jack detection requires that all supplies (analog

and digital) are active and stable. When AVDD is not present, the value reported in the pin widget is

invalid.

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When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will

generate a Power State Change Request when a change in port connectivity is sensed and then

generate an unsolicited response after the HD Audio link has been brought out of a low power state

and the device has been enumerated. Per ECR015-B, this will take less than 10mS.

The following table summarizes the proper resistor tolerances for different analog supply voltages.

AVdd Nominal

Voltage (+/- 5%)

Resistor Tolerance Resistor Tolerance

Pull-Up

SENSE_A/B

4.75V

1%

Resistor

SENSE_A

SENSE_B

39.2K

20.0K

10.0K

5.11K

PORT A (HP0)

PORT B (HP1)

PORT C

PORT E

PORT F

DMIC0

SPDIFOUT0

SPDIFOUT1

(DMIC1)

2.49K

Pull-up to AVDD

See reference design for more information on Jack Detect implementation.

2.1.4.

SPDIF Output

Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the

Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with

all consumer audio gear and allows for convenient integration into home theater systems and media

center PCs.

Per the HDA015-B ECR, the SPDIF outputs support the ability to provide clocking information even

when no stream is selected for the converter, or when in a low power state. Also, as stated in the

ECR, the SPDIF output ports support port presence detect.

SPDIF Outputs are outlined in tables below.

Converter

Dig

Enable

AFG Power

State

Output

Enable

Stream

ID

Keep Alive

Enable

RESET#

Pin Behavior

Hi-Z (internal pull-down

enabled) immediately after

power on, otherwise the

previous state is retained.

D0-D3

Asserted (Low)

-

Table 3. SPDIF OUT 0 Behavior

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Converter

Dig

Enable

AFG Power

State

Output

Enable

Stream

ID

Keep Alive

Enable

RESET#

Pin Behavior

De-Asserted

(High)

Disable

d

-

Hi-Z (internal pull-up enabled)

De-Asserted

(High)

Active - Pin drives 0 (internal

pull-down NA)

Enabled Disabled

Enabled Enabled

D0

Active - Pin drives

SPDIF-format, but data is

zeroes (internal pull-down NA)

De-Asserted

(High)

0

-

De-Asserted

(High)

Active - Pin drives SPDIFOut0

data (internal pull-down NA)

Enabled Enabled 1-15

Disable

-

De-Asserted

(High)

Hi-Z (internal pull-down

enabled)

-

d

Active - Pin drives 0 (internal

pull-down NA)

-

0

D1-D2

De-Asserted

(High)

Enabled

Active - Pin drives

SPDIF-format, but data is

zeroes (internal pull-down NA)

Enabled

-

1

Hi-Z (internal pull-down

enabled)

-

0

1

Disable

d

Hi-Z (internal pull-down

enabled)

De-Asserted

(High)

D3

Active - Pin drives

Enabled Enabled

-

1

-

SPDIF-format, but data is

zeroes (internal pull-down NA)

Hi-Z (internal pull-down

enabled)

D3cold

-

D4

D5

-

Hi-Z (port off)

Table 3. SPDIF OUT 0 Behavior

AFG

Power

State

Keep

Alive

En

GPIO0

Enable

Input

Enable

Output

Enable

Converte Strea

r Dig En m ID

RESET#

Pin Behavior

Hi-Z (internal pull-down

enabled) immediately after

power on, otherwise the

previous state is retained.

D0-D3

Asserted (Low)

-

Active - Pin reflects GPIO0

configuration (internal

pull-up enabled)

De-Asserted

(High)

D0-D3

Enabled -

-

Pin functions as digital mic

input (internal pull-down

enabled)

De-Asserted

(High)

Disabled Enabled Disabled -

Table 4. SPDIF OUT 1 Behavior

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AFG

Power

State

Keep

Alive

En

GPIO0

Enable

Input

Enable

Output

Enable

Converte Strea

RESET#

Pin Behavior

r Dig En

m ID

Hi-Z (internal pull-down

enabled)

Disabled Disabled -

-

Active - Pin drives 0

(internal pull-down NA)

Disabled -

Active - Pin drives

SPDIF-format, but data is

zeroes (internal pull-down

NA)

De-Asserted

(High)

D0

Disabled

0

-

Enabled

Active - Pin drives

SPDIFOut1 data (internal

pull-down NA)

1-15

-

Hi-Z (internal pull-down

enabled)

Disabled -

Enabled

-

Active - Pin drives 0

(internal pull-down NA)

Disabled -

De-Asserted

(High)

Active - Pin drives 0

(internal pull-down NA)

D1-D2

Disabled Disabled

-

0

1

Active - Pin drives

SPDIF-format, but data is

zeroes (internal pull-down

NA)

Enabled

Hi-Z (internal pull-down

enabled)

Disabled -

-

Hi-Z (internal pull-down

enabled)

Disabled -

-

De-Asserted

(High)

Hi-Z (internal pull-down

enabled)

D3

Disabled Disabled

0

Enabled

Active - Pin drives

SPDIF-format, but data is

zeroes (internal pull-down

NA)

Enabled

-

1

-

Hi-Z (internal pull-down

enabled)

D3cold

-

Disabled Disabled -

-

D4

D5

-

Hi-Z (port off)

Table 4. SPDIF OUT 1 Behavior

2.2. Mono Output

The MONO Output has an independent mute (see the Widget listing for details). The MONO Output

derives its input from the output of the summing node after the mono mux. The following sources are

available for the mono pin:

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DAC0 Output: When selected (by using port connection list), both DAC0 outputs are summed

together.

DAC1 Output: When selected (by using port connection list), both DAC1 outputs are summed

together.

Mixer Output: When selected (by using port connection list), both mixer outputs are summed

together.

The stereo inputs are scaled by -6dB and then summed to provide an output that is the average of

the two inputs. The full scale output at mono out is designed to be about 0dBV. It is not possible to

adjust to a +3dBV output level.

2.3. Analog Mixer

The mixer supports independent gain (-34.5 to +12dB in 1.5dB steps) on each input as well as inde-

pendent mutes on each input. The following inputs are available:

•

Port A

Port C

Port E

Port F

2.4. ADC Multiplexers

The 92HD81 codec implements 2 ADC input multiplexers. These multiplexers incorporate the ADC

record gain function (0 to +22.5dB gain in 1.5dB steps) as an output amp and allow a preselection of

one of 7 possible inputs:

•

Port A

Port C

Port E

Port F

Mixer Output

DMIC 0

DMIC 1

2.5. Power Management

The HD Audio specification defines power states, power state widgets, and power state verbs.

Power management is implemented at several levels. The Audio Function Group (AFG) , all con-

verter widgets, and all pin complexes support the power state verb F05/705. Converter widgets are

active in D0 and inactive in D1-D3.

The following table describes what functionality is active in each power state.

D1¹

Function

D0

D2

D3

D3cold

Vendor

Specific D4 SpecificD5

Vendor

SPDIF Outputs

On

On(idle)

On(idle)⁵

Off

Digital Microphone inputs

On

Off

DAC

D2S

ADC

Table 5. Power Management

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D1¹

Function

D0

D2

D3

D3cold

Vendor

Specific D4 SpecificD5

Vendor

ADC Volume Control

Ref ADC

On

Off

On

Off

On

Off

On⁵

Off

On

Off

On

Off

Analog Clocks

GPIO pins

VrefOut Pins

Input Boost

Analog mixer

Mixer Volumes

Analog PC_Beep

Digital PC_Beep

Lo/HP Amps

On

Off

On

Off

On

On⁵

2

Low Drive Low Drive Low Drive

2

Capless HP Amps

BTL Amp

On

Off

Low Drive Low Drive Low Drive

2

Off

Low Drive

3

VAG amp

Low Drive Low Drive

Low Drive

4

Port Sense

Off

On

Reference Bias generator

Reference Bandgap core

HD Audio-Link

On

Limited

On

Off

5

On

Table 5. Power Management

1. No DAC or ADC streams are active. Analog mixing and loop thru are supported.

2. VAG is kept active when ports are disabled or in D3/D3cold/D4. PC_Beep is supported in D3 but may be attenuated and

distorted depending on load impedance.

3. VAG is always ramped up and down gradually, except in the case of a sudden power removal. VAG is active in D2/D3 but

in a low power state.

4. Both AVDD and DVDD must be available for Port Sense to operate.

5. Not active if BITCLK is not running (Controller in D3), but can signal power state change request (PME)

The D3-default state is available for HD Audio compliance. The programmable values, exposed via

vendor-specific settings, are under IDT Device Driver control for further power reduction. The analog

mixer, line and headphone amps, port presence detect, and internal references may be disabled

using vendor specific verbs. Use of these vendor specific verbs will cause pops.

The default power state for the Audio Function Group after reset is D3.

2.6. AFG D0

The AFG D0 state is the active state for the device. All functions are active if their power state (if they

support power management at their node level) has been set to D0.

2.7. AFG D1

2.8. AFG D2

D1 is a lower power mode where all converter widgets are disabled. Analog mixer and port functions

are active. The part will resume from theD1 to theD0 state within 1 mS.

The D2 state further reduces power by disabling the mixer and port functions. The port amplifiers

and internal references remain active to keep port coupling caps charged and the system ready for a

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quick resume to either the D1 or D0 state. The part will resume from the D2 state to the D0 state

within 2mS.

2.9. AFG D3

The D3-default state is available for HD Audio compliance. All converters are shut down. Port ampli-

fiers and references are active but in a low power state to prevent pops. Resume times may be lon-

ger than those from D2, but still less than 10mS to meet Intel low power goals. The default power

state for the Audio Function Group after power is applied is D3.

The traditional use for D3 was as a transitional state before power was removed (D3 cold) before the

system entered into standby, hibernate, or shut-down. To conserve power, Intel now promotes using

D3 whenever there are no active streams or other activity that requires the part to consume full

power. The system remains in S0 during this time. When a stream request or user activity requires

the CODEC to become active, the driver will immediately transition the CODEC from D3 to D0. To

enable this use model, the CODEC must resume within 10mS and not pop. Intel HDA ECR-15b /

Low Power White paper power goals are < 30mW when analog PC_Beep is not enabled, and <

60mW when analog PC_Beep is enabled. (Charge pump and BTL amplifier power excluded.)

While in AFG D3, the HD Audio controller may be in a D0 state (HD Audio bus active) or in a D3

state (HD Audio bus held in reset with no Bit_Clk, SData_Out, or Sync activity.) The expected behav-

ior is as follows (see the ECR15b section for more information):

Function

HDA Bus active

HDA Bus stopped

1

Port Presence Detect

state change

Unsolicited Response

Wake Event followed

by an unsolicited

response

GPIO state change

Unsolicited Response

Wake Event followed by

an unsolicited response

1.The Port Presence detect circuit is currently dependent on a clock and

must be changed to generate a wake event.

2.9.1.

AFG D3cold

The D3cold power state is the lowest power state available that does not use vendor specific verbs.

While in D3cold, the CODEC will still respond to bus requests to revert to a higher power state (dou-

ble AFG reset, link reset). However, audio processing, port presence detect, and other functions are

disabled. Per the HD Audio bus ECR 015b, the D3cold state is intended to be used just prior to

removing power to the CODEC. Typically, power will be removed within 200mS. However, the codec

may exit from the D3cold state by generating 2, back-to-back, AFG reset events. Resume time from

D3cold is less than 200mS.

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2.10. Vendor Specific Function Group Power States D4/D5

The 92HD81 introduces vendor specific power states. A vendor defined verb is added to the Audio

Function Group that combines multiple vendor specific power control bits into logical power states

for use by the audio driver. The 2 states defined offer lower power than the 5 existing states defined

in the HD Audio specification and ECR15b. The Vendor Specific D4 state provides lower digital

power consumption relative to D3cold by disabling HD Audio link responses. Vendor specific D5 fur-

ther reduces power consumption on the digital supply by turning off GPIO drivers, and reduces ana-

log power consumption by turning off all analog circuitry except for reset circuits.

States D4/D5 are not entered until D3cold has been requested. Software can pre-program the D4 or

D5 state as a re-definition of how the part will behave when the D3cold power state is requested or

software may enter D3cold, then set the D4 or D5. The preferred method is to request D3cold, then

select D4 or D5 as desired.This will reduce the severity of pops encountered when entering D4 or

D5.

Both power states require a link reset or removal of DVDD to exit.

The CODEC may pop when using these verbs and transition times to an active state (D1 or D0 for

example) may take several seconds.

2.11. Low-voltage HDA Signaling

The 92HD81 codec is compatible with either 1.5V or 3.3V HDA bus signaling; the voltage selection is

done dynamically based on the input voltage of DVDD_IO.

DVDD_IO is currently not a logic configuration pin, but rather provides the digital power supply to be

used for the HDA bus signals.

When in 1.5V mode, the 92HD81 codec can correctly decode BITCLK, SYNC, RESET# and SDO as

they operate at 1.5V; additionally it will drive SDI and SDO at 1.5V. None of the GPIOs are affected,

as they always function at their nominal voltage (DVDD or AVDD).

2.12. Multi-channel capture

The capability to assign multiple “ADC Converters” to the same stream is supported to meet the

microphone array requirements of Vista and future operating systems. Single converter streams are

still supported this is done by assigning unique non zero Stream IDs to each converter. All capture

devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-

tions regarding digital microphones.

The ADC Converters can be associated with a single stream as long the sample rate and the bits per

sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget

and is restricted to even values. The ADC converters will always put out a stereo sample and there-

fore require 2 channels per converter.

The stream will not be generated unless all entries for the targeted converters are set identically, and

the total number of assigned converter channels matches the value in the NmbrChan field. These

are listed the “Multi-Converter Stream Critical Entries.” table.

An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-

nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero

stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-

ber of channels must be set to 4 channels “NmbrChan = 0011”.

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ADC1 CnvtrID

ADC0 CnvtrID

(NID = 0x08)

[3:0]

(NID = 0x07)

[3:0]

Ch = 2

Ch=0

Table 6. Example channel mapping

Figure 3. Multi-channel capture

ADC0.CnvrtID.Channel = 0

ADC1.CnvrtID.Channel = 2

Data

Length

ADC0

Left Channel

ADC0

Right Channel

ADC1

Left Channel

ADC1

Right Channel

Stream ID

ADC0.CnvrtID.Channel = 2

ADC1.CnvrtID.Channel = 0

Data

Length

ADC1

Left Channel

ADC1

Right Channel

ADC0

Left Channel

ADC0

Right Channel

Stream ID

The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.

Figure 4. Multi-channel timing diagram

BITCLK

SDI

ADC0

L23

ADC0

L0

ADC0

R23

ADC0

R0

ADC1

L23

ADC1

L0

ADC1

R23

ADC1

R0

0

1

0

1

0

STREAM ID

DATA LENGTH

LEFT

RIGHT

LEFT

RIGHT

STREAM TAG

ADC0

ADC1

DATA BLOCK

ADC[1:0] Cnvtr

Bit Number

[15]

Sub Field Name

Description

StrmType

Stream Type (TYPE):

0: PCM

1: Non-PCM (not supported)

Sample Base Rate

0= 48kHz

[14]

FrmtSmplRate

SmplRateMultp

1=44.1KHz

[13:11]

Sample Base Rate Multiple

000=48kHz/44.1kHz or less

001= x2

010= x3 (not supported)

011= x4

100-111= Reserved

Table 7: Mult-channel

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[10:8]

SmplRateDiv

Sample Base Rate Divisor

000= Divide by 1

001= Divide by 2 (not supported)

010= Divide by 3 (not supported)

011= Divide by 4 (not supported)

100= Divide by 5 (not supported)

101= Divide by 6 (not supported)

110= Divide by 7 (not supported)

111= Divide by 8 (not supported)

Bits per Sample

000= 8 bits (not supported)

001= 16 bits

010= 20 bits

011= 24 bits

100-111= Reserved

[6:4]

[3:0]

BitsPerSmpl

NmbrChan

Number of Channels

Number of channels for this stream in each “sample

block” of the “packets” in each “frame” on the link.

0000=1 channel (not supported)

0001 = 2 channels

…

1111= 16 channels.

[7:4]

[3:0]

Strm

Ch

Software-programmable integer representing link

stream ID used by the converter widget. By conven-

tion stream 0 is reserved as unused.

Integer representing lowest channel used by con-

verter.

0 and 2 are valid Entries

If assigned to the same stream, one ADC must be

assigned a value of 0 and the other ADC assigned a

value of 2.

Table 7: Mult-channel

2.13. Digital Microphone Support

The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the

DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry

individual channels of digital microphone data to the ADC. In the event that a single microphone is

used, the data is ported to both ADC channels. This mode is selected using a vendor specific verb

and the left time slot is copied to the ADC left and right inputs.

The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-

chronous to the internal master clock. The default frequency is 2.352Mhz.

The two DMIC data inputs are reported as two stereo input pin widgets that incorporate a boost

amplifier. The pin widgets are shown connected to the ADCs through the same multiplexors as the

analog ports. Although the internal implementation is different between the analog ports and the dig-

ital microphones, the functionality is the same. In most cases, the default values for the DMIC clock

rate and data sample phase will be appropriate and an audio driver will be able to configure and use

the digital microphones exactly like an analog microphone.

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To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected.

When switching from the digital microphone to an analog input to the ADC, the analog portion of the

ADC will be brought back to a full power state and allowed to stabilize before switching from the dig-

ital microphone to the analog input. This should take less than 10mS.

DMIC pin widgets support port presence detect directly using SENSE-B input.

The codec supports the following digital microphone configurations:

Digital Mics

Data Sample

ADC Conn.

Notes

0

1

N/A

No Digital Microphones

Single Edge

0, or 1

Available on either DMIC_0 or DMIC_1

When using a microphone that supports multiplexed operation (2-mics

can share a common data line), configure the microphone for “Left” and

select mono operation using the vendor specific verb.

“Left” D-mic data is used for ADC left and right channels.

2

3

4

Double Edge on

either DMIC_0 or

1

0, or 1

Available on either DMIC_0 or DMIC_1, External logic required to support

sampling on a single Digital Mic pin channel on rising edge and second

Digital Mic right channel on falling edge of DMIC_CLK for those digital

microphones that don’t support alternative clock edge (multiplexed output)

capability.

Double Edge on

one DMIC pin and

Single Edge on

the second DMIC

pin.

Requires both DMIC_0 and DMIC_1, External logic required to support

sampling on a single Digital Mic pin channel on rising edge and second

Digital Mic right channel on falling edge of DMIC_CLK for those digital

microphones that don’t support alternative clock edge (multiplexed output)

capability. Two ADC units are required to support this configuration

Double Edge

Connected to DMIC_0 and DMIC_1, External logic required to support

sampling on a single Digital Mic pin channel on rising edge and second

Digital Mic right channel on falling edge of DMIC_CLK for those digital

microphones that don’t support alternative clock edge capability. Two

ADC units are required to support this configuration

Power State DMIC Widget

Enabled?

DMIC_CLK

Output

DMIC_0,1

Notes

D0

Yes

Clock Capable Input Capable DMIC_CLK Output is Enabled when either DMIC_0 or

DMIC_1 Input Widget is Enabled. Otherwise, the

DMIC_CLK remains Low

D1-D3

D0-D3

D4

Yes

No

-

Clock

Disabled

Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down

Clock

Disabled

Clock

Disabled

D5

-

Clock

Disabled

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Figure 5. Single Digital Microphone (data is ported to both left and right channels

Off-Chip

On-Chip

DMIC_0

OR

DMIC_1

Digital

Microphone

Single Line In

Stereo Channels

Output

STEREO

ADC0 or 1

PCM

DMIC_CLK

On-Chip

Multiplexer

Single Microphone not supporting multiplexed output.

DMIC_0

Valid Data

Or

DMIC_1

Right

Left

Channel Channel

DMIC_CLK

Single “Left” Microphone, DMIC input set to mono input mode.

DMIC_0

Valid Data

Or

DMIC_1

Left & Right

Channel

DMIC_CLK

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Figure 6. Stereo Digital Microphone Configuration

Off-Chip

On-Chip

External

Multiplexer

Digital

On-Chip

Multiplexer

Microphones

DMIC_0

Or

DMIC_1

Stereo Channels

Output

STEREO

ADC0 or 1

PCM

DMIC_CLK

DMIC_0

Valid

Data R

Valid

Data L

Valid

Data R

Valid

Data L

Valid

Data R

Or

DMIC_1

Right

Left

Channel Channel

DMIC_CLK

Note: Some Digital Microphone Implementations support data on either edge, therefore, the

external mux may not be required.

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Figure 7. Quad Digital Microphone Configuration

Off-Chip

On-Chip

Digital

Microphones

External

Multiplexer

On-Chip

Multiplexer

Stereo Channels

Output For

DMIC_0

DMIC_0 L&R

STEREO

ADC0

PCM

DMIC_CLK

On-Chip

Multiplexer

Stereo Channels

Output For

DMIC_1 L&R

DMIC_1

STEREO

ADC1

PCM

External

Multiplexer

Digital

Microphones

Valid

Data R0

Data L0

Data R0

Data L0

Data R0

DMIC_0

Valid

Data R1

Data L1

Data R1

Data L1

Data R1

DMIC_1

Right

Left

Right

Left

Channel

Channel Channel Channel

DMIC_CLK

Note: Some Digital Microphone Implementations support data on either edge, in this case the

external multiplexer isn’t required.

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2.14. Analog PC-Beep

The codec does not support automatic routing of the PC_Beep pin to all outputs when the HD-Link is

in reset. Analog PC-Beep may be supported during HD-Link Reset if analog PC_Beep is manually

enabled before entering reset and the level shifters are locked. Analog PC_Beep is mixed at the port

and only ports enabled as outputs will pass PC_Beep. Analog PC_Beep (or a digital equivalent)

must not prevent passing WLP when analog PC_Beep is enabled. Analog PC_Beep, when enabled,

must not prevent other audio sources from playing (we must mix not mux.) An activity monitor will

allow the BTL amplifier (and cap-less headphone amplifiers if possible) to remain in shutdown when

the function group is in D3 until the beep pin is active and then quickly change to an active state

(within 10mS) to pass the beep tone. Beeps from ICH (from Beep.sys) can have a frequency of

about 37Hz to about 32KHz. Beep duration is programmable from 1mS to about 32 seconds. A typi-

cal beep under Windows XP is 500Hz or 2KHz and lasts 75ms or 150mS. Due to external XOR

gates used as mixers, the idle state may be logic 0 or logic 1.

PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-

ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-

ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless

the output amplitude is reduced.

Analog PC_Beep is not supported in D3 Cold, or the vendor specific states D4/D5.

2.15. Digital PC-Beep

This block uses an 8-bit divider value to generate the PC beep from the 48kHz HD Audio Sync

pulse. The digital PC_Beep block generates the beep tone on all Pin Complexes that are currently

configured as outputs. The HD Audio spec states that the beep tone frequency = (48kHz HD Audio

SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarithmic scale). Other audio

sources are disabled when digital PC_Beep is active.

It should be noted that digital PC Beep is disabled if the divider = 00h.

PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-

ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-

ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless

the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will

prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to

indicate that the part requires a clock.

2.16. Headphone Drivers

The codec implements capless headphone outputs. The Microsoft Windows Logo Program allows

up to the equivalent of 100ohms in series. However, an output level of +3dBV at the pin is required to

support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Microsoft allows device

and system manufactures to limit output voltages to address EU safety requirements. (WLP 3.09 -

please refer to the latest Windows Logo Program requirements from Microsoft.)

The capless headphone drivers are supplied with +/-2.5V derived from AVDD. Therefore, it is possi-

ble to run the headphone supply from 5V and maintain ~60mW peak output power into 32 ohm

headphones. Headphone performance will degrade if more than one port is driving a 32 ohm load.

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2.17. EAPD

The EAPD pin (pin 47) is a dedicated, bi-directional control pin. Although named External Amplifier

Power Down (EAPD) by the HD Audio specification, this pin operates as an external amplifier power

up signal. The EAPD value is reflected on the EAPD pin; a 1 causes the external amplifier to power

up (equivalent to D0), and a 0 causes it to power down (equivalent to D3.) When the EAPD value =

1, the EAPD pin must be placed in a state appropriate to the current power state of the associated

Pin Widget even though the EAPD value (in the register) may remain 1. The default state of this pin

is 0 (driving low.) The pin defaults to an open-drain configuration (an external pull-up is recom-

mended.)

Per the HD Audio specification and ECR15b, multiple ports may control EAPD. The EAPD pin

assumes the highest power state of all the EAPD bits in all of the pin complexes. The default value of

EAPD is 1 (powered on), but the FG power state will override and the pin will be low. A port will

request External Amp Power Up when its power state is active (FG and pin widget power state is D1

or D0) or (Analog PC_Beep is enabled and port is enabled as an output) and the port’s EAPD bit is

set to 1. The state of the EAPD pin (unless configured as an input or held low by an external circuit

when configured as an open drain output) will be the logical OR of the external amp power up

requests from all ports.

By default, the EAPD pin also functions as the Mute#/ShutDown# input for the internal BTL amplifier.

In this mode, a low value at the pin (either due to internal EAPD being 0, or to an external entity forc-

ing the pin low) will cause the internal BTL amplifier to mute or enter a low power state depending on

the amplifier configuration. (See below)

Vendor specific verbs are available to configure this pin. These verbs retain their values across link

and single function group resets but are set to their default values by a power on reset:

MODE1

MODE0

EAPD Pin Function

Open Drain I/O

CMOS Output

CMOS Input

Description

0

1

0

1

0

1

Value at pin is wired-AND of EAPD bit and external signal. (default)

Value of EAPD bit in pin widget is forced at pin

External signal controls internal amps. EAPD bit in pin widget ignored

CMOS Input

Control Flag

Description

EAPD PIN

MODE 1:0

Defines if EAPD pin is used as input, output, or bi-directional port (Open Drain)

BTL/HP SD

0 = Amp controlled by EAPD pin only (default) / 1 = Amp controlled by power state (pin and FG) only

0 = Amp will mute when disabled. (default) / 1 = Amp will shut down (enter a low power state) when disabled

BTL/HP SD

MODE

0 = AMP will power down (or mute) when EAPD pin is low (default) / 1 = Amp will power down (or mute) when EAPD

pin is high.

BTL/HP SD INV

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BTL SD

MODE

EAPD Pin

State

BTL SD

BTL SD INV

Amp State

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Amplifier is mute (default¹)

Amplifier is active

Amplifier is mute

Amplifier is in a low power state

Amplifier is active

Amplifier is in a low power state

Amplifier follows pin/function group power state and will mute

when disabled

1

0

1

NA

Amplifier follows pin/function group power state and will enter a

low power state when disabled

Table 8. BTL Amp Status

1.EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group is not in

D0. The state after a single or double function group reset will be compliant with ECR15b.

HP SD

MODE

HP SD INV

EAPD Pin

State

Headphone Amp State

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Amplifier is mute (default¹)

Amplifier is active

Amplifier is mute

Amplifier is in a low power state

Amplifier is active

Amplifier is in a low power state

Amplifier follows pin/function group power state and will

mute when disabled

1

0

1

NA

Amplifier follows pin/function group power state and will

enter a low power state when disabled

Table 9. Headphone Amp Enable Configuration

1.EAPD bit is set to one by default but the EAPD state is 0 after power-on reset because the function group

is not in D0. The state after a single or double function group reset will be compliant with ECR15b.

EAPD Pin value¹

Description

BEEP

Override

Forced to low when in D2 Follows description in HD Audio spec. External amplifier is shut down when pin or function

0

1

or D3

group power state is D2 or D3 independent of value in EAPD bit.

Power state is ignored and EAPD pin follows EAPD bit value only to allow PC_Beep support

in D2 and D3

Always follows EAPD bit

Table 10. EAPD Low Power Behavior

1. When pin is enabled as Open Drain or CMOS output.

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AFG

RESET#

BEEP

EAPD

Pin Behavior

Power

State

Override

Power State

D0-D3

Asserted (Low)

-

Active low immediately after power on, otherwise the

previous state is retained across FG and link reset events

De-Asserted (High)

-

Active - Pin reflects EAPD bit unless held low by external

source.

D0

D0-D1

Active - Pin reflects EAPD bit unless held low by external

source.

D1

D2

D3

De-Asserted (High)

Disabled

Enabled

D0-D2

Pin forced low to disable external amp

Active - Pin reflects EAPD bit unless held low by external

source.

De-Asserted (High)

Disabled

Enabled

D0-D3

Pin forced low to disable external amp

Active - Pin reflects EAPD bit unless held low by external

source.

De-Asserted (High)

-

Pin forced low to disable external amp

Pin Hi-Z (off)

D3cold

D4

D5

Table 11. EAPD Behavior

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Figure 8. HP EAPD Example to be replaced by single pin for internal amp

HP AUDIO CONTROL BLOCK DIAGRAM

SYNC FROM KBC TO OS

OS

SCAN

CODES

SYNC FROM AUDIO GUI TO KBC

A_EAPD

GPIO_1

MUTE +

UP/DOWN

KBC

CODEC

A_SD

BUTTONS

(MUTE LED ON

SAME BOARD)

SPKR_EN#

SPKR AMP

VDD

Internal

Headphone

Amp

Internal BTL

Amp

SD/Mute

EAPD

SD#

External

Power Amp

EAPD PIN

Control

SMU MUTE

OTHER

CODEC

2.18. BTL Amplifier

An integrated class-AB stereo BTL amplifier is provided to directly drive 4 ohm speakers (2W @

4.75V) or 8 ohm speakers (1W @ 4.75V). No external filter is needed for cable runs of 18” or less.

An internal DC blocking filter prevents distortion when the audio source has DC content, and pre-

vents unintentional power consumption when pausing audio playback. The amplifier may be con-

trolled using the EAPD pin (see EAPD section.)

Using a vendor specific verb, the BTL amplifier may be configured to support a mono speaker con-

nected to the L +/- pins. In this mode, the Left and Right audio is mixed and sent to the left output

only. The right channel is turned off to conserve power.

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The BTL amplifier includes thermal management circuitry. When the CODEC reaches a temperature

of about 135 degrees, the output amplitude of the BTL amp is gradually lowered until the tempera-

ture falls below 135.

Maximum gain for the BTL amplifier is programmable. The following 4 gain settings relative to a

nominal line output are desired: +6.5dB, +9.5dB, +14.5dB and +16.5dB. Absolute gain may vary and

the suggested accuracy is +/-1.5dB. The gain is exposed in a vendor specific widget and is intended

to mimic the pin programmable gain implemented in discrete BTL amplifiers commonly used in note-

book computers.

2.19. GPIO

2.19.1. GPIO Pin mapping and shared functions

GPIO Pin

#

Supply SPDIF SPDIF

GPI/O GPI GP VrefOut DMIC VOL

O

Pull

Up

Pull

Down

In

Out

0

1

2

46

2

DVDD

YES

IN

50K

CLK

IN

4

2.19.2. SPDIF/Digital Microphone/GPIO Selection

3 functions are available on the DMIC_1/GPIO0/SPDIFOUT1 pin (pin 46). To determine which func-

tion is enabled, the order of precedence is followed:

1. If the GPIOs are enabled, they override both SPDIF_OUT and Digital Mics

2. If the GPIOs are not enabled through the AFG, then at reset, the pin is pulled low by an internal

pull-down resistor.

3. If the port is enabled as an input, the digital microphones will be used.

4. If the port is enabled as an output, the SPDIF output will be used.

5. In the event that the port is enabled as an input and an output, the port will be an output and the

Digital Mic path will be mute.

2.19.3. Digital Microphone/GPIO Selection

2 functions are available on the DMIC_CLK/GPIO1 (pin 2) and the DMIC_0/GPIO2 (pin 4) pins. To

determine which function is enabled, the order of precedence is followed:

1. If GPIOs are not enabled through the AFG, then at reset, pins 2 and 4 are pulled low by an inter-

nal pull-down resistor.

2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF

use) and pin 2 becomes an internal pull-down.If GPIO2 is enabled through the AFG, pin 4

becomes a GPIO and is pulled low by an internal pull-down resistor.

3. If the port is enabled as an input, the digital microphones will be used.

4. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone

path will be mute.

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2.20. HD Audio ECR 15b support

Although ECR15b is not yet complete (not a DCN), the 92HD81 will implement complete support for

the specification building on the support already present in previous products. ECR 15b features

supported are:

•

Persistence of many configuration options through bus and function group reset.

The ability to support port presence detect in D3 even when the HD Audio bus is in a low power

state (no clock.)

•

Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.

Notification if persistent register settings have been unexpectedly reset.

SPDIF active in D3 (required)

2.21. Digital Core Voltage Regulator

The digital core operates from 1.4 to 1.98V making it compatible with 1.5V (5%) and 1.8V (10%) sup-

ply voltages. Many systems require that the CODEC use a single 3.3V digital supply, so an inte-

grated regulator is included on die. (Parts may be ordered with the regulator disabled). The regulator

uses pin 9, DVDD, as its voltage source. The output of the LDO is connected to pin 1 and the digital

core. A 10uF capacitor must be placed on pin 1 for proper load regulation and regulator stability.

The digital core voltage regulator is only dependent on DVDD. DVDDIO may be either 3.3 or 1.5V

and may proceed or follow DVDD in sequence. The CODEC digital logic and I/O (unless referenced

to AVDD) will operate in the absence of AVDD. DVDD and AVDD supply sequencing for the applica-

tion of power and the removal of power is neither defined nor guaranteed. It is common for desktop

systems to supply AVDD from the system standby supply and the CODEC will tolerate, indefinitely,

the condition where AVDD is active but DVDD and DVDDIO are inactive.

To prevent pops, software is expected to mute paths as close to the port as is possible when chang-

ing power states or signal topology.

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2.22. Aux Audio Support

See Orderable Part Numbers for which codecs offer this feature.

The codec supports an auxiliary audio mode where analog audio is supported by default after power

is supplied with the HD Audio bus disabled. In this mode, an analog input is routed to one of several

output ports depending on jack presence detection.

2.22.1. General conditions in Aux Audio Mode:

•

HD Audio Link is off (RST# is 0, active, and BitClk is 0, inactive. CODEC does not need to mon-

itor BitClk to enter/exit this mode but must not depend on BitClk to operate.)

•

HD Audio CODEC analog and digital supplies are active.

Port A may be an optional headphone jack (Normal and Aux Audio Mode) or an internal micro-

phone port (Normal Mode only / 92HD81 only)

•

Port B connects to the system headphone jack.

Port D connects to the internal speakers.

Port E is AUX Audio out

Port F is AUX Audio In

The internal digital microphone clock is controlled by a source external to the CODEC and the

CODEC will use the DMIC_CLK pin as a clock input. The DMIC0 input is used to process 1 or 2

digital microphone inputs. The expected clock is 3.072MHz.

•

EAPD is used to control the power state of the mixer, BTL amplifier, and headphone amplifiers.

The amplifiers are off if EAPD is held low.

Internal circuitry will delay enabling (change power state, un-mute, etc.) the output amplifiers a

sufficient amount of time after the application of power or EAPD=1 to prevent pops.

•

Internal circuitry will orchestrate power down (EAPD = 0) to prevent pops.

EAPD must be forced low before removing power.

ECR15b considerations: Clock Stop OK or similar communication will be used to prevent prob-

lems when an OS driver attempts to put the HD Audio bus controller into D3 to save power. The

bus must not be placed into reset with the clock stopped or unless EAPD is forced low or D3cold

has been set. The Enable bit in the Aux Audio vendor specific verb is provided so firmware or

other software can disable Aux Audio support and allow stopping the HD Audio bus when an OS

is in an active state. The default value of this bit is determined by a bond option and may be

determined by reading the device ID. This bit only returns to its default value when a power on

reset event is generated.

2.22.2. “Playback Path” Port Behavior

Port F (Aux Audio In) input is routed to Port D (“internal speakers”), Ports A&B (system headphone

ports), and Port E (Aux Audio Out) through the analog mixer.

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2.22.2.1. When Port E Aux Audio Out presence detect = 0

•

Presence detect for Port E = 0 (nothing plugged in)

Port F Aux Audio input is routed to Port A, B, or D when that port is active.

If either Port A or Port B is in use (port presence detect = 1), Port D, internal speakers, will be

inactive (off)

•

The power supply for Port A and B will be active if either A or B is in use but if only one of the two

ports is in use, the other may be turned off to save power.

If neither Port A nor Port B is in use (port presence detect = 0), Port D, internal speakers, will be

active and ports A and B will be inactive.

EAPD is used to indicate if AUX Audio Mode is in use.

2.22.2.2. When Port E Aux Audio Out presence detect = 1

•

Presence detect for Port E = 1 (something plugged in)

Port F Aux Audio input is routed to Ports A, B

Port D is disabled

If either Port A or Port B is in use (port presence detect = 1), that port will be enabled and output

the audio entering Port F.

•

The power supply for Port A and B will be active if either A or B is in use but if only one of the two

ports is in use, the other may be turned off to save power.

If neither Port A nor Port B is in use (port presence detect = 0), ports A and B will be inactive and

the audio on Port F will play through the dock using resources outside of the CODEC.

EAPD is used to indicate if AUX Audio Mode is in use.

Digital PC Beep

Analog Beep

MixerOutVol

HP

Σ

PORT A

HP Jack

DAC0

DAC1

DAC2

Pin Complex

Pins 28/29

Digital PC Beep

MixerOutVol

HP

Σ

PORT B

Pin Complex

Pins 31/32

DAC0

DAC1

DAC2

Digital PC Beep

Class-AB

Internal

Speakers

(Disabled if port A,

B, or E in use)

MixerOutVol

PORT D

DAC0

DAC1

DAC2

BTL

Pin Complex

Pins 39/41/43/44

mute

vol

Port A

DAC0

DAC1

Port C

Port E

Port F

(Disabled)

MixerOutVol

mute

Vol

Σ

-46.5 to 0 dB

In 1.5 dB steps

Mic Bias

(Black River / Hendrix)

LO

-34.5 to +12 dB

In 1.5 dB steps

Mixer and output ports forced on.

Output sent to BTL amp by default but

changed to HP if presence detect

shows HP.

Aux Audio In

Boost

+0/+10/+20/+30 dB

PORT F

Pin Complex

Pins 17/18

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EAPD

(pin)

Aux

Port E Port B Port A

Port C, D, F,

DMIC detect

Port D

behavior

Port B

behavior

Port A

behavior

Support detect detect detect

Enable¹

0

1

NA

disabled

Widget

controlled

Widget

controlled

Widget

controlled

0

NA

enabled

(F to mix to D)

1

0

1

0

1

0

NA

disabled

enabled

(F to mix to A)

disabled

enabled

(F to mix to B)

disabled

enabled

(F to mix to B)

enabled

(F to mix to A)

1

0

1

0

1

0

1

NA

disabled

enabled

(F to mix to A)

disabled

enabled

(F to mix to B)

1

0

1

NA

disabled

enabled

(F to mix to B)

enabled

(F to mix to A)

1.default value for Aux Audio Enable is determined by bond option.

2.22.3. “Record Path” Port Behavior

Digital Microphone input DMIC0 is used as an internal microphone port. The Digital Microphone

clock pin is used as a clock input. The data on the DMIC0 pin is converted into analog audio using

DAC 0 and sent to Port E (Aux Audio Out.) The expected clock input rate is 3.072MHz. Although this

rate is not guaranteed, existing digital microphones are operated from about 1.5-3.2MHz. The

CODEC does not provide gain for the digital microphone path in this mode and external gain of

20-30dB implemented at the output of Port E is expected for acceptable operation. Any DC offset

from the digital microphone is removed by the AC coupling caps required on Port E.

If Port F presence detect = 0, this indicates that nothing is plugged into Aux Audio In and the digital

microphone input is sent to port E. If Port F presence detect = 1, this indicates that an external

source is plugged into the Aux Audio In. The DAC and Port E are disabled.

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+0/+10/+20/+30 dB

Boost

DMIC_0

DMIC

DMIC_0

Pin 4

DMIC_CLK

Pin 2

Digital PC Beep

Analog Beep

MixerOutVol

LO

Σ

DAC0

DAC1

DAC2

DAC 0

Boost

PORT E

Pin Complex

Pins 15/16

Aux Audio Out

(Disabled if Port

F in use)

LO

Mic Bias

Boost

+0/+10/+20/+30 dB

PORT C

Pin Complex

Pins 19/20

MIC Jack

(Disabled)

EAPD

(pin)

Aux

D MIc

Port F

Ports A, B, C,

D, E detect

Port E behavior

Support detect detect

Enable¹

0

1

X

0

X

NA

disabled

Widget controlled

DMIC routed through CODEC DAC to port E. DMIC

Clock provided from external source through DCLK

pin. 3.072MHz typ.

1

0

1

NA

CODEC DAC and Port E disabled

1.default value for Aux Audio Enable is determined by bond option.

2.22.4. EAPD

Since the Aux Audio mode overrides the default behavior but not the actual port settings when in

reset, the logical state of the EAPD pin must be overridden as well. When Aux Audio mode is

enabled and the part is in reset as described above, the logical state of EAPD will be 1 (External

Amplifier Powered Up) unless held low by an external circuit. This ensures that audio pass-thru and

analog PC_Beep will be supported.

2.22.5. Analog PC_Beep

Analog PC_Beep may be supported in Aux Audio mode. By default, analog PC_Beep is disabled. If

the CODEC is programmed to enable analog PC_Beep and Aux Audio mode is enabled, the next

time reset is asserted, the analog PC_Beep pin will be mixed at each of the active outputs.

2.22.6. Firmware/Software Requirements:

If it is desirable to stop the HD Audio bus while the CODEC is in D3 under OS control per ECR-15b,

Firmware must disable the AUX Audio Mode support in the CODEC prior to loading the OS. If Aux

Audio Mode is not disabled in the CODEC, the CODEC will report to the OS driver that stopping the

bus clock while the CODEC is in D3 is not supported or not available.

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3. CHARACTERISTICS

3.1. Electrical Specifications

3.1.1.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 92HD81. These rat-

ings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional

operation of the device at these or any other conditions above those indicated in the operational sec-

tions of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods can affect product reliability. Electrical parameters are guaranteed only over the

recommended operating temperature range.

Item

Maximum Rating

Analog maximum supply voltage

Digital maximum supply voltage

VREFOUT output current

AVdd

DVdd

6 Volts

5.5 Volts

5 mA

Voltage on any pin relative to ground

Operating temperature

Vss - 0.3 V to Vdd + 0.3 V

0 ^oC to +70 ^oC

Storage temperature

-55 ^oC to +125 ^oC

Soldering temperature information for all available in the package

section of this datasheet.

Soldering temperature

Table 12. Electrical Specification: Maximum Ratings

3.1.2.

Recommended Operating Conditions

Parameter

Min.

1.4

Typ.

Max.

1.98

Units

Power Supplies

DVDD_Core

V

DVDD_IO (3.3V signaling)

DVDD_IO (1.5V signaling)

Digital - 3.3 V

3.135

1.418

3.135

3.8

3.3

1.5

3.3

4

3.465

1.583

3.465

4.2

Power Supply Voltage

(Note: With Supply Override

Enable Bit set to force 5V

operation.)

Analog - 4 V

Analog - 4.5 V

Analog - 5 V

4.51

4.75

5

4.99

V

4.75

0

5.25

+70

+95

V

Ambient Operating Temperature

Case Temperature

°C

T_case(48-QFN)

Table 13. Recommended Operating Conditions

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ESD: The 92HD81 is an ESD (electrostatic discharge) sensitive device. The human body and test equipment can

accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the 92HD81 implements

internal ESD protection circuitry, proper ESD precautions should be followed to avoid damaging the functionality or

performance.

3.2. 92HD81 Analog Performance Characteristics (PRELIMINARY)

(Tambient = 25 ºC, AVdd = Supply ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 20Hz to 20KHz swept

sinusoidal input; Sample Frequency = 48 kHz; 0 dB = 1 VRMS, 10KΩ//50pF load, Testbench Char-

acterization BW: 20 Hz – 20 kHz, 0 dB settings on all gain stages)

Conditions

AVdd

Parameter

Digital to Analog Converters

Resolution

Min

Typ

Max

Unit

All

24

Bits

dB

Dynamic Range¹: PCM to All Analog

Outputs

5V

4.75V

93

100

-60dB FS signal level

-

SNR²- DAC to All Mono/Line-Out Ports

THD+N³- DAC to All Mono/Line-Out Ports

SNR²- DAC to All Headphone Ports

THD+N³- DAC to All Headphone Ports

SNR²- DAC to All Headphone Ports

5V

4.75V

95

Analog Mixer Disabled, PCM data

dB

dBr

dB

Analog Mixer Disabled, 0/-1/-3dB FS

Signal, PCM data

5V

4.75V

83

Analog Mixer Disabled, 10KΩ load,

5V

4.75V

95

PCM data

Analog Mixer Disabled, 0/-1/-3dB FS

5V

4.75V

83

dBr

dB

Signal, 10KΩ load, PCM data

Analog Mixer Disabled, 32Ω load,

5V

4.75V

95

PCM data

THD+N³- DAC to All Headphone Ports

Any Analog Input (ADC) to DAC Crosstalk

Analog Mixer Disabled, 0dB FS

Signal, 32Ω load, PCM data

5V

4.75V

68

dBr

10KHz Signal Frequency. 0dBV

signal applied to ADC, DACs idle,

ports enabled as output.

All

-65

-

dB

Any Analog Input (ADC) to DAC Crosstalk

DAC L/R crosstalk

1KHz Signal Frequency

see above

All

dB

DAC to LO or HP 20-15KHz into

65

10KΩ load

DAC L/R crosstalk

Gain Error

DAC to HP 20-15KHz into 32Ω load

Analog Mixer Disabled

All

dB

Hz

0.5

Interchannel Gain Mismatch

Analog Mixer Disabled

D/A Digital Filter Pass Band⁴

20

-

21,000

D/A Digital Filter Pass Band Ripple⁵

D/A Digital Filter Transition Band

D/A Digital Filter Stop Band

0.1

+/- dB

Hz

All

21,000

31,000

-100

-

31,000

-

Hz

D/A Digital Filter Stop Band Rejection⁶

dB

Table 14. 92HD81 Analog Performance Characteristics

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Conditions

AVdd

Parameter

Min

Typ

Max

Unit

D/A Out-of-Band Rejection⁷

Group Delay (48KHz sample rate)

Attenuation, Gain Step Size DIGITAL

DAC Offset Voltage

All

-55

-

1

dB

ms

-

0.75

10

1

-

dB

20

10

mV

deg.

Deviation from Linear Phase

Analog Outputs

Full Scale All Mono/Line-Outs

5V

4.75V

1.00

DAC PCM Data

32Ω load

-

Vrms

Vp-p

Full Scale All Mono/Line-Outs

All Headphone Capable Outputs

Amplifier output impedance

External load Capacitance

5V

4.75V

2.83

5V

4.75V

40

60

mW

(peak)

Mono/Line Outputs

Headphone Outputs

150

0.1

All

Ohms

pF

Mono/Line Outputs

Headphone Outputs

220

-

Analog inputs

Full Scale Input Voltage

0dB Boost @4.75V

(input voltage required for 0dB FS

output)

5V

4.75V

-

Vrms

1.05

All Analog Inputs with boost

5V

10dB Boost

20dB Boost

30dB Boost

-

Vrms

4.75V 0.320

5V

4.75V 0.105

5V

4.75V 0.032

Boost Gain Accuracy

Input Impedance

All

-1

-

dB

KΩ

pF

50

15

-

Input Capacitance

Analog Mixer

-

Dynamic Range: PCM to All Analog

Outputs

-60dB FS signal level Analog Beep

enabled all other mixer inputs mute

5V

4.75V

93

SNR²- All Line-Inputs to all Line Outputs

All inputs unmuted, single line input

driven by ATE.

5V

4.75V

85

-

dB

dBr

dB

THD+N³- All Line-Inputs to all Line

Outputs

0dB Full Scale Input on one input, all

others silent.

5V

4.75V

65

SNR²- DAC to All Line Outputs

Analog Mixer Enabled, PCM data, all

others inputes mute.

5V

4.75V

93

THD+N³- DAC to All Line-Out Ports

Analog Mixer Enabled, 0/-1/-3dB FS

signal, PCM data, all others inputes

unmute/silent

5V

4.75V

83

dBr

dB

SNR²- DAC to All Ports

Analog Mixer Enabled, PCM data, all

others inputes unmute/silent.

5V

4.75V

85

-

Table 14. 92HD81 Analog Performance Characteristics

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Conditions

AVdd

Parameter

Min

Typ

-

Max

Unit

dBr

dB

THD+N³- DAC to All Ports

Analog Mixer Enabled, 0dB FS

Signal, PCM data, all others inputes

unmute/silent

5V

4.75V

75

Attenuation, Gain Step Size ANALOG

Analog to Digital Converter

Resolution

All

-

1.5

-

24

Bits

Full Scale Input Voltage

0dB Boost

(input voltage required to generate

0dBFS per AES 17)

5V

4.75V

1.05

Dynamic Range¹, All Analog Inputs to A/D

High Pass Filer Enabled, -60dB FS,

No boost

5V

4.75V

86

92

dB

SNR²- All Analog Inputs to A/D

Full Scale Input Voltage

5V

4.75V

86

High Pass Filter enabled

-

20dB Boost

(input voltage required to generate

0dBFS per AES 17)

5V

0.105

4.75V 0.105

Dynamic Range¹, All Analog Inputs to A/D

THD+N³All Analog Inputs to A/D

20dB Boost

High Pass Filter Enabled, -60dB FS

5V

4.75V

81

High Pass Filter enabled, -1/-3dB FS

signal level

5V

4.75V

78

dB

20dB Boost, High Pass Filter

enabled, -1/-3dB FS signal level

5V

4.75V

72

Analog Frequency Response⁸

A/D Digital Filter Pass Band⁴

All

10

20

-

30,000

21,000

Hz

A/D Digital Filter Pass Band Ripple⁵

A/D Digital Filter Transition Band

A/D Digital Filter Stop Band

All

0.1

+/- dB

Hz

21,000

31,000

-100

-

31,000

-

Hz

A/D Digital Filter Stop Band Rejection⁶

Group Delay

dB

48 KHz sample rate

1

ms

Any unselected analog Input to ADC

Crosstalk

10KHz Signal Frequency

All

-65

-

dB

Any unselected analog Input to ADC

Crosstalk

1KHz Signal Frequency

All

-65

-

dB

ADC L/R crosstalk

Any selected input to ADC 20-15Khz

DAC to ADC crosstalk

DAC output 0dBFS. All outputs

loaded. Input to ADC open. 20-15Khz

Spurious Tone Rejection⁹

-100

1.5

-

Attenuation, Gain Step Size

(analog)

-

Interchannel Gain Mismatch ADC

Power Supply

-

0.5

Power Supply Rejection Ratio

10kHz

All

-

-60

-

dB

Table 14. 92HD81 Analog Performance Characteristics

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Conditions

1kHz

AVdd

Parameter

Power Supply Rejection Ratio

D0 Didd¹⁰

Min

Typ

-70

25

60

20

34

7

Max

Unit

dB

All

-

3.3V, 1.8V, 1.5V

4.75V

mA

D0 Aidd¹⁰

D0 Didd¹¹

3.3V, 1.8V, 1.5V

4.75V

D0 Aidd¹¹

D1 Didd¹²

3.3V, 1.8V, 1.5V

4.75V

D1 Aidd¹²

30

7

D2 Didd

3.3V, 1.8V, 1.5V

4.75V

D2 Aidd

15

2

D3 (Beep enabled) Didd¹³

D3 (Beep enabled) Aidd¹³

D3 Didd¹³

3.3V, 1.8V, 1.5V

4.75V

10

2

3.3V, 1.8V, 1.5V

4.75V

D3 Aidd¹³

5

D3cold Didd¹³

3.3V, 1.8V, 1.5V

4.75V

1

D3cold Aidd¹³

5

Vendor D4 Didd

Vendor D4 Aidd

Vendor D5 Didd

Vendor D5 Aidd

One Stereo ADC Didd

One Stereo ADC Aidd

One Stereo DAC Didd

One Stereo DAC Aidd

Voltage Reference Outputs

3.3V, 1.8V, 1.5V

4.75V

0.4

5

3.3V, 1.8V, 1.5V

4.75V

0.4

0.6

4

3.3V, 1.8V, 1.5V

4.75

8

3.3V, 1.8V, 1.5V

4.75V

4

6

VREFOut¹⁴

0.5 X

AVdd

All

-

V

mA

V

VREFOut Drive

VREFILT (VAG)

1.6

0.45 X

AVdd

Phased Locked Loop

PLL lock time

All

96

200

500

usec

psec

PLL (or HD Audio Bit CLK) 24MHz clock

jitter

150

ESD / Latchup

Latch-up

As described in JESD78A Class II

As described in JESD22-A114-B

As described in JESD22-C101

All

70

3K

1K

degC

ESD - Human Body Model

Charged Device Model

2K

V

500

Table 14. 92HD81 Analog Performance Characteristics

1.Dynamic Range is the ratio of the full scale signal to the noise output with a -60dBFS signal as defined in AES17 as SNR in the

presence of signal and outlined in AES6id, measured “A weighted” over 20 Hz to 20 kHz bandwidth

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2.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.

(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).

3.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, over 20 Hz to 20 kHz bandwidth.Results at the jack

are dependent on external components and will likely be 1 - 2dB worse.

4.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

5.Peak-to-Peak Ripple over Passband meets ± 0.125dB limits, 48 kHz or 44.1 kHz Sample Frequency. 1dB limit.

6.Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.

7.The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8

to 100 kHz, with respect to a 1 Vrms DAC output.

8.± 1dB limits for Line Output & 0 dB gain, at -20dBV

9.Spurious tone rejection is tested with ADC dither enabled and compared to ADC performance without dither.

10.All functions/converters active, pin complexes enabled, two FDX streams, line (10Kohm) loads. Add 24mA analog current per

stereo 32 ohm headphone.

11.One stereo DAC and corresponding pin widgets enabled (playback mode)

12.Mixer enabled

13.Idle measurement D3 set for minimum clicks/pops (biases and min. amps. on)

14.Can be set to 0.5 or 0.8 AVdd.

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3.3. AC Timing Specs

3.3.1.

HD Audio Bus Timing

Parameter

Definition

Symbol

Min

Typ

Max

Units

23.997

6

24.002

4

BCLK Frequency

Average BCLK frequency

24.0

Mhz

BCLK Period

Period of BCLK including jitter

High phase of BCLK

Low phase of BCLK

BCLK jitter

Tcyc

T_high

T_low

41.163 41.67 42.171

ns

ps

BCLK High Phase

BCLK Low Phase

BCLK jitter

17.5

24.16

500

150

Time after rising edge of BCLK

that SDI becomes valid

SDI delay

SDO setup

SDO hold

T_tco

T_su

T_h

3

5

11

ns

Setup for SDO at both rising and

falling edges of BCLK

Hold for SDO at both rising and

falling edges of BCLK

Table 15. HD Audio Bus Timing

Figure 9. HD Audio Bus Timing

3.3.2.

SPDIF Timing

Parameter

Definition

Symbol

Min

Typ

Max

Units

highest rate of encoded signal

64 times the sample rate

SPDIF_OUT Frequency

2.8224

177.15

3.072

12.288

MHz

SPDIF_OUT unit interval

SPDIF_OUT jitter

1/(128 times the sample rate)

SPDIF_OUT jitter

UI

162.76

40.69

4.43

ns

Table 16. SPDIF Timing

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Parameter

SPDIF_OUT rise time

SPDIF_OUT fall time

Definition

Symbol

T_rise

T_fall

Min

Typ

Max

15

Units

ns

15

ns

Table 16. SPDIF Timing

3.3.3.

Digital Microphone Timing

Parameter

Definition

Average DMIC_CLK frequency

Period of DMIC_CLK

DMIC_CLK jitter

Symbol

Min

Typ

Max

4.704

212.59

5000

Units

MHz

ns

DMIC_CLK Frequency

DMIC_CLK Period

DMIC_CLK jitter

1.176

850.34

2.352

425.17

Tdmic_cyc

ps

Setup for the microphone data at

both rising and falling edges of

DMIC_CLK

DMIC Data setup

DMIC Data hold

Tdmic_su

Tdmic_h

5

ns

Hold for the microphone data at

both rising and falling edges of

DMIC_CLK

Table 17. Digital Mic timing

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3.3.4.

Class-AB BTL Amplifier Performance

Parameter

Min

Typ

Max

Unit

Output Power (BTL 4 ohm, 5V - Continuous Average

Power))

2

W

Output Power (BTL 8 ohm, 5V - Continuous Average

Power))

1

W

Amplifier Efficiency η (4 Ω ,5V, 2W)¹

THD+N (BTL 4 or 8 ohm, 5V, FS)

Frequency Response

60

1

%

20

-

20K

Hz

uV

mA

Output voltage noise

50

0.6

shutdown current

Table 18. Class-AB BTL Amplifier Performance

1. Amplifier efficiency includes circuits specific to the BTL amplifier audio path such as temperature limit, short circuit, and other support circuits.

3.3.5.

Capless Headphone Supply Characteristics

Parameter

Min

Typ

1

Max

Unit

LDO idle current

2

3

6

mA

Cap-less Headphone Amp idle current

Charge Pump idle current

2

4

mA

mS

Charge Pump shutdown time

Charge Pump start-up time

1

10

Table 19. Capless Headphone Supply

Frequency

384

2.2

KHz

uF

C1/C2 cap value

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4. FUNCTIONAL BLOCK DIAGRAMS

TA revision, Port C is input only, if Output is needed use YD or UA revision..

ADC0

PCM to

SPDIF OUT

ADC1

SPDIF OUT1 (shared)

Pin 46

Digital PC Beep

Analog Beep

Stream &

Channel

Select

Mic Bias

MixerOutVol

HP

Σ

DAC0

DAC1

ADC0

ADC1

PCM to

SPDIF OUT

SPDIF OUT0

Pin 48

Boost

+0/+10/+20/+30 dB

Port A

PORT A

Pin Complex

Pins 28/29

Stream &

Channel

Select

Digital PC Beep

Analog Beep

Cap-less

Stream &

Channel

Select

Digital

Mute

vol

DAC0

DAC 0

MixerOutVol

HP

Σ

PORT B

DAC0

DAC1

Pin Complex

Pins 31/32

Digital PC Beep

MixerOutVol

Stream &

Channel

Select

LO

Digital

Mute

DAC0

DAC1

DAC 1

Mic Bias

Boost

+0/+10/+20/+30 dB

Port C

PORT C

Pin Complex

Pins 19/20

Mixer

Port C

Port E

Port F

DMIC0

DMIC1

Port A

0 to +22.5 dB

In 1.5 dB steps

Digital PC Beep

Analog Beep

Class-AB

MixerOutVol

Stream &

Channel

Select

Σ

PORT D

DAC0

DAC1

mute

vol

Gain

ADC0

BTL

Pin Complex

Pins 39/41/43/44

Digital PC Beep

Analog Beep

MixerOutVol

LO

Σ

DAC0

DAC1

Mixer

Port C

Port E

Port F

DMIC0

DMIC1

Port A

0 to +22.5 dB

In 1.5 dB steps

Boost

+0/+10/+20/+30 dB

Port E

PORT E

Pin Complex

Pins 15/16

Stream &

Channel

Select

Digital PC Beep

Analog Beep

mute

vol

Gain

ADC1

MixerOutVol

LO

DAC0

DAC1

Boost

+0/+10/+20/+30 dB

Port F

PORT F

Pin Complex

Pins 17/18

Digital PC Beep

Analog Beep

mute

vol

Port A

DAC0

DAC1

Port C

Port E

Port F

MixerOutVol

LO

Σ

Mono

DAC0

DAC1

mute

Pin Complex

Pin 27

Mixer

Σ

mute

vol

Analog PC_BEEP

MixerOutVol

mute

Vol

0,-6,-12,-18dB

-46.5 to 0 dB

In 1.5 dB steps

-34.5 to +12 dB

In 1.5 dB steps

Digital Microphone volume and mute is

done after the ADC but shown here and in

widget list as same as analog path.

+0/+10/+20/+30 dB

Boost

DMIC_0

DMIC_1

DMIC

DMIC_0

Pin 4

DMIC_1

(shared)

Pin 46

Boost

+0/+10/+20/+30 dB

Figure 10. Functional Block Diagram

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5. WIDGET INFORMATION AND SUPPORTED COMMAND VERBS

TA revision, Port C is input only, if Output is needed use YD or UA revision

NID = 0Ah

-95.25 to 0dB

NID = 13h 0.75dB step

DAC0

HP

DAC1

MIXER

Port A

DAC0

IN VOL

10/20/30

BIAS

DAC0

Port A

NID = 0Bh

-95.25 to 0dB

NID = 14h 0.75dB step

DAC0

HP

DAC1

MIXER

Port B

DAC1

NID = 0Ch

NID = 17h

DAC0

LO

Port C

Port E

Port F

DMIC0

DMIC1

DAC1

MIXER

NID = 15h

ADC0

Port C

IN VOL

10/20/30

BIAS

ADC0

MUX

Port C

NID = 0Dh

0 to 22.5dB

1.5dB step

DAC0

DAC1

MIXER

BTL

Mixer

Port A

Port D

NID = 18h

Port C

Port E

Port F

DMIC0

DMIC1

NID = 16h

ADC1

NID = 0Eh

DAC0

DAC1

MIXER

LO

ADC1

MUX

Port E

IN VOL

10/20/30

0 to 22.5dB

1.5dB step

Mixer

Port A

Port E

NID = 22h

Reserved

NID = 0Fh

DAC0

DAC1

MIXER

LO

Port F

IN VOL

BIAS

10/20/30

Port F

NID = 1Bh

Mixer

Mute Volume

Port A

NID = 1Ch

Mixer

DAC0

DAC1

Port C

Port E

Port F

MixerOutVol

Mixer

OutVol

Mute Volume

Σ

-46.5 to 0dB

in 1.5dB steps

HDA

Link

-34.5 to +12dB

in 1.5dB steps

D – Nodes are Digital Capable

NID = 19h

NID = 1Ah

Mono mix

NID = 10h

DAC0

LO

DAC1

MIXER

Mono mux

Mono

NID = 1Fh

To all ports enabled

as an output

NID = 1Dh

Mute Volume

PC_BEEP (Pin 12)

VSV

Dig0Pin

0,-6,-12,-18dB

Analog*

SPDIF

OUT0

Digital

D

NID = 11h

D

NID = 20h

DMIC0

NID = 1Eh

DMIC0

10/20/30

Dig1Pin

D

SPDIF

OUT1

Digital

NID = 21h

D

Digital

PC_BEEP

To all ports enabled

as an output

NID = 12h

DMIC1 VOL

(VSW)

Digital

DMIC1

Analog*

10/20/30

Figure 11. Widget Diagram

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6. PORT CONFIGURATIONS

6.1. Suggested Desktop Configurations

Desktop 1

Desktop 3

Rear

Front

Rear

Front

B

C

HP

E

A

LO / LI

E

A

F

LI

HP

B

C

MIC / LI

HP

MIC,LI

SPDIF_OUT

MIC (bias

= AVDD)

SPDIF_OUT

HDMI/Display Port

Desktop 4

Desktop 2

Rear

Front

Rear

Front

HP

B

C

A

F

HP

F

E

C

LI

LO

HP

B

A

MIC (bias

= AVDD)

MIC / LI

HP/Mic

MIC / LI

SPDIF_OUT

HDMI/Display Port

Figure 12. Desktop Port Configurations

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6.2. Suggested Mobile Port Configurations

Side

Dock

HP / LO

MIC / LI

HP USING External AMP

MIC / LI

B

A

E

C

OPTION A

HDMI/Display Port

OPTION B

SPDIF_OUT

Internal

A

M

P

D

A

M

P

*EAPD

M

Digital Mic

Array

Digital Mic

External

Port F may be used for internal

analog microphones

Figure 13. Port Configuration

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6.3. Pin Configuration Default Register Settings

The following table shows the Pin Widget Configuration Default settings. Mobile 3-jack implementa-

tion with 3 HP jacks in front and 2 jacks in rear. The internal speaker is redirected from the front

(green) headphone jack, while the other (black) headphone jack and microphone jack may be used

for RTC.

Pin Name

Port

Location

Device

Connection

Color

Misc

Port

Name

PortAPin

Connect to Mainboard

HP Out

2h

1/8 inch Jack Green Jack Detect

3h

1h

2h

Fh

Jack

00b

Front

2h

1h

4h

Override=0

PortBPin

PortCPin

Connect to Mainboard

HP Out

2h

1/8 inch Jack

1h

Black

1h

Jack Detect

Override=0

0h

Jack

00b

Front

2h

Connect to Mainboard

Mic In

Ah

1/8 inch Jack

1h

Pink

9h

Jack Detect

Override=0

Jack

00b

Front

2h

PortDPin

PortEPin*

Internal

10b

NA

010000b

Speaker

1h

Other Analog Unknown Jack Detect

7h 0h Override=0

1/8 inch Jack Green Jack Detect

3h

5h

0h

Connect to Mainboard

Line In

8h

Jack

00b

Rear

1h

4h

Override=0

PortFPin

Connect to Mainboard

Line In

8h

1/8 inch Jack

1h

Pink

9h

Jack Detect

Override=0

4h

0h

Jack

00b

Rear

1h

MonoOutPin

DigOutPin0

Internal

10b

Internal

010000b

Other

Fh

Unknown

0h

Unknown Jack Detect

8h

6h

0h

Override=0

Connect to Mainboard SPDIF Out

optical

5h

Black

1h

Jack Detect

Override=1

Jack

00b

Rear

000001b

4h

DigOutPin1

DigMic0Pin

Connect to

Jack

Internal

011000b

Digital

Other Out

5h

Other Digital Unknown Jack Detect

7h

4h

0h

1h

6h

0h

Override=1

10b

Internal

10b

Internal

010000b

Mic In

Ah

ATAPI

3h

Unknown Jack Detect

0h Override=0

Table 20. Pin Configuration Default Settings

*Revision YB & prior, Port E configuation was device = 0h Line Out.

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PC AUDIO

7. WIDGET INFORMATION

Bits [39:32]

Bits [31:28]

BITS [27:20]

BITS[19:16]

BITS [15:0]

Payload Data (16-bit)

Reserved

CODEC Address

NID

Verb ID (4-bit)

Table 21. Command Format for Verb with 4-bit Identifier

Bits [39:32]

Bits [31:28]

BITS [27:20]

BITS[19:8]

BITS [7:0]

Payload Data (8-bit)

Reserved

CODEC Address

NID

Verb ID (12-bit)

Table 22. Command Format for Verb with 12-bit Identifier

There are two types of responses: Solicited and Unsolicited. Solicited responses are provided as a

direct response to an issued command and will be provided in the frame immediately following the

command. Unsolicited responses are provided by the CODEC independent of any command. Unso-

licited responses are the result of CODEC events such as a jack insertion detection. The formats for

Solicited Responses and Unsolicited Responses are shown in the tables below. The “Tag” field in

bits [31:28] of the Unsolicited Response identify the event.

Bit [35]

Bit [34]

BITS [33:32]

Reserved

BITS[31:0]

Valid (Valid = 1)

UnSol = 0

Response

Table 23. Solicited Response Format

Bit [35]

Bit [34]

BITS [33:32]

BITS[31:28]

Tag

BITS [27:0]

Response

Valid (Valid = 1)

UnSol = 1

Reserved

Table 24. Unsolicited Response Format

7.1. Widget List

ID

Widget Name

Description

Root Node

00h

01h

0Ah

0Bh

Root

AFG

Audio Function Group

Port A

Port B

Port A Pin Widget (Capless Headphone)

Port B Pin Widget (Capless Headphone)

Port C Pin Widget (Line IN/OUT, MIC for YD/UA revisions)

(Line IN, MIC for TA revision)

0Ch

Port C

0Dh

0Eh

Port D

Port E

Port D Pin Widget (BTL output - EAPD control)

Port E Pin Widget (Line IN/OUT)

Table 25. High Definition Audio Widget

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PC AUDIO

ID

Widget Name

Port F

Description

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

Port F Pin Widget (Line IN/OUT, MIC)

MonoOut Pin Widget (output only)

Digital Microphone 0 Pin Widget

Vendor Specific Widget - D-Mic1 volume

Stereo Output Converter to DAC

Stereo Input Converter to ADC

ADC0 Mux with volume and mute

ADC1 Mux with volume and mute

Mono output source select

MonoOut

DigMic0

DigMic1 Vol

DAC0

DAC1

ADC0

ADC1

ADC0Mux

ADC1Mux

Mono Mux

Mono Mix

Mixer

Stereo to mono conversion

Input Mixer (Input Ports, DACs, Analog PC_Beep)

Volume control for analog mixer

Stereo Output for SPDIF_Out

MixerOutVol

SPDIFOut0

SPDIFOut1

Dig0Pin

Second Stereo Output for SPDIF_Out

First Digital Output Pin (pin48)

Dig1Pin

Second Digital Output Pin / DMIC Input Pin (pin 46)

Digital PC Beep

DigBeep

DAC2

Stereo Output Converter to DAC

Table 25. High Definition Audio Widget

55

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PC AUDIO

7.2. Reset Key

Abbreviation

POR

Description

Power On Reset.

SAFG

Single AFG Reset - One single write to the Reset Verb in the AFG Node.

DAFG

Double AFG Reset - Two consecutive Single AFG Resets with only idle frames (if

any) and no Link Resets between.

S&DAFG

LR

Single And Double AFG Reset - Either one will cause reset.

Link Reset - Level sensitive reset anytime the HDA Reset is set low.

ELR

Exiting Link Reset - Edge sensitive reset any time the HDA Reset transitions from

low to high.

ULR

PS

Unexpected Link Reset - Level sensitive reset anytime the HDA Reset is set low

when the ClkStopOK indicator is currently set to 0.

Power State Change - Reset anytime the Actual Power State changes for the Widget

in question.

7.3. Root (NID = 00h): VendorID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0000h

Field Name

Bits

R/W

Default

Reset

Vendor

31:16

R

111Dh

N/A

Vendor ID.

15:8

DeviceFix

R

see below

N/A

Device ID.

7:0

DeviceProg

Device ID.

Device

92HD81B1X (Aux Mode enabled)

92HD81B1C

76D5h

Device ID

7605h

56

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PC AUDIO

7.3.1.

Root (NID = 00h): RevID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0002h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Major

R

1h

N/A (Hard-coded)

Major rev number of compliant HD Audio spec.

19:16 0h N/A (Hard-coded)

Minor rev number of compliant HD Audio spec.

15:12 xh

Vendor's rev number for this device.

11:8 xh

Vendor's rev number for this device.

7:4 xh

Vendor stepping number within the Vendor RevID.

3:0 xh N/A (Hard-coded)

Vendor stepping number within the Vendor RevID.

Minor

R

RevisionFix

RevisionProg

SteppingFix

SteppingProg

R

N/A (Hard-coded)

R

7.3.2.

Root (NID = 00h): NodeInfo

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0004h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:16

StartNID

Rsvd1

R

01h

N/A (Hard-coded)

Starting node number (NID) of first function group

15:8

R

00h

01h

N/A (Hard-coded)

Reserved.

7:0

TotalNodes

R

Total number of nodes

7.4. AFG (NID = 01h): NodeInfo

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0004h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:16

StartNID

Rsvd1

R

0Ah

N/A (Hard-coded)

Starting node number for function group subordinate nodes.

15:8

R

00h

N/A (Hard-coded)

Reserved.

7:0

TotalNodes

R

19h

Total number of nodes.

58

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PC AUDIO

7.4.1.

AFG (NID = 01h): FGType

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0005h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:9

R

000000h

N/A (Hard-coded)

Reserved.

8

UnSol

R

1h

N/A (Hard-coded)

Unsolicited response supported: 1 = yes, 0 = no.

7:0 1h N/A (Hard-coded)

NodeType

R

Function group type:

00h = Reserved

01h = Audio Function Group

02h = Vendor Defined Modem Function Group

03h-7Fh = Reserved

80h-FFh = Vendor Defined Function Group

7.4.2.

AFG (NID = 01h): AFGCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0008h

Field Name

Bits

R/W

Default

Reset

Rsvd3

31:17

Reserved.

16

R

00h

N/A (Hard-coded)

BeepGen

R

1h

N/A (Hard-coded)

Beep generator present: 1 = yes, 0 = no.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Rsvd2

15:12

Reserved.

11:8

R

0h

N/A (Hard-coded)

InputDelay

R

Dh

N/A (Hard-coded)

Typical latency in frames. Number of samples between when the sample is re-

ceived as an analog signal at the pin and when the digital representation is

transmitted on the HD Audio link.

Rsvd1

7:4

R

0h

N/A (Hard-coded)

Reserved.

3:0

OutputDelay

R

Dh

N/A (Hard-coded)

Typical latency in frames. Number of samples between when the signal is re-

ceived from the HD Audio link and when it appears as an analog signal at the

pin.

7.4.3.

AFG (NID = 01h): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:21

Reserved.

20

R

000h

N/A (Hard-coded)

B32

B24

B20

R

0h

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

R

20 bit audio format support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

B16

17

R

1h

N/A (Hard-coded)

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B8

R

N/A (Hard-coded)

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

44.1kHz rate support: 1 = yes, 0 = no.

0h

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

R5

4

R

R4

3

R

R3

2

R

16kHz rate support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

R2

1

R

0h

N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R1

0

R

N/A (Hard-coded)

7.4.4.

AFG (NID = 01h): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

0h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

Float32

PCM

1

R

0

R

7.4.5.

AFG (NID = 01h): InAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Dh

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Field Name

Bits

R/W

Default

Reset

Mute

31

R

0h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

27h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

03h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.4.6.

AFG (NID = 01h): PwrStateCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Fh

Field Name

Bits

R/W

Default

1h

Reset

EPSS

31

R

N/A (Hard-coded)

Extended power states support: 1 = yes, 0 = no.

ClkStop

30

R

1h

N/A (Hard-coded)

D3 clock stop support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

S3D3ColdSup

29

R

1h

N/A (Hard-coded)

Codec state intended during system S3 state: 1 = D3Hot, 0 = D3Cold.

On YB revs & prior, this was called LPD3Sup & default was 0h

Rsvd

28:5

R

000000h

N/A (Hard-coded)

Reserved.

4

D3ColdSup

D3Sup

D2Sup

D1Sup

D0Sup

R

1h

D3Cold power state support: 1 = yes, 0 = no.

1h

D3 power state support: 1 = yes, 0 = no.

1h

D2 power state support: 1 = yes, 0 = no.

1h

D1 power state support: 1 = yes, 0 = no.

1h

D0 power state support: 1 = yes, 0 = no.

3

R

2

R

1

R

0

R

7.4.7.

AFG (NID = 01h): GPIOCnt

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0011h

Field Name

Bits

R/W

Default

Reset

GPIWake

31

R

1h

N/A (Hard-coded)

Wake capability. Assuming the Wake Enable Mask controls are enabled,

GPIO's configured as inputs can cause a wake (generate a Status Change

event on the link) when there is a change in level on the pin.

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Field Name

Bits

R/W

Default

Reset

GPIUnsol

30

R

1h

N/A (Hard-coded)

GPIO unsolicited response support: 1 = yes, 0 = no.

Rsvd

29:24

R

00h

N/A (Hard-coded)

Reserved.

23:16

NumGPIs

NumGPOs

NumGPIOs

R

00h

N/A (Hard-coded)

Number of GPI pins supported by function group.

15:8 00h N/A (Hard-coded)

Number of GPO pins supported by function group.

7:0 03h N/A (Hard-coded)

Number of GPIO pins supported by function group.

R

7.4.8.

AFG (NID = 01h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

02h

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

NumSteps

14:8

R

7Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

Rsvd1

Offset

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

R

7Fh

N/A (Hard-coded)

Indicates which step is 0dB

7.4.9.

AFG (NID = 01h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd3

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Function Group have been reset.

Cleared by PwrState 'Get' to this Widget.

ClkStopOK

Error

9

R

1h

Bit clock can currently be removed: 1 = yes, 0 = no.

0h POR - DAFG - ULR

POR - DAFG - ULR

8

R

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7

R

0h

N/A (Hard-coded)

Reserved.

6:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

3

R

0h

N/A (Hard-coded)

Reserved.

2:0

Set

RW

3h

POR - DAFG - LR

Current power state setting for this widget.

7.4.10. AFG (NID = 01h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable: 1 = enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.4.11. AFG (NID = 01h): GPIO

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

715h

Get

F1500h

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

Data2

Data1

Data0

RW

0h

POR - DAFG - ULR

Data for GPIO2. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

1

RW

0h

POR - DAFG - ULR

Data for GPIO1. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

0

RW

0h

POR - DAFG - ULR

Data for GPIO0. If this GPIO bit is configured as Sticky (edge-sensitive) input,

it can be cleared by writing "0". For details of read back value, refer to HD Audio

spec. section 7.3.3.22

7.4.12. AFG (NID = 01h): GPIOEn

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

716h

Get

F1600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

Mask2

Mask1

RW

0h

POR - DAFG - ULR

Enable for GPIO2: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

1

RW

0h

POR - DAFG - ULR

Enable for GPIO1: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

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Field Name

Bits

R/W

Default

Reset

Mask0

0

RW

0h

POR - DAFG - ULR

Enable for GPIO0: 0 = pin is disabled (Hi-Z state); 1 = pin is enabled; behavior

determined by GPIO Direction control

7.4.13. AFG (NID = 01h): GPIODir

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

717h

Get

F1700h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

Control2

Control1

Control0

RW

0h

POR - DAFG - ULR

Direction control for GPIO2: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

1

RW

0h

POR - DAFG - ULR

Direction control for GPIO1: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

0

RW

0h

POR - DAFG - ULR

Direction control for GPIO0: 0 = GPIO is configured as input; 1 = GPIO is con-

figured as output

7.4.14. AFG (NID = 01h): GPIOWakeEn

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

718h

Get

F1800h

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

W2

W1

W0

RW

0h

POR - DAFG - ULR

Wake enable for GPIO2: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

1

RW

0h

POR - DAFG - ULR

Wake enable for GPIO1: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

0

RW

0h

POR - DAFG - ULR

Wake enable for GPIO0: 0 = wake-up event is disabled; 1 = When HD Audio

link is powered down (RST# is asserted), a wake-up event will trigger a Status

Change Request event on the link.

7.4.15. AFG (NID = 01h): GPIOUnsol

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

719h

Get

F1900h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

EnMask2

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO2. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO2 is configured as input and changes state.

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Field Name

Bits

R/W

Default

Reset

EnMask1

1

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO1. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO1 is configured as input and changes state.

EnMask0

0

RW

0h

POR - DAFG - ULR

Unsolicited enable mask for GPIO0. If set, and the Unsolicited Response con-

trol for this widget has been enabled, an unsolicited response will be sent when

GPIO0 is configured as input and changes state.

7.4.16. AFG (NID = 01h): GPIOSticky

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

71Ah

Get

F1A00h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

Mask2

Mask1

Mask0

RW

0h

POR - DAFG - ULR

GPIO2 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

1

RW

0h

POR - DAFG - ULR

GPIO1 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

0

RW

0h

POR - DAFG - ULR

GPIO0 input type (when configured as input): 0 = Non-Sticky (level-sensitive);

1 = Sticky (edge-sensitive).

7.4.17. AFG (NID = 01h): SubID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

723h

722h

721h

720h

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7.4.17. AFG (NID = 01h): SubID

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F2300h / F2200h / F2100h / F2000h

Field Name

Bits

R/W

Default

Reset

Subsys3

31:24

RW

00h

POR

Subsystem ID (byte 3)

23:16 RW

Subsystem ID (byte 2)

15:8 RW

Subsystem ID (byte 1)

7:0 RW

Subsys2

Subsys1

Assembly

00h

01h

00h

POR

Assembly ID (Not applicable to codec vendors).

7.4.18. AFG (NID = 01h): GPIOPlrty

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

770h

Get

F7000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

GP2

RW

1h

POR - DAFG - ULR

GPIO2 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

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Field Name

Bits

R/W

Default

Reset

GP1

1

RW

1h

POR - DAFG - ULR

GPIO1 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

GP0

0

RW

1h

POR - DAFG - ULR

GPIO0 Polarity:

If configured as output or non-sticky input:

0 = inverting

1 = non-inverting

If configured as sticky input:

0 = falling edges will be detected

1 = rising edges will be detected

7.4.19. AFG (NID = 01h): GPIODrive

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

771h

Get

F7100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

OD2

OD1

RW

0h

POR - DAFG - ULR

GPIO2 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

1

RW

0h

POR - DAFG - ULR

GPIO1 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float

for 1).

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Field Name

Bits

R/W

Default

Reset

OD0

0

RW

0h

POR - DAFG - ULR

GPIO0 Drive Mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float

for 1).

7.4.20. AFG (NID = 01h): DMic

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

778h

Get

F7800h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:6

R

0000000h

N/A (Hard-coded)

Reserved.

5

Mono1

Mono0

PhAdj

RW

0h

POR

DMic1 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

4

RW

0h

POR

DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-

plicated to the right channel).

3:2

RW

0h

POR

Selects what phase of the DMic clock the data should be latched:

0h = left data rising edge/right data falling edge

1h = left data center of high/right data center of low

2h = left data falling edge/right data rising edge

3h = left data center of low/right data center of high

Rate

1:0

RW

2h

POR

Selects the DMic clock rate:

0h = 4.704MHz

1h = 3.528MHz

2h = 2.352MHz

3h = 1.176MHz.

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PC AUDIO

7.4.21. AFG (NID = 01h): DACMode

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

780h

Get

F8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

SDMSettleDisable

SDMCoeffSel

RW

0h

POR

SDM wait-to-settle disable:

1 = at mute, the SDM switches to the mute pattern immediately

0 = at mute, the SDM switches to the mute pattern after settling (can take up to

~45ms)

6

RW

0h

POR

DAC SDM coefficient select (stages 1, 2, 3):

1 = 1/16, 1/2, 1/4

0 = 1/16, 1/4, 1/2

SDMLFHalf

5

RW

0h

POR

DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.

4 RW 0h POR

SDMLFDisable

DAC SDM local feedback disable: 1 = local feedback disabled, 0 = local feed-

back enabled.

InvertValid

3

RW

0h

POR

DAC Valid Invert: 1 = 7.056MHz valid strobe is inverted, 0 = 7.056MHz valid

strobe is not inverted.

InvertData

2

RW

0h

POR

DAC Data Invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert-

ed.

Atten6dBDisable

1

RW

0h

POR

Disable built-in -6dB digital attenuation: 1 = -6dB disabled, 0 = -6dB enabled.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Fade

0

RW

1h

POR

DAC Gain Fade Enable:

1 = gain will be slowly faded from old value to new value (~10ms)

0 = gain will jump immediately to new value.

7.4.22. AFG (NID = 01h): ADCMode

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

784h

Get

F8400h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:4

R

0000000h

N/A (Hard-coded)

Reserved.

3

InvertValid

RW

0h

POR

ADC Valid Invert: 1 = 14.112MHz valid strobe is inverted, 0 = 14.112MHz valid

strobe is not inverted.

InvertData

Rsvd1

2

RW

0h

POR

ADC Data Invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.4.23. AFG (NID = 01h): EAPD

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

788h

Get

F8800h

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:15

Reserved.

14

R

00000h

N/A (Hard-coded)

HPBSDInv

RW

0h

POR

HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPBSDMode

13

RW

0h (YC/YD)

1h (UA/YA)

POR

HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

HPBSD

12

RW

0h

POR

HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd3

11

R

0h

N/A (Hard-coded)

POR

Reserved.

10

HPASDInv

RW

0h

HP Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

HPASDMode

9

RW

0h (YC/YD)

1h (UA/TA)

POR

HP Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

HPASD

Rsvd2

8

RW

0h

POR

HP Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

7

R

0h

N/A (Hard-coded)

Reserved.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

BTLSDInv

6

RW

0h

POR

BTL Amp Shutdown Invert:

0 = Amp will power down (or mute) when EAPD pin is low

1 = Amp will power down (or mute) when EAPD pin is high

BTLSDMode

5

RW

0h (YC/YD)

1h (UA/TA)

POR

BTL Amp Shutdown Mode:

0 = Amp will mute when disabled

1 = Amp will enter a low power state when disabled

BTLSD

4

RW

0h

POR

BTL Amp Shutdown Control Select:

0 = Amp controlled by EAPD pin only

1 = Amp controlled by power state only

Rsvd1

3:2

R

0h

N/A (Hard-coded)

POR

Reserved.

1:0

PinMode

RW

0h

EAPD Pin Mode:

00b = Open Drain I/O (Value at pin is wired-AND of EAPD bit and external sig-

nal)

01b = CMOS Output (Value of EAPD bit is forced at pin)

1xb = CMOS Input (External signal controls internal amps, EAPD bit ignored)

7.4.24. AFG (NID = 01h): PortUse

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7C0h

Get

FC000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:7

R

0000000h

N/A (Hard-coded)

Reserved.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Mono

6

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

PortF

PortE

PortD

PortC

PortB

PortA

5

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

4

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

3

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable.

2

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

1

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable

0

RW

0h (YC/YD)

1h (UA/TA)

POR

1=power down port if not input or output enabled, 0=do not force power down

based on input or output enable.

7.4.25. AFG (NID = 01h): VSPwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7D8h

Get

FD800h

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

D5

D4

RW

0h

POR - ELR

Vendor specific D5 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If set, this bit over-

rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-

ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state

via POR or rising edge of Link Reset.

0

RW

0h

POR - ELR

Vendor specific D4 power state, only entered once the part is already in D3cold

(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)

is set, this bit is overridden. Includes the power savings of D3cold, but addi-

tionally powers down the HDA interface (no responses). Exit this power state

via POR or rising edge of Link Reset.

7.4.26. AFG (NID = 01h): AnaPort

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7EDh

7ECh

Get

FEC00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

Reserved.

6

MonoPwd

FPwd

RW

0h

POR

Power down Mono Output.

RW

Power down Port F.

RW

Power down Port E.

5

EPwd

4

80

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

Field Name

Bits

R/W

Default

Reset

DPwd

3

RW

0h

POR

Power down Port D.

RW

Power down Port C.

RW

Power down Port B.

RW

Power down Port A.

CPwd

BPwd

APwd

2

0h

POR

1

0

7.4.27. AFG (NID = 01h): AnaBeep

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7EEh

Get

FEE00h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

0000000h

N/A (Hard-coded)

Reserved.

2:1

Gain

RW

3h

POR

Analog PC Beep Gain: 0h = -24dB, 1h = -18dB, 2h = -12dB, 3h = -6dB.

0 RW 0h POR

Enable

Analog PC Beep Enable: 1 = Analog PC beep enabled, 0 = Analog PC beep

disabled.

7.4.28. AFG (NID = 01h): AnaBTL YC and YD Revisions

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

7F6h

7F5h

7F4h

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PC AUDIO

7.4.28. AFG (NID = 01h): AnaBTL YC and YD Revisions

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

FF400h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:30

Reserved.

29

R

0h

N/A (Hard-coded)

TSOverHeat

TSAlgVol

R

0h

POR

Temperature sensing overheat indicator.

28:24 17h

R

Temperature sensing volume for the BTL amplifier: 00000b..11111b = Range

specificity for MaxVol field.

Rsvd3

23:22

Reserved.

21

R

0h

N/A (Hard-coded)

TSOverrideReset

RW

0h

POR

Override reset for the BTL amplifier temperature sensing circuit: set to 1 to re-

calculate, set back to 0 to latch the value.

TSOverrideVol

20:16

RW

17h

POR

Override volume for the BTL amplifier: 00000b..11111b = Range specified for

MaxVol field.

TSOverrideSel

Rsvd2

15

RW

0h

POR

Override select for the BTL amplifier volume.

14:12

R

0h

N/A (Hard-coded)

POR

Reserved.

11:8

TSWait

RW

6h (YA rev)

0h

Temperature sensing wait time between volume increments/decrements:

0h..Fh = 0..1.28s in 85.3ms steps.

MonoSel

7

RW

0h

POR

Mono select for the BTL amplifier: 1= mono, 0 = stereo.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Rsvd1

6:5

R

0h

N/A (Hard-coded)

Reserved.

4:0

MaxVol

RW

17h

POR

Gain setting for the BTL amplifier (temperature sensing logic will decrement

from here):

00000 = -26.25dB:

00001 = -19.80dB

00010 = -15.80dB

00011 = -12.85dB

00100 = -10.40dB

00101 = -8.27dB

00110 = -6.35dB

00111 = -4.60dB

01000 = -2.90dB

01001 = -1.25dB

01010 = 0.35dB

01011 = 1.98dB

01100 = 3.63dB

01101 = 5.35dB

01110 = 7.19dB

01111 = 9.18dB

10000 = 9.95dB

10001 = 10.75dB

10010 = 11.58dB

10011 = 12.48dB

10100 = 13.43dB

10101 = 14.46dB

10110 = 15.57dB

10111 = 16.79dB

11000-11111 = Not valid

7.4.29. AFG (NID = 01h): AnaBTL UA and TA Revisions

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7F6h

7F5h

7F4h

Get

FF400h

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Rsvd3

31

R

0h

N/A (Hard-coded)

Reserved.

30

TSTripHighStatus

TSTripLowStatus

TSVolStatus

R

0h

POR

Temp sense high trip point status

29 0h

Temp sense low trip point status

28:24 00h

R

Temp sense volume status for the BTL amplifier: 00000b..11111b = Range

specificity for MaxVol field.

TSMuteStatus

TSPwdStatus

Rsvd2

23

Temp sense forced mute status for the BTL amplifier.

22 0h POR

Temp sense forced powerdown status for the BTL amplifier.

R

0h

POR

R

21

R

0h

N/A (Hard-coded)

Reserved.

20

TSOverrideReset

RW

0h

POR

Override reset for the BTL amplifier temperature sensing circuit: set to 1 to re-

calculate, set back to 0 to latch the value.

TSOverrideSel

TSTestMode

19

RW

0h

POR

Override select for the BTL amplifier volume. Use MaxVol[4:0] and TSOverri-

deReset directly to drive analog

18

RW

0h

POR

Temp sense test mode select, 0=normal operation, 1=sensor will trip at ambi-

ent temperature.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

TSForcePwd

17

RW

0h (UA)

1h (TA)

POR

Temp sense force powerdown select

0=BTL will not be muted and powered down even if it is still overheating when

the volume is 0h

1=BTL will be muted and powered down even if it is still overheating when the

volume is 0h

TSInstantCutMode

16

RW

0h

POR

Temp sense instant cut mode

0=Two trip points used to smoothly adjust the volume

1=One single trip point used to set volume to wither 0 or max value (TI mode)

TSWait

15:12

RW

3h

POR

Temperature sensing wait time between volume increments

0h = 2ms (polling at 2ms)

1h = 4ms (polling at 4ms)

2h = 8ms (polling at 8ms)

3h = 16ms (polling at 16ms)

4h = 32ms (polling at 16ms)

5h = 64ms (polling at 16ms)

6h = 128ms (polling at 16ms)

7h = 256ms (polling at 16ms)

8h = 512ms (polling at 16ms)

9h = 1.024s (polling at 16ms)

Ah = 2.048s (polling at 16ms)

Bh = 4.096s (polling at 16ms)

Ch = 8.192s (polling at 16ms)

Dh = 16.384s (polling at 16ms)

Eh = 32.768s (polling at 16ms)

Fh = 65.536s (polling at 16ms).

TSTripSplit

11:10

RW

0h

POR

Temp sense split setting, determines how many degrees above the low point the

high point is set:

0h = 15 Degrees C

1h = 30 Degrees C

2h = 45 Degrees C

3h = 60 Degrees C.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

TSTripShift

9:8

RW

02h

POR

Temp sense shift setting, determines where the low point is set:

0h = 110 Degrees C

1h = 125 Degrees C

2h = 140 Degrees C

3h = 155 Degrees C

Rsvd1

7:6

R

0h

NA

Reserved

5

MonoSel

MaxVol

RW

0h‘

POR

Mono select for the BTL amplifier, 1=mono, 0=stereo

4:0 RW 0Fh POR

Gain setting for the BTL amplifier (temperature sensing logic will decrement

from here):

00000 = -26.25dB:

00001 = -19.80dB

00010 = -15.80dB

00011 = -12.85dB

00100 = -10.40dB

00101 = -8.27dB

00110 = -6.35dB

00111 = -4.60dB

01000 = -2.90dB

01001 = -1.25dB

01010 = 0.35dB

01011 = 1.98dB

01100 = 3.63dB

01101 = 5.35dB

01110 = 7.19dB

01111 = 9.18dB

10000 = 9.95dB

10001 = 10.75dB

10010 = 11.58dB

10011 = 12.48dB

10100 = 13.43dB

10101 = 14.46dB

10110 = 15.57dB

10111 = 16.79dB

11000-11111 = Not valid

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PC AUDIO

7.4.30. AFG (NID = 01h): AnaCapless

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7FAh

7F9h

7F8h

Get

FF800h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:26

Reserved.

25

R

00h

N/A (Hard-coded)

VRegSCDet

R

0h

POR

Capless regulator short circuit detect indicator.

24 0h POR

Capless charge pump short circuit detect indicator.

ChargePumpSCDet

VRegSel

R

23:20

RW

4h (YC/YD)

3h (UA)

POR

Capless regulator output voltage multiply ratio.

19 RW 0h POR

VRegSCRstB

Capless regulator short circuit detect reset: 0 = short circuit detect disabled, 1

= short circuit detect enabled.

VRegGndShort

VRegPwd

18

Ground the capless regulator output.

17 RW 0h

Capless regulator powerdown.

16 RW 0h

RW

0h

POR

ChargePumpSCRstB

Capless charge pump short circuit detect reset: 0 = short circuit detect dis-

abled, 1 = short circuit detect enabled.

ChargePumpHiZ

15

RW

0h

POR

Hi-Z the capless charge pump outputs.

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

PC AUDIO

Field Name

Bits

R/W

Default

Reset

ChargePumpPwd

14

RW

0h

POR

Capless charge pump powerdown.

ChargePumpSplyDetOver-

ride

13

RW

1h (YA rev)

0h

POR

Capless charge pump supply detect override.

ChargePumpFreqBypass

ChargePumpClkRate

12

RW

1h (YA, YC)

0h (YB rev)

POR

Capless charge pump frequency reg bypass.

11:8

RW

8h

POR

Capless charge pump clock rate:

0000b = 800.0kHz (24MHz/30)

0001b = 750.0kHz (24MHz/32)

0010b = 706.9kHz (24MHz/34)

0011b = 666.7kHz (24MHz/36)

0100b = 631.6kHz (24MHz/38)

0101b = 600.0kHz (24MHz/40)

0110b = 571.4kHz (24MHz/42)

0111b = 545.5kHz (24MHz/44)

1000b = 800.0kHz (24MHz/30)

1001b = 857.1kHz (24MHz/28)

1010b = 923.1kHz (24MHz/26)

1011b = 1.000MHz (24MHz/24)

1100b = 1.091MHz (24MHz/22)

1101b = 1.200MHz (24MHz/20)

1110b = 1.333MHz (24MHz/18)

1111b = 1.500MHz (24MHz/16)

ChargePumpClkDiv

7:5

RW

4h

POR

Capless charge pump analog clock divider:

001b = No divide

010b = Divide by 2, 50% duty cycle

100b = Divide by 4, 50% duty cycle

110b = Divide by 2, 75% duty cycle

011b = Divide by 4, 75% duty cycle

111b = Divide by 4, 87.5% duty cycle

Other values undefined

ChargePumpClkSel

4

RW

0h

POR

Capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock

defined by AFGCaplessChargePumpClkRate[3:0] field below.

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

PadGnd

3

RW

0h

POR

Ground the output pad of the capless amplifiers.

RW 0h POR

Ground the input to the capless output amplifiers.

0h POR

InputGnd

Reserved

2

1

R

Revisions YC & prior was capless headphone amplifier gain. This bit is no lon-

ger neded..

AntiPopBypass

0

RW

0h

POR

Revision YC & prior was capless headphone gain. This bit has been repur-

posed for Anti-Pop bypass..

7.4.31. AFG (NID = 01h): Reset

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

7FFh

Get

FFF00h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:0

Execute

W

00h

N/A (Hard-coded)

Function Reset. Function Group reset is executed when the Set verb 7FF is

written with 8-bit payload of 00h. The codec should issue a response to ac-

knowledge receipt of the verb, and then reset the affected Function Group and

all associated widgets to their power-on reset values. Some controls such as

Configuration Default controls should not be reset. Overlaps Response.

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7.4.32. AFG (NID = 01h): AuxAudio

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

774h

Get

F7400h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

MixerPwd

Enable

RW

0h

POR

Aux Audio Moder mixer powerdown: 0 = Mixer enabled during Aux Audio

Mode, 1 = Mixer forced powered down during Aux Audio Mode.

0

RW

1h

POR

Aux Audio Mode select: 0 = Aux Audio disabled, 1 = Aux Audio enabled during

HDA Link Reset.

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7.5. PortA (NID = 0Ah): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.5.1.

PortA (NID = 0Ah): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

R

0000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

17h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

1h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

0h

N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

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7.5.2.

PortA (NID = 0Ah): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.5.3.

PortA (NID = 0Ah): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

23:16 1Ch

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

ConL2

ConL1

R

N/A (Hard-coded)

R

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Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

13h

N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.5.4.

PortA (NID = 0Ah): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.5.5.

PortA (NID = 0Ah): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.5.6.

PortA (NID = 0Ah): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.5.7.

PortA (NID = 0Ah): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.5.8.

PortA (NID = 0Ah): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPhnEn

OutEn

InEn

RW

0h

POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

RW 0h

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

6

POR - DAFG - ULR

N/A (Hard-coded)

5

Rsvd1

4:3

R

0h

Reserved.

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Field Name

Bits

R/W

Default

Reset

VRefEn

2:0

RW

0h

POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.5.9.

PortA (NID = 0Ah): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.5.10. PortA (NID = 0Ah): ChSense

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

709h

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7.5.10. PortA (NID = 0Ah): ChSense

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.5.11. PortA (NID = 0Ah): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.5.12. PortA (NID = 0Ah): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

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Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

02h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

2h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

4h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

Fh

POR

Default assocation.

3:0

RW

Sequence.

7.6. PortB (NID = 0Bh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

00h

Reset

Rsvd2

31:24

R

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

1h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

Striping support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

FormatOvrd

4

R

0h

N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.6.1.

PortB (NID = 0Bh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

0h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

1h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.6.2.

PortB (NID = 0Bh): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

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7.6.2.

PortB (NID = 0Bh): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.6.3.

PortB (NID = 0Bh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

23:16 1Ch

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

7:0 13h

DAC0 Converter widget (0x13)

ConL2

ConL1

ConL0

R

N/A (Hard-coded)

R

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7.6.4.

PortB (NID = 0Bh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.6.5.

PortB (NID = 0Bh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.6.6.

PortB (NID = 0Bh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPhnEn

OutEn

RW

0h

POR - DAFG - ULR

Headphone amp enable: 1 = enabled, 0 = disabled.

6

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

Rsvd1

5:0

RW

00h

Reserved.

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7.6.7.

PortB (NID = 0Bh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.6.8.

PortB (NID = 0Bh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

Reset

PresDtct

31

R

0h

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

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PC AUDIO

7.6.9.

PortB (NID = 0Bh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.6.10. PortB (NID = 0Bh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

02h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

2h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

1h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

1h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.7. PortC (NID = 0Ch): WCap

TA revision, Port C is input only, if Output is needed use YD or UA revision.

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

SwapCap

PwrCntrl

Dig

15:12

Reserved.

11

R

0h

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

R

9

R

Digital stream support: 1 = yes (digital), 0 = no (analog).

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Field Name

Bits

R/W

Default

Reset

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

1h

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.7.1.

PortC (NID = 0Ch): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

VrefCntrl

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

15:8

R

17h

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

Trigger required for impedance sense: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ImpSenseCap

0

R

0h

N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.7.2.

PortC (NID = 0Ch): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.7.3.

PortC (NID = 0Ch): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

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Field Name

Bits

R/W

Default

Reset

ConL2

23:16

R

1Ch

N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

7:0 13h

ConL1

ConL0

R

N/A (Hard-coded)

R

DAC0 Converter widget (0x13)

7.7.4.

PortC (NID = 0Ch): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.7.5.

PortC (NID = 0Ch): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Gain

1:0

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.7.6.

PortC (NID = 0Ch): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.7.7.

PortC (NID = 0Ch): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd3

9

R

0h

N/A (Hard-coded)

Reserved.

8

Error

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.7.8.

PortC (NID = 0Ch): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

RW 0h

5

Input enable: 1 = enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

4:3

R

0h

N/A (Hard-coded)

Reserved.

2:0

VRefEn

RW

0h

POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.7.9.

PortC (NID = 0Ch): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

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7.7.10. PortC (NID = 0Ch): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.7.11. PortC (NID = 0Ch): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

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7.7.12. PortC (NID = 0Ch): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

71Fh

71Eh

71Dh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

02h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

9h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

2h

0h

POR

Default assocation.

3:0

RW

Sequence.

7.8. PortD (NID = 0Dh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

00h

Reset

Rsvd2

31:24

R

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

Striping support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

FormatOvrd

4

R

0h

N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.8.1.

PortD (NID = 0Dh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

1h

Balanced I/O support: 1 = yes, 0 = no.

0h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

0h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.8.2.

PortD (NID = 0Dh): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

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7.8.2.

PortD (NID = 0Dh): ConLst

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.8.3.

PortD (NID = 0Dh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

23:16 1Ch

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

7:0 13h

DAC0 Converter widget (0x13)

ConL2

ConL1

ConL0

R

N/A (Hard-coded)

R

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7.8.4.

PortD (NID = 0Dh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.8.5.

PortD (NID = 0Dh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.8.6.

PortD (NID = 0Dh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

Rsvd1

RW

1h (YC/YD)

0h (UA/TA)

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

5:0

R

0h

Reserved.

7.8.7.

PortD (NID = 0Dh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.8.8.

PortD (NID = 0Dh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

71Fh

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

10h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

1h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

7h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

3h

0h

POR

Default assocation.

3:0

RW

Sequence.

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7.9. PortE (NID = 0Eh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

UnSolCap

7

R

1h

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

ProcWidget

Stripe

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.9.1.

PortE (NID = 0Eh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

R

0000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

0h

N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

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7.9.2.

PortE (NID = 0Eh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.9.3.

PortE (NID = 0Eh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

23:16 1Ch

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

ConL2

ConL1

R

N/A (Hard-coded)

R

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Field Name

Bits

R/W

Default

Reset

ConL0

7:0

R

13h

N/A (Hard-coded)

DAC0 Converter widget (0x13)

7.9.4.

PortE (NID = 0Eh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.9.5.

PortE (NID = 0Eh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.9.6.

PortE (NID = 0Eh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.9.7.

PortE (NID = 0Eh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

Act

R

3h

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.9.8.

PortE (NID = 0Eh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

0h

Reserved.

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7.9.9.

PortE (NID = 0Eh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.9.10. PortE (NID = 0Eh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

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7.9.11. PortE (NID = 0Eh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

7.9.12. PortE (NID = 0Eh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

8h

POR

0h (YB rev &

prior)

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

RW

4h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

7:4

RW

4h

5h (YB rev &

prior)

Default assocation.

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Field Name

Bits

R/W

Default

Reset

Sequence

3:0

RW

1h

POR

0h (YB rev &

prior)

Sequence.

7.10. PortF (NID = 0Fh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

R

0h

Left/right swap support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

PwrCntrl

10

R

1h

N/A (Hard-coded)

Power state support: 1 = yes, 0 = no.

0h

Dig

9

R

N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

1h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.10.1. PortF (NID = 0Fh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

VrefCntrl

R

1h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

15:8

R

00h

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

Trigger required for impedance sense: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ImpSenseCap

0

R

0h

N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

7.10.2. PortF (NID = 0Fh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.10.3. PortF (NID = 0Fh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

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Field Name

Bits

R/W

Default

Reset

ConL2

23:16

R

1Ch

N/A (Hard-coded)

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

7:0 13h

DAC0 Converter widget (0x13)

ConL1

ConL0

R

N/A (Hard-coded)

R

7.10.4. PortF (NID = 0Fh): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.10.5. PortF (NID = 0Fh): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Gain

1:0

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.10.6. PortF (NID = 0Fh): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.10.7. PortF (NID = 0Fh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd3

9

R

0h

N/A (Hard-coded)

Reserved.

8

Error

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.10.8. PortF (NID = 0Fh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

RW 0h

5

Input enable: 1 = enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

4:3

R

0h

N/A (Hard-coded)

Reserved.

2:0

VRefEn

RW

0h

POR - DAFG - ULR

Vref selection (See VrefCntrl field of PinCap parameter for supported selec-

tions):

000b= HI-Z

001b= 50%

010b= GND

011b= Reserved

100b= 80%

101b= 100%

110b= Reserved

111b= Reserved

7.10.9. PortF (NID = 0Fh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

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7.10.10. PortF (NID = 0Fh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.10.11. PortF (NID = 0Fh): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1

EAPD

Rsvd1

RW

1h

POR - DAFG - ULR

EAPD control: 1 = set EAPD pin to 1 (powered) up if this pin is powered up, 0

= set EAPD pin to 0.

0

R

0h

N/A (Hard-coded)

Reserved.

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7.10.12. PortF (NID = 0Fh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

71Fh

71Eh

71Dh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

01h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

8h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

1h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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PC AUDIO

Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

9h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

0h

POR

Default assocation.

3:0

RW

Sequence.

156

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7.11. MonoOut (NID = 10h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ProcWidget

6

R

0h

N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

0h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Stripe

5

R

N/A (Hard-coded)

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.11.1. MonoOut (NID = 10h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

0h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

0h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.11.2. MonoOut (NID = 10h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.11.3. MonoOut (NID = 10h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

1Ah

N/A (Hard-coded)

R

MonoMix Summing widget (0x1A)

7.11.4. MonoOut (NID = 10h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

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Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.11.5. MonoOut (NID = 10h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

000000h

N/A (Hard-coded)

Reserved.

6

OutEn

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

5:0

R

0h

N/A (Hard-coded)

Reserved.

7.11.6. MonoOut (NID = 10h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

1h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

00h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

Fh

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

0h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

0h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

Fh

0h

POR

Default assocation.

3:0

RW

Sequence.

7.12. DMic0 (NID = 11h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

00h

Reset

N/A (Hard-coded)

Rsvd2

31:24

R

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

UnsolCap

ProcWidget

Stripe

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

8

R

0h

Connection list present: 1 = yes, 0 = no.

1h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

4

R

Stream format override: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

AmpParOvrd

3

R

0h

N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

OutAmpPrsnt

InAmpPrsnt

Stereo

2

R

N/A (Hard-coded)

1

R

0

R

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.12.1. DMic0 (NID = 11h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

VRefCntrl

R

0h

EAPD support: 1 = yes, 0 = no.

15:8

R

00h

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

BalancedIO

6

R

0h

N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

0h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

InCap

5

R

N/A (Hard-coded)

OutCap

4

R

HPhnDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.12.2. DMic0 (NID = 11h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.12.3. DMic0 (NID = 11h): InAmpRight

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Set

350h

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7.12.3. DMic0 (NID = 11h): InAmpRight

Reg

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.12.4. DMic0 (NID = 11h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

7.12.5. DMic0 (NID = 11h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:6

R

0000000h

N/A (Hard-coded)

Reserved.

5

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Input enable: 1 = enabled, 0 = disabled.

Rsvd1

4:0

R

00h

Reserved.

7.12.6. DMic0 (NID = 11h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

Tag

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.12.7. DMic0 (NID = 11h): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.12.8. DMic0 (NID = 11h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

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Field Name

Bits

R/W

Default

Reset

Location

29:24

RW

10h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

Device

23:20

RW

Ah

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

ConnectionType

19:16

RW

3h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

Color

15:12

Color:

RW

0h

POR

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

4h

Eh

POR

Default assocation.

3:0

RW

Sequence.

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7.13. DMic1Vol (NID = 12h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

Fh

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

UnsolCap

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ProcWidget

6

R

0h

N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Stripe

5

R

N/A (Hard-coded)

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.13.1. DMic1Vol (NID = 12h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

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7.13.2. DMic1Vol (NID = 12h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

20h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

Dig1Pin Pin widget (0x20)

ConL2

ConL1

ConL0

R

7.13.3. DMic1Vol (NID = 12h): InAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.13.4. DMic1Vol (NID = 12h): InAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

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Field Name

Bits

R/W

Default

Reset

Rsvd1

31:2

R

00000000h

N/A (Hard-coded)

Reserved.

1:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.13.5. DMic1Vol (NID = 12h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

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7.14. DAC0 (NID = 13h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

8

R

0h

Connection list present: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ProcWidget

6

R

0h

N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Stripe

5

R

N/A (Hard-coded)

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.14.1. DAC0 (NID = 13h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

StrmType

R

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

FrmtSmplRate

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

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Field Name

Bits

R/W

Default

Reset

SmplRateMultp

13:11

RW

0h

POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.14.2. DAC0 (NID = 13h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Gain

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.14.3. DAC0 (NID = 13h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.14.4. DAC0 (NID = 13h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd4

31:11

R

000000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.14.5. DAC0 (NID = 13h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.14.6. DAC0 (NID = 13h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.15. DAC1 (NID = 14h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

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Field Name

Bits

R/W

Default

Reset

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

N/A (Hard-coded)

SwapCap

PwrCntrl

Dig

R

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

0h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

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7.15.1. DAC1 (NID = 14h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

StrmType

R

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

BitsPerSmpl

6:4

RW

3h

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.15.2. DAC1 (NID = 14h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.15.3. DAC1 (NID = 14h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Gain

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:0 RW 7Fh

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.15.4. DAC1 (NID = 14h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

3:2

R

0h

Reserved.

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Field Name

Bits

R/W

Default

Reset

Set

1:0

RW

3h

POR - DAFG - LR

Current power state setting for this widget.

7.15.5. DAC1 (NID = 14h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.15.6. DAC1 (NID = 14h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

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7.16. DAC2 (NID = 22h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

Fh

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 0h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

8

R

0h

Connection list present: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ProcWidget

6

R

0h

N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

0h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Stripe

5

R

N/A (Hard-coded)

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.16.1. DAC2 (NID = 22h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

StrmType

R

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 0h

FrmtSmplRate

R

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

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Field Name

Bits

R/W

Default

Reset

SmplRateMultp

13:11

R

0h

N/A (Hard-coded)

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

R

0h

N/A (Hard-coded)

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

R

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

R

0h

N/A (Hard-coded)

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.16.2. DAC2 (NID = 22h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Gain

R

0h

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

6:0 00h

R

N/A (Hard-coded)

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.16.3. DAC2 (NID = 22h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Gain

R

0h

Amp mute: 1 = muted, 0 = not muted.

6:0 00h

R

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.16.4. DAC2 (NID = 22h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd4

31:11

R

000000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

0h

N/A (Hard-coded)

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

N/A (Hard-coded)

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

0h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

R

0h

Current power state setting for this widget.

7.16.5. DAC2 (NID = 22h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

R

0h

N/A (Hard-coded)

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 0h N/A (Hard-coded)

R

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.16.6. DAC2 (NID = 22h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

R

0h

N/A (Hard-coded)

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.17. ADC0 (NID = 15h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

1h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

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Field Name

Bits

R/W

Default

Reset

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

N/A (Hard-coded)

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

1h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

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7.17.1. ADC0 (NID = 15h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.17.2. ADC0 (NID = 15h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

17h

N/A (Hard-coded)

R

ADC0Mux Selector widget (0x18)

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7.17.3. ADC0 (NID = 15h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

StrmType

R

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

BitsPerSmpl

6:4

RW

3h

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.17.4. ADC0 (NID = 15h): ProcState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

703h

Get

F0300h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPFOCDIS

RW

0h

POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Rsvd1

6:2

R

00h

N/A (Hard-coded)

Reserved.

1:0

ADCHPFByp

RW

1h

POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

7.17.5. ADC0 (NID = 15h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

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Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.17.6. ADC0 (NID = 15h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

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Field Name

Bits

R/W

Default

Reset

Ch

3:0

RW

0h

POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.18. ADC1 (NID = 16h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

1h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

Dh

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

R

Power state support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

Dig

9

R

0h

N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

1h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

N/A (Hard-coded)

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.18.1. ADC1 (NID = 16h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.18.2. ADC1 (NID = 16h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ADC1Mux widget (0x18)

ConL2

ConL1

ConL0

R

00h

18h

N/A (Hard-coded)

R

7.18.3. ADC1 (NID = 16h): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

StrmType

R

0h

N/A (Hard-coded)

POR - DAFG - ULR

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

13:11 RW 0h

Sample base rate multiple:

FrmtSmplRate

SmplRateMultp

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

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7.18.4. ADC1 (NID = 16h): ProcState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

703h

Get

F0300h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

HPFOCDIS

RW

0h

POR - DAFG - ULR

HPF offset calculation disable. 1 = calculation disabled; 0 = calculation en-

abled.

Rsvd1

6:2

R

00h

N/A (Hard-coded)

Reserved.

1:0

ADCHPFByp

RW

1h

POR - DAFG - ULR

Processing State: 00b= bypass the ADC HPF ("off"), 01b-11b= ADC HPF is en-

abled ("on" or "benign").

7.18.5. ADC1 (NID = 16h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

Rsvd3

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

9

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Error

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.18.6. ADC1 (NID = 16h): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

7.19. ADC0Mux (NID = 17h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

DigitalStrm

ConnList

UnsolCap

ProcWidget

Stripe

1h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

Striping support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

FormatOvrd

4

R

0h

N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.19.1. ADC0Mux (NID = 17h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

07h

N/A (Hard-coded)

Number of NID entries in connection list.

7.19.2. ADC0Mux (NID = 17h): ConLstEntry4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0204h

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Field Name

Bits

R/W

Default

Reset

ConL7

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Port A Pin widget (0x0A)

15:8

ConL6

ConL5

ConL4

R

0Ah

N/A (Hard-coded)

R

12h

DMic1Vol Selector widget (0x12)

7:0 11h

DMic0 Pin widget (0x11)

R

7.19.3. ADC0Mux (NID = 17h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

1Bh

N/A (Hard-coded)

Mixer Summing widget (0x1B)

ConL2

ConL1

ConL0

23:16

Port F Pin widget (0x0F)

15:8

Port E Pin widget (0x0E)

7:0

Port C Pin widget (0x0C)

R

0Fh

0Eh

0Ch

N/A (Hard-coded)

R

7.19.4. ADC0Mux (NID = 17h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

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Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

05h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

0Fh

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

Indicates which step is 0dB

7.19.5. ADC0Mux (NID = 17h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:4

R

0h

Reserved.

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Field Name

Bits

R/W

Default

Reset

Gain

3:0

RW

0h

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.19.6. ADC0Mux (NID = 17h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.19.7. ADC0Mux (NID = 17h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

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7.19.8. ADC0Mux (NID = 17h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.19.9. ADC0Mux (NID = 17h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.20. ADC1Mux (NID = 18h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

R

0h

Reserved.

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Field Name

Bits

R/W

Default

Reset

SwapCap

11

R

1h

N/A (Hard-coded)

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

PwrCntrl

R

N/A (Hard-coded)

DigitalStrm

ConnList

9

R

N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

N/A (Hard-coded)

UnsolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParamOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.20.1. ADC1Mux (NID = 18h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

07h

N/A (Hard-coded)

Number of NID entries in connection list.

7.20.2. ADC1Mux (NID = 18h): ConLstEntry4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0204h

Field Name

Bits

R/W

Default

Reset

ConL7

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Port A Pin widget (0x0A)

15:8

ConL6

ConL5

ConL4

R

0Ah

12h

N/A (Hard-coded)

R

DMic1Vol Selector widget (0x12)

7:0 11h

DMic0 Pin widget (0x11)

R

7.20.3. ADC1Mux (NID = 18h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

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Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

1Bh

N/A (Hard-coded)

Mixer Summing widget (0x1B)

ConL2

ConL1

ConL0

23:16

Port F Pin widget (0x0F)

15:8

Port E Pin widget (0x0E)

7:0

Port C Pin widget (0x0C)

R

0Fh

0Eh

0Ch

N/A (Hard-coded)

R

7.20.4. ADC1Mux (NID = 18h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

05h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

0Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Offset

6:0

R

00h

N/A (Hard-coded)

Indicates which step is 0dB

7.20.5. ADC1Mux (NID = 18h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:4

R

0h

Reserved.

3:0

RW

0h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.20.6. ADC1Mux (NID = 18h): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

6:4

R

0h

N/A (Hard-coded)

Reserved.

3:0

Gain

RW

0h

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.20.7. ADC1Mux (NID = 18h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.20.8. ADC1Mux (NID = 18h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

Rsvd3

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

9

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Error

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.20.9. ADC1Mux (NID = 18h): EAPDBTLLR

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ch

Get

F0C00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

SwapEn

Rsvd1

RW

0h

POR - DAFG - ULR

Swap enable: 1 = L/R swap enabled, 0 = L/R swap disabled.

1:0

R

0h

N/A (Hard-coded)

Reserved.

7.21. MonoMux (NID = 19h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

Striping support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

FormatOvrd

4

R

0h

N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.21.1. MonoMux (NID = 19h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

03h

N/A (Hard-coded)

Number of NID entries in connection list.

7.21.2. MonoMux (NID = 19h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

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Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

DAC2 Converter widget (0x22)

23:16 1Ch

MixerOutVol Selector widget (0x1C)

15:8 14h

DAC1 Converter widget (0x14)

7:0 13h

DAC0 Converter widget (0x13)

ConL2

ConL1

ConL0

R

N/A (Hard-coded)

R

7.21.3. MonoMux (NID = 19h): ConSelectCtrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

701h

Get

F0100h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:2

R

0000000h

N/A (Hard-coded)

Reserved.

1:0

Index

RW

0h

POR - DAFG - ULR

Connection select control index.

7.21.4. MonoMux (NID = 19h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

R

000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.22. MonoMix (NID = 1Ah): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

2h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

4

R

Stream format override: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

AmpParOvrd

3

R

0h

N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

0h

OutAmpPrsnt

InAmpPrsnt

Stereo

2

R

N/A (Hard-coded)

1

R

0

R

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.22.1. MonoMix (NID = 1Ah): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.22.2. MonoMix (NID = 1Ah): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

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Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

19h

N/A (Hard-coded)

R

MonoMux Selector widget (0x19)

7.22.3. MonoMix (NID = 1Ah): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

Reserved.

5:4

R

3h

POR - DAFG - LR

Actual power state of this widget.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

3:2

R

0h

N/A (Hard-coded)

Reserved.

1:0

Set

RW

0h

POR - DAFG - LR

Current power state setting for this widget.

7.23. Mixer (NID = 1Bh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

2h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Left/right swap support: 1 = yes, 0 = no.

10 1h

R

Power state support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

Dig

9

R

0h

N/A (Hard-coded)

Digital stream support: 1 = yes (digital), 0 = no (analog).

ConnList

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

1h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

N/A (Hard-coded)

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.23.1. Mixer (NID = 1Bh): InAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Dh

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Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

05h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

1Fh

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

17h

Indicates which step is 0dB

7.23.2. Mixer (NID = 1Bh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

06h

N/A (Hard-coded)

Number of NID entries in connection list.

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7.23.3. Mixer (NID = 1Bh): ConLstEntry4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0204h

Field Name

Bits

R/W

Default

Reset

ConL7

31:24

R

00h

0Ah

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

ConL6

ConL5

ConL4

R

Port A Pin widget (0x0A). Uses InAmpLeft5/InAmpRight5 controls.

7:0 14h N/A (Hard-coded)

DAC1 Converter widget (0x14). Uses InAmpLeft4/InAmpRight4 controls.

R

7.23.4. Mixer (NID = 1Bh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

13h

Reset

N/A (Hard-coded)

ConL3

31:24

R

DAC0 Converter widget (0x13). Uses InAmpLeft3/InAmpRight3 controls.

23:16 0Fh N/A (Hard-coded)

Port F Pin widget (0x0F). Uses InAmpLeft2/InAmpRight2 controls.

15:8 0Eh N/A (Hard-coded)

Port E Pin widget (0x0E). Uses InAmpLeft1/InAmpRight1 controls.

7:0 0Ch N/A (Hard-coded)

ConL2

ConL1

ConL0

R

Port C Pin widget (0x0C). Uses InAmpLeft0/InAmpRight0 controls.

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7.23.5. Mixer (NID = 1Bh): InAmpLeft0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

360h

Get

B2000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.6. Mixer (NID = 1Bh): InAmpRight0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

350h

Get

B0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.7. Mixer (NID = 1Bh): InAmpLeft1

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

361h

Get

B2001h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.8. Mixer (NID = 1Bh): InAmpRight1

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

351h

Get

B0001h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.9. Mixer (NID = 1Bh): InAmpLeft2

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

362h

Get

B2002h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.10. Mixer (NID = 1Bh): InAmpRight2

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

352h

Get

B0002h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.11. Mixer (NID = 1Bh): InAmpLeft3

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

363h

Get

B2003h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.12. Mixer (NID = 1Bh): InAmpRight3

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

353h

Get

B0003h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.13. Mixer (NID = 1Bh): InAmpLeft4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

364h

Get

B2004h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.14. Mixer (NID = 1Bh): InAmpRight4

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

354h

Get

B0004h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.15. Mixer (NID = 1Bh): InAmpLeft5

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

365h

Get

B2005h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

7.23.16. Mixer (NID = 1Bh): InAmpRight5

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

355h

Get

B0005h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

17h

Amp gain step number (see InAmpCap parameter pertaining to this widget).

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7.23.17. Mixer (NID = 1Bh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.24. MixerOutVol (NID = 1Ch): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

3h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

0h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

0h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

Striping support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

FormatOvrd

4

R

0h

N/A (Hard-coded)

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

3

R

N/A (Hard-coded)

2

R

1

R

0

R

7.24.1. MixerOutVol (NID = 1Ch): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.24.2. MixerOutVol (NID = 1Ch): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

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Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

1Bh

N/A (Hard-coded)

R

Mixer Summing widget (0x1B)

7.24.3. MixerOutVol (NID = 1Ch): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

05h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

1Fh

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Offset

6:0

R

1Fh

N/A (Hard-coded)

Indicates which step is 0dB

7.24.4. MixerOutVol (NID = 1Ch): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

1h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:5

R

0h

Reserved.

4:0

RW

1Fh

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.24.5. MixerOutVol (NID = 1Ch): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

1h

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

6:5

R

0h

N/A (Hard-coded)

Reserved.

4:0

Gain

RW

1Fh

POR - DAFG - ULR

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.24.6. MixerOutVol (NID = 1Ch): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

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7.25. SPDIFOut0 (NID = 1Dh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

4h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

8

R

0h

Connection list present: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

ProcWidget

6

R

0h

N/A (Hard-coded)

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

1h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

Stripe

5

R

N/A (Hard-coded)

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.25.1. SPDIFOut0 (NID = 1Dh): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:21

Reserved.

20

R

000h

N/A (Hard-coded)

B32

B24

R

0h

32 bit audio format support: 1 = yes, 0 = no.

19 1h

R

24 bit audio format support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

B20

18

R

1h

N/A (Hard-coded)

20 bit audio format support: 1 = yes, 0 = no.

17 1h

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B16

B8

R

N/A (Hard-coded)

R

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

44.1kHz rate support: 1 = yes, 0 = no.

0h

32kHz rate support: 1 = yes, 0 = no.

0h

22.05kHz rate support: 1 = yes, 0 = no.

0h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

R5

4

R

R4

3

R

R3

2

R

16kHz rate support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

R2

1

R

0h

N/A (Hard-coded)

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R1

0

R

N/A (Hard-coded)

7.25.2. SPDIFOut0 (NID = 1Dh): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

1h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

Float32

PCM

1

R

0

R

7.25.3. SPDIFOut0 (NID = 1Dh): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

R

00h

N/A (Hard-coded)

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

00h

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

Indicates which step is 0dB

7.25.4. SPDIFOut0 (NID = 1Dh): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

FrmtNonPCM

FrmtSmplRate

RW

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

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Field Name

Bits

R/W

Default

Reset

SmplRateMultp

13:11

RW

0h

POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.25.5. SPDIFOut0 (NID = 1Dh): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.25.6. SPDIFOut0 (NID = 1Dh): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.25.7. SPDIFOut0 (NID = 1Dh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

R

000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.25.8. SPDIFOut0 (NID = 1Dh): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.25.9. SPDIFOut0 (NID = 1Dh): DigCnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

73Fh

73Eh

70Eh

70Dh

Get

F0E00h / F0D00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

Reserved.

23

R

00h

N/A (Hard-coded)

KeepAlive

RW

0h

POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1

CC

22:15

R

00h

0h

N/A (Hard-coded)

Reserved.

14:8

RW

POR - DAFG - ULR

CC: Category Code.

RW

L: Generation Level.

RW

PRO: Professional.

RW

/AUDIO: Non-Audio.

RW

COPY: Copyright.

RW

PRE: Preemphasis.

RW

VCFG: Validity Config.

L

7

PRO

AUDIO

COPY

PRE

VCFG

V

6

0h

5

0h

4

0h

3

0h

2

0h

1

RW

0h

V: Validity.

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Field Name

Bits

R/W

Default

Reset

DigEn

0

RW

0h

POR - DAFG - ULR

Digital enable: 1 = converter enabled, 0 = converter disable.

7.26. SPDIFOut1 (NID = 1Eh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

0h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

4h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

SwapCap

PwrCntrl

Dig

15:12

Reserved.

11

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

R

9

R

Digital stream support: 1 = yes (digital), 0 = no (analog).

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

ConnList

8

R

0h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

0h

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

1h

Stream format override: 1 = yes, 0 = no.

1h

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.26.1. SPDIFOut1 (NID = 1Eh): PCMCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ah

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:21

R

000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

B32

20

R

0h

N/A (Hard-coded)

32 bit audio format support: 1 = yes, 0 = no.

19 1h

24 bit audio format support: 1 = yes, 0 = no.

18 1h

20 bit audio format support: 1 = yes, 0 = no.

17 1h

16 bit audio format support: 1 = yes, 0 = no.

16 0h

8 bit audio format support: 1 = yes, 0 = no.

B24

B20

B16

B8

R

N/A (Hard-coded)

R

Rsvd1

R12

R11

R10

R9

15:12

Reserved.

11

R

0h

R

0h

384kHz rate support: 1 = yes, 0 = no.

10 1h

192kHz rate support: 1 = yes, 0 = no.

0h

176.4kHz rate support: 1 = yes, 0 = no.

1h

96kHz rate support: 1 = yes, 0 = no.

1h

88.2kHz rate support: 1 = yes, 0 = no.

1h

48kHz rate support: 1 = yes, 0 = no.

1h

44.1kHz rate support: 1 = yes, 0 = no.

0h

R

9

R

8

R

R8

7

R

R7

6

R

R6

5

R

R5

4

R

32kHz rate support: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

R4

3

R

0h

N/A (Hard-coded)

22.05kHz rate support: 1 = yes, 0 = no.

0h

16kHz rate support: 1 = yes, 0 = no.

0h

11.025kHz rate support: 1 = yes, 0 = no.

0h

8kHz rate support: 1 = yes, 0 = no.

R3

R2

R1

2

R

N/A (Hard-coded)

1

R

0

R

7.26.2. SPDIFOut1 (NID = 1Eh): StreamCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Bh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:3

R

00000000h

N/A (Hard-coded)

Reserved.

2

AC3

R

1h

N/A (Hard-coded)

AC-3 formatted data support: 1 = yes, 0 = no.

0h

Float32 formatted data support: 1 = yes, 0 = no.

1h N/A (Hard-coded)

PCM-formatted data support: 1 = yes, 0 = no.

Float32

PCM

1

R

0

R

7.26.3. SPDIFOut1 (NID = 1Eh): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

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Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

Rsvd2

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

00h

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

00h

Indicates which step is 0dB

7.26.4. SPDIFOut1 (NID = 1Eh): Cnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

2h

Get

A0000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:16

Reserved.

15

R

0000h

N/A (Hard-coded)

POR - DAFG - ULR

FrmtNonPCM

FrmtSmplRate

RW

0h

Stream type: 1 = Non-PCM, 0 = PCM.

14 RW 0h

Sample base rate: 1 = 44.1kHz, 0 = 48kHz.

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Field Name

Bits

R/W

Default

Reset

SmplRateMultp

13:11

RW

0h

POR - DAFG - ULR

Sample base rate multiple:

000b= x1 (48kHz/44.1kHz or less)

001b= x2 (96kHz/88.2kHz/32kHz)

010b= x3 (144kHz)

011b= x4 (192kHz/176.4kHz)

100b-111b Reserved

SmplRateDiv

10:8

RW

0h

POR - DAFG - ULR

Sample base rate divider:

000b= Divide by 1 (48kHz/44.1kHz)

001b= Divide by 2 (24kHz/20.05kHz)

010b= Divide by 3 (16kHz/32kHz)

011b= Divide by 4 (11.025kHz)

100b= Divide by 5 (9.6kHz)

101b= Divide by 6 (8kHz)

110b= Divide by 7

111b= Divide by 8 (6kHz)

Rsvd1

7

R

0h

3h

N/A (Hard-coded)

Reserved.

6:4

BitsPerSmpl

RW

POR - DAFG - ULR

Bits per sample:

000b= 8 bits

001b= 16 bits

010b= 20 bits

011b= 24 bits

100b= 32 bits

101b-111b= Reserved

NmbrChan

3:0

RW

1h

POR - DAFG - ULR

Total number of channels in the stream assigned to this converter:

0000b-1111b= 1-16 channels.

7.26.5. SPDIFOut1 (NID = 1Eh): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.26.6. SPDIFOut1 (NID = 1Eh): OutAmpRight

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

390h

Get

B8000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Amp mute: 1 = muted, 0 = not muted.

Rsvd1

6:0

R

00h

Reserved.

7.26.7. SPDIFOut1 (NID = 1Eh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

R

000000h

N/A (Hard-coded)

Reserved.

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SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

Field Name

Bits

R/W

Default

Reset

SettingsReset

10

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

3h

Current power state setting for this widget.

7.26.8. SPDIFOut1 (NID = 1Eh): CnvtrID

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

706h

Get

F0600h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7:4

Strm

Ch

RW

0h

POR - S&DAFG - LR - PS

Stream ID: 0h = Converter "off", 1h-Fh = valid ID's.

3:0 RW 0h POR - S&DAFG - LR - PS

Channel assignment ("Ch" and "Ch+1" assigned as a pair, for a stereo convert-

er).

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7.26.9. SPDIFOut1 (NID = 1Eh): DigCnvtr

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

73Fh

73Eh

70Eh

70Dh

Get

F0E00h / F0D00h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

Reserved.

23

R

00h

N/A (Hard-coded)

KeepAlive

RW

0h

POR - DAFG - ULR

Keep Alive Enable: 1 = clocking information maintained during D3, 0 = clock

information not required during D3.

Rsvd1

CC

22:15

R

00h

0h

N/A (Hard-coded)

Reserved.

14:8

RW

POR - DAFG - ULR

CC: Category Code.

RW

L: Generation Level.

RW

PRO: Professional.

RW

/AUDIO: Non-Audio.

RW

COPY: Copyright.

RW

PRE: Preemphasis.

RW

VCFG: Validity Config.

L

7

PRO

AUDIO

COPY

PRE

VCFG

V

6

0h

5

0h

4

0h

3

0h

2

0h

1

RW

0h

V: Validity.

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

DigEn

0

RW

0h

POR - DAFG - ULR

Digital enable: 1 = converter enabled, 0 = converter disable.

7.27. Dig0Pin (NID = 1Fh): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:24

R

00h

N/A (Hard-coded)

Reserved.

23:20

Type

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

SwapCap

PwrCntrl

Dig

15:12

Reserved.

11

R

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

R

9

R

Digital stream support: 1 = yes (digital), 0 = no (analog).

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

ConnList

8

R

1h

N/A (Hard-coded)

Connection list present: 1 = yes, 0 = no.

1h

UnSolCap

ProcWidget

Stripe

7

R

N/A (Hard-coded)

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

Stream format override: 1 = yes, 0 = no.

0h

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

6

R

N/A (Hard-coded)

5

R

FormatOvrd

AmpParOvrd

OutAmpPrsnt

InAmpPrsnt

Stereo

4

R

3

R

2

R

1

R

0

R

7.27.1. Dig0Pin (NID = 1Fh): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

N/A (Hard-coded)

Rsvd2

31:17

R

0000h

Reserved.

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Field Name

Bits

R/W

Default

Reset

EapdCap

16

R

0h

N/A (Hard-coded)

EAPD support: 1 = yes, 0 = no.

VrefCntrl

15:8

R

00h

N/A (Hard-coded)

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

6

BalancedIO

InCap

R

0h

Balanced I/O support: 1 = yes, 0 = no.

0h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

5

R

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.27.2. Dig0Pin (NID = 1Fh): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

7.27.3. Dig0Pin (NID = 1Fh): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

00h

1Dh

N/A (Hard-coded)

R

SPDIFOut0 Converter widget (0x1D)

7.27.4. Dig0Pin (NID = 1Fh): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

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Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.27.5. Dig0Pin (NID = 1Fh): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

Reserved.

6

OutEn

RW

0h

POR - DAFG - ULR

Output enable: 1 = enabled, 0 = disabled.

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Field Name

Bits

R/W

Default

Reset

Rsvd1

5:0

R

00h

N/A (Hard-coded)

Reserved.

7.27.6. Dig0Pin (NID = 1Fh): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.27.7. Dig0Pin (NID = 1Fh): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

IDT™ CONFIDENTIAL

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Field Name

Bits

R/W

Default

Reset

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

7.27.8. Dig0Pin (NID = 1Fh): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

71Dh

Byte 1 (Bits 7:0)

71Fh

71Eh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

0h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

1h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

4h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

5h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

1h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

6h

0h

POR

Default assocation.

3:0

RW

Sequence.

7.28. Dig1Pin (NID = 20h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

00h

Reset

N/A (Hard-coded)

Rsvd2

31:24

R

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

4h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Delay

19:16

R

0h

N/A (Hard-coded)

Number of sample delays through widget.

Rsvd1

15:12

Reserved.

11

R

0h

SwapCap

PwrCntrl

Dig

0h

Left/right swap support: 1 = yes, 0 = no.

10 1h

Power state support: 1 = yes, 0 = no.

1h

Digital stream support: 1 = yes (digital), 0 = no (analog).

R

9

R

ConnList

UnSolCap

ProcWidget

Stripe

8

R

1h

Connection list present: 1 = yes, 0 = no.

1h

Unsolicited response support: 1 = yes, 0 = no.

0h

Processing state support: 1 = yes, 0 = no.

0h

Striping support: 1 = yes, 0 = no.

0h

N/A (Hard-coded)

7

R

N/A (Hard-coded)

6

R

N/A (Hard-coded)

5

R

FormatOvrd

4

R

Stream format override: 1 = yes, 0 = no.

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Field Name

Bits

R/W

Default

Reset

AmpParOvrd

3

R

0h

N/A (Hard-coded)

Amplifier capabilities override: 1 = yes, no.

0h

Output amp present: 1 = yes, 0 = no.

0h

Input amp present: 1 = yes, 0 = no.

1h

OutAmpPrsnt

InAmpPrsnt

Stereo

2

R

N/A (Hard-coded)

1

R

0

R

Stereo stream support: 1 = yes (stereo), 0 = no (mono).

7.28.1. Dig1Pin (NID = 20h): PinCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Ch

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:17

Reserved.

16

R

0000h

N/A (Hard-coded)

EapdCap

VrefCntrl

R

0h

EAPD support: 1 = yes, 0 = no.

15:8

R

00h

Vref support:

bit 7 = Reserved

bit 6 = Reserved

bit 5 = 100% support (1 = yes, 0 = no)

bit 4 = 80% support (1 = yes, 0 = no)

bit 3 = Reserved

bit 2 = GND support (1 = yes, 0 = no)

bit 1 = 50% support (1 = yes, 0 = no)

bit 0 = Hi-Z support (1 = yes, 0 = no)

Rsvd1

7

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

BalancedIO

6

R

0h

N/A (Hard-coded)

Balanced I/O support: 1 = yes, 0 = no.

1h

Input support: 1 = yes, 0 = no.

1h

Output support: 1 = yes, 0 = no.

0h

Headphone amp present: 1 = yes, 0 = no.

1h

Presence detection support: 1 = yes, 0 = no.

0h

Trigger required for impedance sense: 1 = yes, 0 = no.

0h N/A (Hard-coded)

Impedance sense support: 1 = yes, 0 = no.

InCap

5

R

N/A (Hard-coded)

OutCap

4

R

HdphDrvCap

PresDtctCap

TrigRqd

3

R

2

R

1

R

ImpSenseCap

0

R

7.28.2. Dig1Pin (NID = 20h): ConLst

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F000Eh

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

LForm

ConL

R

0h

N/A (Hard-coded)

Connection list format: 1 = long-form (15-bit) NID entries, 0 = short-form (7-bit)

NID entries.

6:0

R

01h

N/A (Hard-coded)

Number of NID entries in connection list.

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7.28.3. Dig1Pin (NID = 20h): ConLstEntry0

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0200h

Field Name

Bits

R/W

Default

Reset

ConL3

31:24

R

00h

1Eh

N/A (Hard-coded)

Unused list entry.

23:16

Unused list entry.

15:8

Unused list entry.

7:0

ConL2

ConL1

ConL0

R

SPDIFOut1 Converter widget (0x1E)

7.28.4. Dig1Pin (NID = 20h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

Rsvd3

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

9

R

0h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Error

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.28.5. Dig1Pin (NID = 20h): PinWCntrl

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

707h

Get

F0700h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:7

R

0000000h

N/A (Hard-coded)

Reserved.

6

OutEn

InEn

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

Output enable: 1 = enabled, 0 = disabled.

RW 0h

Input enable: 1 = enabled, 0 = disabled.

5

Rsvd1

4:0

R

00h

Reserved.

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7.28.6. Dig1Pin (NID = 20h): UnsolResp

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

708h

Get

F0800h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

En

RW

0h

POR - DAFG - ULR

Unsolicited response enable (also enables Wake events for this Widget): 1 =

enabled, 0 = disabled.

Rsvd1

Tag

6

R

0h

N/A (Hard-coded)

Reserved.

5:0

RW

00h

POR - DAFG - ULR

Software programmable field returned in top six bits (31:26) of every Unsolicit-

ed Response generated by this node.

7.28.7. Dig1Pin (NID = 20h): ChSense

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

709h

Get

F0900h

Field Name

Bits

R/W

Default

0h

Reset

PresDtct

31

R

POR

Presence detection indicator: 1 = presence detected; 0 = presence not detect-

ed.

Rsvd

30:0

R

00000000h

N/A (Hard-coded)

Reserved.

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7.28.8. Dig1Pin (NID = 20h): ConfigDefault

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

71Fh

71Eh

71Dh

71Ch

Get

F1F00h / F1E00h / F1D00h / F1C00h

Field Name

Bits

R/W

Default

Reset

PortConnectivity

31:30

RW

2h

POR

Port connectivity:

0h = Port complex is connected to a jack

1h = No physical connection for port

2h = Fixed function device is attached

3h = Both jack and internal device attached (info in all other fields refers to in-

tegrated device, any presence detection refers to jack)

Location

29:24

RW

18h

POR

Location

Bits [5..4]:

0h = External on primary chassis

1h = Internal

2h = Separate chassis

3h = Other

Bits [3..0]:

0h = N/A

1h = Rear

2h = Front

3h = Left

4h = Right

5h = Top

6h = Bottom

7h-9h = Special

Ah-Fh = Reserved

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Field Name

Bits

R/W

Default

Reset

Device

23:20

RW

5h

POR

Default device:

0h = Line out

1h = Speaker

2h = HP out

3h = CD

4h = SPDIF Out

5h = Digital other out

6h = Modem line side

7h = Modem handset side

8h = Line in

9h = Aux

Ah = Mic in

Bh = Telephony

Ch = SPDIF In

Dh = Digital other in

Eh = Reserved

Fh = Other

ConnectionType

19:16

RW

6h

POR

Connection type:

0h = Unknown

1h = 1/8" stereo/mono

2h = 1/4" stereo/mono

3h = ATAPI internal

4h = RCA

5h = Optical

6h = Other digital

7h = Other analog

8h = Multichannel analog (DIN)

9h = XLR/Professional

Ah = RJ-11 (modem)

Bh = Combination

Ch-Eh = Reserved

Fh = Other

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Field Name

Bits

R/W

Default

Reset

Color

15:12

RW

0h

POR

Color:

0h = Unknown

1h = Black

2h = Grey

3h = Blue

4h = Green

5h = Red

6h = Orange

7h = Yellow

8h = Purple

9h = Pink

Ah-Dh = Reserved

Eh = White

Fh = Other

Misc

11:8

RW

1h

POR

Miscellaneous:

Bits [3..1] = Reserved

Bit 0 = Jack detect override

Association

Sequence

7:4

RW

7h

0h

POR

Default assocation.

3:0

RW

Sequence.

7.29. DigBeep (NID = 21h): WCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0009h

Field Name

Bits

R/W

Default

00h

Reset

N/A (Hard-coded)

Rsvd3

31:24

R

Reserved.

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Field Name

Bits

R/W

Default

Reset

Type

23:20

R

7h

N/A (Hard-coded)

Widget type:

0h = Out Converter

1h = In Converter

2h = Summing (Mixer)

3h = Selector (Mux)

4h = Pin Complex

5h = Power

6h = Volume Knob

7h = Beep Generator

8h-Eh = Reserved

Fh = Vendor Defined

Rsvd2

19:4

R

0h

1h

N/A (Hard-coded)

Reserved.

3

AmpParOvrd

OutAmpPrsnt

Rsvd1

R

Amplifier capabilities override: 1 = yes, no.

1h

Output amp present: 1 = yes, 0 = no.

2

R

1:0

R

0h

Reserved.

7.29.1. DigBeep (NID = 21h): OutAmpCap

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

Get

F0012h

Field Name

Bits

R/W

Default

Reset

Mute

31

R

1h

N/A (Hard-coded)

Mute support: 1 = yes, 0 = no.

Rsvd3

30:23

R

00h

N/A (Hard-coded)

Reserved.

22:16

StepSize

R

17h

Size of each step in the gain range: 0 to 127 = .25dB to 32dB, in .25dB steps.

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Field Name

Bits

R/W

Default

Reset

Rsvd2

15

R

0h

N/A (Hard-coded)

Reserved.

14:8

NumSteps

Rsvd1

R

03h

N/A (Hard-coded)

Number of gains steps (number of possible settings - 1).

7

R

0h

N/A (Hard-coded)

Reserved.

6:0

Offset

R

03h

Indicates which step is 0dB

7.29.2. DigBeep (NID = 21h): OutAmpLeft

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

3A0h

Get

BA000h

Field Name

Bits

R/W

Default

Reset

Rsvd2

31:8

R

000000h

N/A (Hard-coded)

Reserved.

7

Mute

Rsvd1

Gain

RW

0h

POR - DAFG - ULR

N/A (Hard-coded)

POR - DAFG - ULR

Amp mute: 1 = muted, 0 = not muted.

6:2

R

00h

Reserved.

1:0

RW

1h

Amp gain step number (see OutAmpCap parameter pertaining to this widget).

7.29.3. DigBeep (NID = 21h): PwrState

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

705h

Get

F0500h

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Field Name

Bits

R/W

Default

Reset

Rsvd4

31:11

Reserved.

10

R

000000h

N/A (Hard-coded)

SettingsReset

R

1h

POR - DAFG - ULR

Indicates if any persistent settings in this Widget have been reset. Cleared by

PwrState 'Get', or a 'Set' to any Verb in this Widget.

Rsvd3

Error

9

R

0h

N/A (Hard-coded)

Reserved.

8

R

0h

POR - DAFG - ULR

Error indicator: 1 = cannot enter requested power state, 0 = no problem with

requested power state.

Rsvd2

Act

7:6

R

0h

N/A (Hard-coded)

POR - DAFG - LR

N/A (Hard-coded)

POR - DAFG - LR

Reserved.

5:4

R

3h

Actual power state of this widget.

Rsvd1

Set

3:2

R

0h

Reserved.

1:0

RW

0h

Current power state setting for this widget.

7.29.4. DigBeep (NID = 21h): Gen

Reg

Set

Byte 4 (Bits 31:24)

Byte 3 (Bits 23:16)

Byte 2 (Bits 15:8)

Byte 1 (Bits 7:0)

70Ah

Get

F0A00h

Field Name

Bits

R/W

Default

Reset

Rsvd

31:8

R

000000h

N/A (Hard-coded)

Reserved.

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Field Name

Bits

R/W

Default

Reset

Divider

7:0

RW

00h

POR - DAFG - LR

Enable internal PC-Beep generation. Divider == 00h disables internal PC Beep

generation and enables normal operation of the codec. Divider != 00h gener-

ates the beep tone on all Pin Complexes that are currently configured as out-

puts. The HD Audio spec states that the beep tone frequency = (48kHz HD

Audio SYNC rate) / (4*Divider), producing tones from 47 Hz to 12 kHz (logarith-

mic scale).

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8. PINOUTS

8.1. Pin Assignment

DVDD_CORE

DMIC_CLK/GPIO 1

DVDD_IO

1

36

35

34

33

32

31

30

29

28

27

26

25

Cap+

2

Cap-

3

V-

DMIC_0/GPIO 2

SDATA_OUT

BITCLK

4

AVSS2

HP1_R

HP1_L

AVSS2

HP0_R

HP0_L

AVDD1

AVSS1

Mono_Out

5

6

48

QFN

DVSS

7

SDATA_IN

DVDD

8

9

SYNC

10

11

12

RESET#

PCBEEP

Port

SENSE-ASENSE-B

HP0

HP1

Y

-

x

Y

x

-

Y

x

Y

PORTC

PORTD

PORTE

PORTF

DMIC0

SPDIF0

SPDIF1

Figure 14. Pin Assignment

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8.2. Pin Table for 48-pin QFN

Internal

Pull-up/Pull-down

48 pin

location

Pin Name

Pin Function

I/O

DVDD_CORE

1.5V Digital Core Regulator Filter Cap

O(Digital)

None

1

2

3

4

Pull-Up 50k with GPIO

or Pull-down 50k with

Digital Mic

DMIC_CLK/GPIO1

DVDD_IO

Digital Mic Clock Output/GPIO1

Reference Voltage (1.5V or 3.3V)

Digital Mic 01 Input/GPIO2

I/O(Digital)

I(Digital)

None

Pull-Up 50k with GPIO

or Pull-down 50k with

Digital Mic

DMIC0/GPIO2

I/O(Digital)

SDATA_OUT

BITCLK

HD Audio Serial Data output from controller

HD Audio Bit Clock

I/O(Digital)

I(Digital)

None

5

6

DVSS

Digital Ground

I(Digital)

7

SDATA_IN

DVDD

HD Audio Serial Data Input to controller

Digital Vdd= 3.3V

O(Digital)

I(Digital)

8

9

SYNC

HD Audio Frame Sync

HD Audio Reset

I(Digital)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

RESET#

I(Digital)

PCBEEP

PC Beep

I(Analog)

SENSE_A

SENSE_B

PORTE_L

PORTE_R

PORTF_L

PORTF_R

PORTC_L

PORTC_R

VREFFILT

CAP2

Jack insertion detection Ports A,B,C,SPDIF0

Jack insertion detection Ports E,F, Mono, SPDIF1

Port E Left

I(Analog)

I/O(Analog)

O(Analog)

I(Analog)

Port E Right

Port F Left

Port F Right

Port C Left

Port C Right

Analog Virtual Ground

Reference filter Cap

Reference Voltage out drive (intended for mic bias)

Mono output

VREFOUT-A

VREFOUT-C

Mono_Out

AVSS1

Analog Ground

AVDD1

Analog Vdd

I(Analog)

PORTA_L (HP0)

PORTA_R (HP0)

AVSS

Port A Output Left

I/O(Analog)

I(Analog)

Port A Output Right

Analog Ground

PORTB_L (HP1)

PORTB_R (HP1)

AVSS

Port B Output Left

I/O(Analog)

I(Analog)

Port B Output Right

Analog Ground

Table 26. Pin Table

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Internal

Pull-up/Pull-down

48 pin

location

Pin Name

Pin Function

Negative analog supply

I/O

V-

O(Analog)

I(Analog)

O(Analog)

I(Analog)

O(Analog)

I(Analog)

None

34

35

36

37

38

39

40

41

42

43

44

45

CAP-

CAP+

VREG

Chargepump cap -

None

Chargepump cap +

Linear Regulator Output (2.5V) filter cap

Analog Supply for VREG

Analog Supply for Class-D amp

BTL amp Left +

AVDD2

PVDD

PORTD_+L

PORTD_-L

PVSS

BTL amp Left -

Analog Ground

PORTD_R-

PORTD_R+

PVDD

BTL amp Right -

BTL amp Right +

Analog Supply for Class-D amp

Pull-up 60K with GPIO

Pull-down 60K with DMIC

or SPDIFOUT

DMIC1/GPIO/

SPDIFOUT1

Digital Microphone input, SPDIF Output, or GPIO0

EAPD

I/O(Digital)

46

I/O (Open

Drain Digital)

EAPD

Pull-up 60K

47

48

SPDIFOUT0

SPDIF0

O(Digital)

60K internal pull-down

Table 26. Pin Table

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9. PACKAGE OUTLINE AND PACKAGE DIMENSIONS

Package dimensions are kept current with JEDEC Publication No. 95Solder Reflow Profile

9.1. 48-Pad QFN Package

QFN Dimensions in mm

Key

Min

0.80

0.00

Nom

0.90

Max

1.0

A

A1

A3

D

0.02

0.05

0.20 REF

7.00 BSC

5.50 BSC

7.00 BSC

5.50 BSC

0.40

D1

E

E1

L

0.35

0.45

e

0.50 BSC

0.20-0.25

0.25

R

b

0.18

5.50

0.30

5.80

D2

E2

ZD

ZE

5.65

0.75 BSC

Additional

Approved

Option

Figure 15. 48QFN Package Diagram

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9.2. Standard Reflow Profile Data

Note: These devices can be hand soldered at 360 ^oC for 3 to 5 seconds.

FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid

State Surface Mount Devices” (www.jedec.org/download).

Profile Feature

Pb Free Assembly

Average Ramp-Up Rate (Ts_max- Tp)

3 ^oC / second max

Temperature Min (Ts_min

Temperature Max (Ts_max

Time (ts_min- ts_max

)

150 ^oC

Preheat:

200 ^oC

60 - 180 seconds

Temperature (T_L)

Time (t_L)

217 ^oC

60 - 150 seconds

Time maintained above:

Peak / Classification Temperature (Tp)

Time within 5 ^oC of actual Peak Temperature (tp)

Ramp-Down rate

See “Package Classification Reflow Temperatures”

20 - 40 seconds

6 ^oC / second max

Time 25 ^oC to Peak Temperature

8 minutes max

Note: All temperatures refer to topside of the package, measured on the package body surface.

Table 27. Standard Reflow Profile

Figure 16. Solder Reflow Profile

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10.DISCLAIMER

While the information presented herein has been checked for both accuracy and reliability, manufac-

turer assumes no responsibility for either its use or for the infringement of any patents or other rights

of third parties, which would result from its use. No other circuits, patents, or licenses are implied.

This product is intended for use in normal commercial applications. Any other applications, such as

those requiring extended temperature range, high reliability, or other extraordinary environmental

requirements, are not recommended without additional processing by manufacturer. Manufacturer

reserves the right to change any circuitry or specifications without notice. Manufacturer does not

authorize or warrant any product for use in life support devices or critical medical instruments.

IDT™ CONFIDENTIAL

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PC AUDIO

11. DOCUMENT REVISION HISTORY

Revision

0.5

Date

Description of Change

January 25, 2008 Initial release

0.9

May 9, 2008

Added widget details.Integrated addendum sections into datasheet.

Removed low voltage part number, as not needed as the DVD_IO pin dynamically selects low

voltage (1.5V) or normal (3.3V) HDA bus signaling based on what voltage is on the pin

0.91

May 27, 2008

YA revision and beyond updates

• BTL amp gain settings added to Section 2.18, “BTL Amplifier”

• Corrected tables in Section 2.17, “EAPD”

• Widget Changes in AFG (NID = 01h)

• AFGEAPD changed to have separate control bits for BTL, HP-A and HP-B

• AFGAnaPort Verb changed to remove the GSMark control, and to provide Ports A and B

with one power down control each, as opposed to each having a HP power down and a lin-

eout power down

0.92

August 6, 2008

• AFGAnaBeep Verb changed to add more flexible modes of operation

• AFGAnaBTL Verb changed to add MaxVol field and remove +6db control. Other fields

shifted a bit to maintain logical grouping

AFGAnaCapless Verb changed for new charge pump clock controls, as well as new test bits

required by the analog

Corrected Mic Boost Voltages in Section 3.2

Updated to include Aux mode Section 2.22, “Aux Audio Support (92HD81B1X only)”, widget controls

added at Chapter 7.4.32, “AFG (NID = 01h): AuxAudio”

corrected part number mappings Section 1.2, “Orderable Part Numbers”

corrected device ID mappings Section 7.3.1, “Root (NID = 00h): RevID”

0.93

October 2, 2008

October 27, 2008

Updated 3 widget default values for YB revision

Chapter 7.4.28, “AFG (NID = 01h): AnaBTL YC and YD Revisions” TS Wait BITs 11:8, default 6h to

0h

Chapter 7.4.30, “AFG (NID = 01h): AnaCapless” ChargePumpFreqBypass BIT 12 default 1h to 0h

Chapter 7.4.30, “AFG (NID = 01h): AnaCapless” ChargePumpSplyDetOverride BIT 13 default 1h to

0h

0.94

0.95

0.96

December 10, 2008 Corrected conflicting pin naming on pins 43 and 44.

Updated for the YC revision

Chapter 7.4.6, “AFG (NID = 01h): PwrStateCap” The LPD3Sup bit was renamed and default was

changed

Chapter 7.4.30, “AFG (NID = 01h): AnaCapless” ChargePumpFreqBypass BIT 12 default changed

Chapter 7.9.12, “PortE (NID = 0Eh): ConfigDefault” and Chapter 6.3, “Pin Configuration Default

Register Settings” Configuration default change

January 9, 2009

Updated for the WA revision

0.97

0.98

January 12,2009

March 5, 2009

Chapter 7.4.30, “AFG (NID = 01h): AnaCapless” ChargePumpFreqBypass BIT 12 default changed,

changed m3dB field name to “Reserved” and changed p6dB field name to “AntiPopBypass.”

Removed WA items.

Please note YD revision has no changes in documentation from YC. All YC notes apply to YD.

Removed 3.3V Analog option. Contact IDT for more information.

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Revision

Date

Description of Change

Added UA widget changes

All vendor defined widgets are now reset on POR except VSPwrState

Chapter 7.4.23, “AFG (NID = 01h): EAPD” AFGEAPDxxxSDMode defaults were changed to 1

Chapter 7.4.24, “AFG (NID = 01h): PortUse” AFGPortUse defaults were changed to 1

Chapter 7.4.29, “AFG (NID = 01h): AnaBTL UA Revision” AFGAnaBTL Verb updated and

rearranged

Chapter 7.4.30, “AFG (NID = 01h): AnaCapless” AFGAnaCaplessVRegSel definition changed, and

default changed from 4h to 2h

0.985

April 2009

Chapter 7.8.6, “PortD (NID = 0Dh): PinWCntrl” PortDPinWCntrlOutEn bit default changed to 0

Chapter 7.4.26, “AFG (NID = 01h): AnaPort” RTZCon[2:0] field removed from the AFGAnaDAC

Verb. HPILimit[1:0] field removed from the AFGAnaSply Verb. p6dB and m3dB bits removed from

the AFGAnaCapless Verb, AntiPopBypass bit added to bit 0 of that Verb.

0.986

0.987

September 2009

November 2009

Indicated that all UA widget comments also apply to the TA revision.

TA revision, Port C for Input use only. If Output on Port C is needed, please use the YD or UA

revisions. Notations made at PortC references.

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6024 Silver Creek Valley Road

San Jose, California 95138

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications de-

scribed herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and perfor-

mance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained

herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s

products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This

document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be

reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own

risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, in-

cluding protected names, logos and designs, are the property of IDT or their respective third party owners.


型号：	92HD81B1C5NLGXUAX
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PCM Codec, 1-Func, ROHS COMPLIANT, QFN-48 PC
文件：	总289页 (文件大小：3502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

92HD81B1C5NLGXUAX [IDT]

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