952607FT [IDT]
Clock Generator, PDSO48;
| 型号： | 952607FT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO48 光电二极管 |
| 文件： | 总22页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
ICS952607
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
Features/Benefits:
•
•
•
•
•
•
•
•
QuadRomTM frequency selection.
Programmable output frequency.
•
•
•
•
•
•
•
•
2 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
9 - PCI, 3 free running, 33MHz
3 - REF, 14.318MHz
3 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
2 - 48MHz
Programmable asynchronous 3V66&PCI frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system
malfunctions.
•
•
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
1 - 24/48MHz
Key Specifications:
•
•
•
•
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
•
•
•
Uses external 14.318MHz reference input.
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
+/- 300ppm frequency accuracy on CPU & SRC clocks
•
Supports CPU clks up to 400MHz
Functionality
Pin Configuration
*FS1/REF0
*FS0/REF1
REF2
1
2
3
4
5
6
7
8
9
48 VDDA
47 GND
46 IREF
45 Reset#
44 GND
43 CPUCLKT1
42 CPUCLKC1
41
VDDCPU
40 CPUCLKT0
39 CPUCLKC0
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
CPU
MHz
AGP
MHz
PCI
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2 10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11
12
13
14
15
16
17
18
19
20
38
VDDPCI
GND
GND
37 SRCCLKT
36 SRCCLKC
^^PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
35
VDD
34 VttPWR_GD/PD#
33 SDATA
32 SCLK
31
30
29
3V66_0
3V66_1
GND
PCICLK4
PCICLK5
**Sel24_48#/24_48MHz 21
28 VDD3V66
22
23
24
27
**FS3/48MHz_0
3V66_2
26 3V66_3/VCH
48MHz_1
25
GND
VDD48
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
48-pin SSOP
1
1
1
1
1
1
1
1
0
1
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
0734A—A07/26/05
Integrated
Circuit
ICS952607
Systems, Inc.
Pin Description
PIN # PIN NAME
PIN TYPE DESCRIPTION
1
2
3
4
5
6
7
8
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
I/O
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
14.318 MHz reference clock.
OUT
PWR
IN
OUT
PWR
I/O
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
^^PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
9
I/O
10
11
12
13
14
15
16
17
18
19
20
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCICLK4
PCICLK5
PCI clock output.
21
**Sel24_48#/24_48MHz
I/O
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 = 48MHz.
22
23
24
25
26
27
28
29
30
31
32
33
**FS3/48MHz_0
48MHz_1
GND
VDD48
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
48MHz clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
SDATA
I/O
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active high input. / Asynchronous active low
input pin used to power down the device into a low power state.
34
VttPWR_GD/PD#
IN
35
36
VDD
PWR
OUT
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
SRCCLKC
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
37
38
39
SRCCLKT
GND
OUT
PWR
OUT
CPUCLKC0
40
41
42
CPUCLKT0
VDDCPU
OUT
PWR
OUT
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
CPUCLKC1
43
44
45
CPUCLKT1
GND
OUT
PWR
OUT
Ground pin.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
Reset#
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Ground pin.
46
IREF
OUT
47
48
GND
VDDA
PWR
PWR
3.3V power for the PLL core.
0734A—07/26/05
2
Integrated
Circuit
ICS952607
Systems, Inc.
General Description
ICS952607 is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets. ICS952607 is driven with a 14.318MHz crystal. It
generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA suuport.
The ICS952607 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. This part also
provides 128 frequency selections via ICS QuadROMTM technology as an alternate to M/N programming.
Block Diagram
Frequency
Dividers
48MHz (1:0)
24_48MHz
PLL2
X1
X2
XTAL
REF (2:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
SRCCLKT
SCLK
SDATA
Programmable
Spread
Programmable
Frequency
Dividers
STOP
Logic
SRCCLKC
PLL1
VTTPWRGD#
PD#
Control
Logic
3V66 (3:0)
PCICLK (5:0)
PCICLK_F (2:0)
FS (4:0)
RESET#
I REF
Sel24_48#
Power Groups
Pin Number
Description
VDD
GND
4
28
7
29
Xtal, Ref
3V66
11,17
35
41
12,18
38
44
PCICLK outputs
SRCCLK outputs
CPU outputs
48
25
47
24
MCLK, CPU Analog, CPU digital
48MHz Fix, Fix Digital, Fix analog
0734A—07/26/05
3
Integrated
Circuit
ICS952607
Systems, Inc.
Table1: QuadRom Frequency Selection Table
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
AGP
PCI
Spread
%
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0
MHz
MHz
MHz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0.35% Center
0.35% Center
0.35% Center
0.35% Center
No Spread
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No Spread
No Spread
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
No Spread
0
0
0
0
1
1
1
1
0
0
1
1
0
1
No Spread
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
No Spread
No Spread
No Spread
No Spread
Table continued on next page.
0734A—07/26/05
4
Integrated
Circuit
ICS952607
Systems, Inc.
Table1: QuadRom Frequency Selection Table (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0
MHz
MHz
MHz
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.66
35.66
35.66
35.66
35.66
35.66
35.66
35.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
%
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
103.00
206.00
137.33
171.67
228.89
412.00
274.67
343.33
105.00
210.00
140.00
175.00
233.33
420.00
280.00
350.00
107.00
214.00
142.66
178.34
237.78
428.00
285.34
356.66
110.00
220.00
146.66
183.34
244.44
440.00
293.34
366.66
68.66
68.66
68.66
68.66
68.66
68.66
68.66
68.66
69.99
69.99
69.99
69.99
69.99
69.99
69.99
69.99
71.33
71.33
71.33
71.33
71.33
71.33
71.33
71.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table continued on next page.
0734A—07/26/05
5
Integrated
Circuit
ICS952607
Systems, Inc.
Table1: QuadRom Frequency Selection Table 3 (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0
MHz
95.00
MHz
MHz
31.66
31.66
31.66
31.66
31.66
31.66
31.66
31.66
30.00
30.00
30.00
30.00
30.00
30.00
30.00
30.00
28.33
28.33
28.33
28.33
28.33
28.33
28.33
28.33
26.66
26.66
26.66
26.66
26.66
26.66
26.66
26.66
%
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
63.33
63.33
63.33
63.33
63.33
63.33
63.33
63.33
59.99
59.99
59.99
59.99
59.99
59.99
59.99
59.99
56.66
56.66
56.66
56.66
56.66
56.66
56.66
56.66
53.33
53.33
53.33
53.33
53.33
53.33
53.33
53.33
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
190.00
126.66
158.34
211.11
380.00
253.34
316.66
90.00
180.00
120.00
150.00
200.00
360.00
240.00
300.00
85.00
170.00
113.33
141.67
188.89
340.00
226.67
283.33
80.00
160.00
106.66
133.34
177.78
320.00
213.34
266.66
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table continued on next page.
0734A—07/26/05
6
Integrated
Circuit
ICS952607
Systems, Inc.
Table1: QuadRom Frequency Selection Table 4 (Continued)
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
AGP
PCI
Spread
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0
MHz
MHz
MHz
38.33
38.33
38.33
38.33
38.33
38.33
38.33
38.33
40.00
40.00
40.00
40.00
40.00
40.00
40.00
40.00
26.00
26.00
26.00
26.00
26.00
26.00
26.00
26.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
%
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
115.00
230.00
153.33
191.67
255.55
460.00
306.67
383.33
115.00
230.00
153.33
191.67
255.55
460.00
306.67
383.33
78.00
156.00
104.00
130.00
173.33
312.00
208.00
260.00
75.00
76.66
76.66
76.66
76.66
76.66
76.66
76.66
76.66
79.99
79.99
79.99
79.99
79.99
79.99
79.99
79.99
51.99
51.99
51.99
51.99
51.99
51.99
51.99
51.99
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
150.00
100.00
125.00
166.67
300.00
200.00
250.00
0734A—07/26/05
7
Integrated
Circuit
ICS952607
Systems, Inc.
General I2C serial interface information for the ICS952607
How to Write:
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3(H)
• ICS clock will acknowledge
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
starT bit
T
T
starT bit
Slave Address D2(H)
Slave Address D2(H)
WR
WR
WRite
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0734A—07/26/05
8
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Frequency Select Register
Control
Function
Byte 0
Pin #
Name
Type
0
1
PWD
Frequency H/W IIC
Select
-
Latch Inputs
IIC
Bit 7
FS Source
RW
0
-
-
-
-
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FS6
FS5
FS4
FS3
FS2
FSA
FSB
Freq Select Bit 6
Freq Select Bit 5
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
See Table 1: QuadRom Frequency Selection
Table
I2C Table: Spreading and Device Behavior Control Register
Control
Byte 1
Pin #
Name
Type
0
1
PWD
Function
Spread Select 1
Spread Select 0
Spread Enable Control
WD Soft Reset Enable
Output Control
-
-
-
-
00 = 0.35%
01 = 0.50%
ON
ON
Disable
-
10 = 0.75%
11 = No Spread
OFF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SS1
SS0
SS_EN
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
1
1
1
1
OFF
Enable
-
Enable
Enable
WDS_EN
SRC/SRC#
Reserved
CPUCLKT/C_1
CPUCLKT/C_0
37,36
-
43,42
40,39
Reserved
Output Control
Output Control
Disable
Disable
I2C Table: Output Control Register
Control
Function
Byte 2
Pin #
Name
Type
0
1
PWD
0: SRCT Driven during
PD#; 1: Tri-stated
-
-
-
Driven
-
Hi-Z
-
Bit 7
Bit 6
Bit 5
SRC Stop Mode
Reserved
RW
RW
RW
0
0
0
Reserved
0: CPUT Driven during
PD#; 1: Tri-stated
Driven
Hi-Z
CPUT Stop Mode
-
27
-
-
-
-
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
3V66_2
Reserved
Reserved
Reserved
Reserved
Output Control
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
0
1
1
1
1
Disable
Enable
-
-
-
-
-
-
I2C Table: Output Control Register
Control
Function
Byte 3
Pin #
Name
Type
0
1
PWD
-
-
See Table 5: Async AGP/PCI Freq Table
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASEL1
3V66/PCI Freq Select
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
1
1
1
1
1
-
-
Reserved
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
20
19
16
15
14
13
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
0734A—07/26/05
9
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Output Control Register
Control
Function
Byte 4
Pin #
Name
Type
0
1
PWD
48MHz_0
2x output drive
2x drive
100MHz
normal
200MHz
Bit 7
Bit 6
0=2x drive
RW
-
0
0
SRC Frequency
Select
SRCFS
-
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
3V66_1
3V66_0
Reserved
RW
RW
RW
RW
RW
RW
0
1
1
1
1
1
30
31
10
9
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Output Control
Output Control
Output Control
Output Control
Output Control
PCICLK_F2
PCICLK_F1
PCICLK_F0
8
I2C Table: Reserved Register
Control
Function
Byte 5
Pin #
Name
Type
0
1
PWD
3V66_3/VCH
Select
-
3V66
VCH
Bit 7
Output Select
RW
0
0
-
-
26
-
-
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Mode Sel1
Mode Sel0
3V66_3/VCH
M PLL2 Div3
M PLL2 Div2
M PLL2 Div1
M PLL2 Div0
RW
RW
RW
RW
RW
RW
RW
PLL Mode Selection Bits
Output Control
See Table 4: Mode Selection Table
Disable Enable
0
1
X
X
X
X
The decimal representation of M PLL2 Div
(3:0) + 2 is equal to REF divider value for
PLL2
M Divider Programming
bits for Async mode 2&3
-
Table 3: Linear M/N AGP/PCI Programmable Frequency Example
Hex B5b3:0 Hex B6b6:0 AGP Freq
PCI Freq
Hex B5b3:0 Hex B6b6:0 AGP Freq
PCI Freq
C
B
A
7
31
2D
29
1D
19
36
32
2E
2A
37
65.15
65.24
65.34
65.79
66.01
66.14
66.30
66.47
66.68
67.21
32.58
32.62
32.67
32.89
33.01
33.07
33.15
33.24
33.34
33.61
C
7
33
1E
2F
2B
34
30
2C
35
28
1B
67.44
67.57
67.70
68.01
68.58
68.93
69.34
69.73
69.83
70.01
33.72
33.78
33.85
34.01
34.29
34.47
34.67
34.86
34.91
35.01
B
A
C
B
A
C
9
6
D
C
B
A
D
6
0734A—07/26/05
10
Integrated
Circuit
ICS952607
Systems, Inc.
Table 4: Mode Selection Table
Mode
Standard Overclock Mode
Byte 5 bit(6:5) = 00
Byte 11 & 12
CPU Overclock Mode
Byte 5 bit(6:5) = 01
Graphic Overclock Mode
IIC Control
Byte 5 bit(6:5) = 10
Byte 11 & 12
CPU M/N Overclocking
SRC M/N Overclocking
AGP/PCI M/N Overclocking
Byte 11 & 12
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Byte 5 & 6 (asynchronous)
Byte 11 & 12
Byte 11 & 12
Byte 5 & 6 (asynchronous)
Latch input shoud be set as FS(4:0)
= 10xxx. CPU & SRC have spread.
Spreading
Remark
All clocks have spread.
Only CPU clocks have spread.
CPU overclock by Byte 11&12
SRC/AGP/PCI overclock by Byte
5&6 asynchronously.
CPU/SRC overclock by Byte 11&12
AGP/PCI overclock by Byte 5&6
asynchronously.
All clocks oveclock together by Byte
11&12 M/N programming.
Mode B (B6&B3 bit 7) AGP/PCI can
be selected to be overclock from 66/33,
72/36 or 80/40.
Simple async AGP/PCI overclocking SRC can be kept at 100 w/o spread Simple async AGP/PCI overclocking
w/o using M/N programming.
yet AGP/PCI can be overclocked.
w/o using M/N programming.
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7
Byte3 Bit7
3V66/PCI Frequency
66.66/33.33
0
0
1
0
1
0
80.00/40.00
72.73/36.36
I2C Table: Vendor & Revision ID Register
Control
Function
Byte 6
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
See Table 4: Async AGP/PCI Freq Table
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ASEL0
3V66/PCI Freq Select
RW
RW
RW
RW
RW
RW
RW
RW
0
X
X
X
X
X
X
X
N PLL2 Div6
N PLL2 Div5
N PLL2 Div4
N PLL2 Div3
N PLL2 Div2
N PLL2 Div1
N PLL2 Div0
The decimal representation of N PLL2 Div
(6:0) + 8 is equal to VCO divider value for
PLL2.
N Divider Programming
bits for Async mode 2&3
I2C Table: Vendor & Revision ID Register
Control
Function
Byte 7
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
X
X
X
X
0
0
0
1
REVISION ID
VENDOR ID
I2C Table: Byte Count Register
Control
Function
Byte 8
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
Writing to this register will configure how
many bytes will be read back, default is 0F =
15 bytes.
Byte Count
Programming b(7:0)
0734A—07/26/05
11
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Watchdog Timer Register
Control
Function
Byte 9
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
WD Timer Bit 7
WD Timer Bit 6
WD Timer Bit 5
WD Timer Bit 4
WD Timer Bit 3
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
0
1
1
These bits represent X*290ms the watchdog
timer waits before it goes to alarm mode.
Default is 11 x 293ms = 3.2s.
I2C Table: VCO Control Select Bit & WD Timer Control Register
Control
Byte 10
Pin #
Name
Type
0
1
PWD
Function
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
-
-
-
Disable
Disable
Enable
Enable
Bit 7
Bit 6
Bit 5
M/NEN
WDEN
RW
R
0
1
0
Latched FS/Byte0
WD B10 b(4:0)
WDFSEN
RW
-
-
-
-
-
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
RW
RW
RW
RW
RW
0
0
0
0
0
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
I2C Table: VCO Frequency Control Register
Control
Function
Byte 11
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up = latch-
in or Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
M Divider Programming
bits
I2C Table: VCO Frequency Control Register
Control
Function
Byte 12
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up = latch-
in or Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2]
N Divider Programming
b(8:0)
I2C Table: Spread Spectrum Control Register
Control
Function
Byte 13
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
These Spread Spectrum bits in Byte 13 and
14 will program the spread pecentage. It is
recommended to use ICS Spread % table for
spread programming.
Spread Spectrum
Programming b(7:0)
0734A—07/26/05
12
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Spread Spectrum Control Register
Control
Function
Reserved
Reserved
Byte 14
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
R
R
-
-
-
-
0
0
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
RW
RW
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(13:8)
SSP8
I2C Table: Output Divider Control Register
Control
Function
Byte 15
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
SRC Div3
SRC Div2
SRC Div1
SRC Div0
CPU Div3
CPU Div2
CPU Div1
CPU Div0
RW
RW
RW
RW
RW
RW
RW
RW
0000:/2
0001:/3
0100:/4
1000:/8 1100:/16
X
X
X
X
X
X
X
X
Bit 7
SRC Divider Ratio
Programmaing Bits
0101:/6 1001:/12 1101:/24
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
0000:/2
0001:/3
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
0100:/4
1000:/8 1100:/16
CPUDivider Ratio
Programmaing Bits
0101:/6 1001:/12 1101:/24
I2C Table: Output Divider Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Byte 16
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
3V66Div3
3V66Div2
3V66Div1
3V66Div0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000:/2
0001:/3
0100:/4
1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
3V66 Divider Ratio
Programmaing Bits
0010:/5 0110:/10 1010:/20 1110:/40
0011:/7 0111:/14 1011:/28 1111:/56
I2C Table: Output Divider Control Register
Control
Function
Byte 17
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
3V66INV
SRCINV
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
X
X
X
X
0
Bit 7
3V66 Phase Invert
SRC Phase Invert
CPU Phase Invert
Reserved
Default
Default
Default
Inverse
Inverse
Inverse
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUINV
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
-
-
Reserved
Reserved
0
0
Reserved
0
I2C Table: Group Skew Control Register
Control
Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 18
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
0734A—07/26/05
13
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Group Skew Control Register
Control
Function
Byte 19
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66Skw3
3V66Skw2
3V66Skw1
3V66Skw0
PCISkw3
PCISkw2
PCISkw1
PCISkw0
RW
RW
RW
RW
RW
RW
RW
RW
0000:0
0100:150 1000:300 1100:450
0
0
0
0
1
1
0
0
CPU-3V66 7 Step Skew
Control (ps)
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
0000:0
0100:150 1000:300 1100:450
CPU-PCI 7 Step Skew
Control (ps)
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
I2C Table: Group Skew Control Register
Control
Function
Byte 20
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCISkw3
PCISkw2
PCISkw1
PCISkw0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0000:0
0100:150 1000:300 1100:450
1
1
0
0
0
0
0
0
CPU-PCI F(2:0) 7 Step
Skew Control (ps)
0001:N/A 0101:N/A 1001:N/A 1101:600
0010:N/A 0110:N/A 1010:N/A 1110:750
0011:N/A 0111:N/A 1011:N/A 1111:900
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
I2C Table: Slew Rate Control Register
Control
Function
Byte 21
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
00 = 0.63X
01 = 0.75X
10 = 0.88X
11 = 1.00X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
PCIFStr1
PCIFStr0
Reserved
Reserved
Reserved
Reserved
PCICLKF (2:0) Strength
Control
RW
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
00 = 0.70X
01 = 0.80X
10 = 0.90X
11 = 1.00X
AGPStr1
AGPStr0
AGPCLK Strength
Control
I2C Table: Slew Rate Control Register
Control
Function
Byte 22
Pin #
Name
Type
0
1
PWD
-
-
-
-
-
-
-
-
00 = Medium
01 = Weak
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
10 = Strong
11 = N/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
1
0
1
1
1
1
1
1
REF_Slw
REF Slew Rate Control
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
PCIFStr1
PCIFStr0
PCIFStr1
PCIFStr0
PCIFStr1
PCIFStr0
PCICLK (5) Strength
Control
PCICLK (4:2) Strength
Control
RW
RW
RW
PCICLK (1:0) Strength
Control
I2C Table: Output Control Register
Control
Byte 23
Pin #
Name
Type
0
1
PWD
Function
22
21
2
1
3
23
-
-
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
-
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
0
0
48MHz_0
24_48MHz
REF1
REF0
REF2
48MHz_1
Reserved
Reserved
-
-
Reserved
0734A—07/26/05
14
Integrated
Circuit
ICS952607
Systems, Inc.
I2C Table: Read Back Register
Control
Function
Byte 24
Pin #
Name
Type
R
0
-
1
-
PWD
X
WD Hard Alarm Status
Read back
WD Soft Alarm Status
-
-
Bit 7
Bit 6
WDHRB
WDSRB
-
-
R
X
Read back
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
FS4RB
FS3RB
FS2RB
FSARB
FSBRB
R
R
R
R
R
R
0
X
X
X
X
X
FS4 Read back
FS3 Read back
FS2 Read back
FSA Read back
FSB Read back
0734A—07/26/05
15
Integrated
Circuit
ICS952607
Systems, Inc.
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)
resistor is used to provide both the solid CMOS programming
voltageneededduringthepower-upprogrammingperiodandto
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0734A—07/26/05
16
Integrated
Circuit
ICS952607
Systems, Inc.
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD + 0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
VIH
VMID
V
DD + 0.3
Input High Voltage
Input MID Voltage
3.3V +/-5%
3.3V +/-5%
2
1
V
V
1.8
VSS
0.3
-5
-
VIL
IIH
Input Low Voltage
Input High Current
3.3V +/-5%
0.8
5
V
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
uA
uA
IIL1
-5
Input Low Current
VIN = 0 V; Inputs with pull-up
resistors
IIL2
-200
uA
IDD3.3OP
IDD3.3PD
Full Active, CL = Full load;
Operating Supply Current
Powerdown Current
350
mA
all diff pairs driven
all differential pairs tri-stated
VDD = 3.3 V
35
12
mA
mA
MHz
nH
pF
Input Frequency3
Pin Inductance1
Fi
Lpin
CIN
14.31818
3
1
1
1
1
7
5
6
5
Logic Inputs
Output pin capacitance
Input Capacitance1
COUT
pF
4
X1 & X2 pins
pF
CINX
From VDD Power-Up or de-
assertion of PD# to 1st clock.
Triangular Modulation
Clk Stabilization1,2
TSTAB
1.8
33
ms
1,2
1
Modulation Frequency
30
kHz
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
4 Crystal recommendations: CL = 20pF and Shunt cap. Max = 5pF.
0734A—07/26/05
17
Integrated
Circuit
ICS952607
Systems, Inc.
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL =2pF
PARAMETER
SYMBOL
CONDITIONS
VO = Vx
MIN
TYP
MAX
850
UNITS NOTES
Current Source Output
Impedance
Zo1
Ω
3000
1
Statistical measurement on single
ended signal using oscilloscope
math function.
Voltage High
Voltage Low
VHigh
VLow
660
1
1
mV
-150
150
Measurement on single ended
signal using absolute value.
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
1150
1
1
1
mV
mV
mV
-300
250
550
140
Variation of crossing over all
edges
Crossing Voltage (var)
d-Vcross
1
Long Accuracy
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
ppm
tr
tf
d-tr
d-tf
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
-300
175
175
300
700
700
125
125
ppm
ps
ps
ps
ps
1,2
1
1
1
1
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom
dt3
tsk3
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
100
125
tjcyc-cyc
Jitter, Cycle to cycle
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
0734A—07/26/05
18
Integrated
Circuit
ICS952607
Systems, Inc.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Long Accuracy
Output High Voltage
Output Low Voltage
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
IOH = -1 mA
MIN
-300
2.4
TYP
MAX
300
UNITS Notes
ppm
V
1,2
VOH
VOL
IOL = 1 mA
V OH@MIN = 1.0 V
VOH@MAX = 3.135 V
0.55
-33
V
-33
30
mA
mA
mA
mA
V/ns
V/ns
ns
IOH
IOL
Output High Current
Output Low Current
V
V
OL @MIN = 1.95 V
OL@MAX = 0.4 V
38
4
4
2
2
Edge Rate
Edge Rate
Rise Time
Fall Time
Rising edge rate
Falling edge rate
1
1
0.5
0.5
1
1
1
1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
ns
dt1
VT = 1.5 V
VT = 1.5 V
Duty Cycle
Skew
45
55
%
ps
ps
1
1
1
tsk1
250
250
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
300
UNITS Notes
Long Accuracy
Output High Voltage
Output Low Voltage
ppm
VOH
VOL
see Tperiod min-max values
IOH = -1 mA
-300
2.4
ppm
V
1,2
IOL = 1 mA
0.55
-33
38
V
V OH@MIN = 1.0 V
VOH@MAX = 3.135 V
VOL@MIN = 1.95 V
VOL@MAX = 0.4 V
-33
30
mA
mA
mA
mA
IOH
IOL
Output High Current
Output Low Current
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
1
0.5
0.5
45
4
4
2
V/ns
V/ns
ns
ns
%
1
1
1
1
1
1
1
tr1
tf1
dt1
2
55
500
250
tsk1
VT = 1.5 V
ps
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
ps
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
0734A—07/26/05
19
Integrated
Circuit
ICS952607
Systems, Inc.
Electrical Characteristics - VCH, 48MHz, 24MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
Long Accuracy
Output High Voltage
Output Low Voltage
ppm
VOH
VOL
see Tperiod min-max values
IOH = -1 mA
-200
2.4
200
0.55
-33
ppm
V
V
mA
mA
mA
mA
V/ns
V/ns
1,2
IOL = 1 mA
V OH@MIN = 1.0 V
VOH@MAX = 3.135 V
-33
30
IOH
IOL
Output High Current
Output Low Current
VOL @MIN = 1.95 V
VOL@MAX = 0.4 V
38
2
2
Edge Rate
Edge Rate
Rising edge rate
Falling edge rate
1
1
1
1
tr1
tf1
dt1
tsk1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
Fall Time
Duty Cycle
Skew
1
1
45
2
2
55
1
ns
ns
%
1
1
1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
ns
125us period jitter
(8kHz frequency modulation
amplitude)
Long Term Jitter
6
ns
1
1Guaranteed by design, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
ppm
CONDITIONS
MIN TYP MAX
UNITS Notes
Long Accuracy
Output High Voltage
Output Low Voltage
see Tperiod min-max values
IOH = -1 mA
-300
2.4
300
ppm
V
1
1
VOH
1
IOL = 1 mA
V OH@MIN = 1.0 V, V OH@MAX
0.4
-23
V
VOL
=
1
Output High Current
Output Low Current
-29
29
mA
mA
IOH
3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4
1
27
IOL
V
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
Fall Time
Skew
1
1
2
2
ns
ns
ps
%
1
1
1
1
1
tr1
1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
tf1
1
500
55
tsk1
1
VT = 1.5 V
Duty Cycle
45
dt1
1
VT = 1.5 V
Jitter
1000
ps
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
0734A—07/26/05
20
Integrated
Circuit
ICS952607
Systems, Inc.
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
h x 45°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
VARIATIONS
- C -
D mm.
D (inch)
N
e
SEEAATTIINNGG
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952607yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
RoHS Compliant (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0734A—07/26/05
21
Integrated
Circuit
ICS952607
Systems, Inc.
Revision History
Rev.
Issue Date Description
Page #
1. Added SMBus Slave Address page.
A
7/26/2005 2. Updated LF Ordering Information to RoHS Compliant.
8, 21
0734A—07/26/05
22
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