952703FT [IDT]
Clock Generator;
| 型号： | 952703FT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总16页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Programmable Timing Control Hub for K7TM System
Recommended Application:
Features/Benefits:
SiS741 style chipset with 964 South Bridge.
•
Selectable synchronous/asynchronous AGP/PCI
frequency
•
•
•
•
•
•
Programmable output frequency.
Output Features:
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
•
•
•
•
•
•
•
•
•
•
1 - Pair of differential open drain CPU outputs
1 - Single-ended open drain CPU output
1 - Pair of current mode differential serial reference clock
8 - PCICLK @ 3.3V including 2 PCI clock free running
2 - AGPCLK @ 3.3V
3 - REF @ 3.3V
2 - ZCLK @ 3.3V
2 - IOAPIC @ 2.5V
1 - 12_48MHz @ 3.3V
•
•
•
Uses external 14.318MHz reference input.
1 - 24_48MHz @ 3.3V
Key Specifications:
•
•
•
•
•
CPU Output Jitter <250ps
AGP Output Jitter <250ps
ZCLK Output Jitter <250ps
PCI Output Jitter <500ps
CPU-AGP/PCI/ZCLK skew: 2.5ns~3.5ns
Functionality
Pin Configuration
Bit3
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bit2
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Bit0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU
MHz
SRC
MHz
ZCLK
MHz
AGP
MHz
PCI
MHz
VDDREF 1
**FS0/REF0 2
**FS1/REF1 3
**Mode/REF2 4
GNDREF 5
48 VDDLAPIC
47 IOAPIC1
46 IOAPIC0
45 GNDAPIC
Bit4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
200.00
200.01
200.97
190.11
100.00
100.00
100.99
95.00
166.66
166.65
161.59
151.97
133.33
133.34
133.98
126.66
206.02
210.00
214.06
217.90
103.01
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
133.33
133.34
133.98
126.74
133.33
133.34
134.66
126.66
133.33
133.32
129.27
121.57
133.33
133.34
133.98
126.66
137.35
140.00
142.70
145.27
137.35
66.66
66.67
66.99
63.37
66.66
66.67
67.33
63.33
66.66
66.66
64.64
60.79
66.66
66.67
66.99
63.33
68.67
70.00
71.35
72.63
68.67
33.33
33.33
33.49
31.69
33.33
33.33
33.66
31.67
33.33
33.33
32.32
30.39
33.33
33.33
33.49
31.67
34.34
35.00
35.68
36.32
34.34
VDDSRC
44
X1 6
43 SRCCLKT
42 SRCCLKC
X2 7
GND
GNDZ 8
41
ZCLK0 9
40 CPUCLKODT1
GNDCPU
ZCLK1 10
39
38
37
36
35
34
33
32
31
30
29
28
27
CPUCLKODT0
CPUCLKODC0
AVDD
VDDZ 11
SCLK 12
VDDPCI 13
AGND
*FS2/PCICLK_F0 14
*FS3/PCICLK_F1 15
PCICLK0 16
IREF
1
0
0
1
0
0
1
0
0
1
0
1
SDATA
GNDAGP
PCICLK1 17
AGPCLK0
AGPCLK1
VDDAGP
GNDPCI 18
0
0
0
0
1
1
0
1
VDDPCI 19
PCICLK2 20
0
1
0
0
AVDD48
*(PCI_STOP#)PCICLK3 21
*(CPU_STOP#)PCICLK4 22
*(PD#)PCICLK5 23
GNDPCI 24
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
105.00
106.99
109.01
164.66
167.91
171.22
174.38
137.32
140.00
142.67
145.33
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
140.00
142.65
145.35
131.73
134.33
136.98
139.50
137.32
140.00
142.67
145.33
70.00
71.33
72.68
65.86
67.17
68.49
69.75
68.66
70.00
71.34
72.66
35.00
35.66
36.34
32.93
33.58
34.24
34.88
34.33
35.00
35.67
36.33
12_48MHz/SEL12_48#MHz*
26 24_48MHz/SEL24_48#MHz**~
25 GND48
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This output have 1.5X Drive Strength
0813A—04/01/05
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
General Description
The ICS952703 is a two chip clock solution for desktop designs using SiS741 style chipsets. When used with a zero delay
buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals
for such a system.
The ICS952703 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
Frequency
Dividers
PLL2
12_48MHZ
24_48MHZ
X1
X2
XTAL
REF (2:0)
CPUCLKODT (1:0)
CPUCLKODC0
SRCCLKT
SRCCLKC
CPU_STOP#
PCI_STOP#
SCLK
Programmable
Spread
Programmable
Frequency
Dividers
SEL24_48MHZ
SEL12_48MHz
PD#
IOAPIC (1:0)
PCICLKF (1:0)
PCICLK (5:0)
ZCLK (1:0)
STOP
Logic
PLL1
Control
Logic
SDATA
FS (3:0)
MODE
AGPCLK (1:0)
0813A—04/01/05
2
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Pin Description
PIN
TYPE
PIN # PIN NAME
DESCRIPTION
1
PWR Ref, XTAL power supply, nominal 3.3V
VDDREF
**FS0/REF0
**FS1/REF1
**Mode/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
2
3
4
5
6
7
8
9
I/O
I/O
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Function select latch input pin, 0=Desktop Mode, 1=Mobile Mode / Ref clock output.
PWR Ground pin for the REF outputs.
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Ground pin for the ZCLK outputs
OUT 3.3V Hyperzip clock output.
10 ZCLK1
OUT 3.3V Hyperzip clock output.
11 VDDZ
PWR Power supply for ZCLK clocks, nominal 3.3V
12 SCLK
IN
Clock pin of I2C circuitry 5V tolerant
13 VDDPCI
14 *FS2/PCICLK_F0
15 *FS3/PCICLK_F1
16 PCICLK0
17 PCICLK1
18 GNDPCI
19 VDDPCI
20 PCICLK2
PWR Power supply for PCI clocks, nominal 3.3V
I/O
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
OUT PCI clock output.
OUT PCI clock output.
PWR Ground pin for the PCI outputs
PWR Power supply for PCI clocks, nominal 3.3V
OUT PCI clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
21
I/O
*(PCI_STOP#)PCICLK3
Stops all CPUCLKs besides the CPUCLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
22
I/O
*(CPU_STOP#)PCICLK4
Asynchronous active low input pin used to power down the device into a low power state /
PCI clock output.
23 *(PD#)PCICLK5
I/O
24 GNDPCI
25 GND48
PWR Ground pin for the PCI outputs
PWR Ground pin for the 48MHz outputs
26 24_48MHz/SEL24_48#MHz**~
27 12_48MHz/SEL12_48#MHz*
I/O
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz.
12/48MHz clock output / Latched select input for 12/48MHz output. 0=48MHz, 1 = 12MHz.
28 AVDD48
29 VDDAGP
30 AGPCLK1
31 AGPCLK0
32 GNDAGP
33 SDATA
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
PWR Power supply for AGP clocks, nominal 3.3V
OUT AGP clock output
OUT AGP clock output
PWR Ground pin for the AGP outputs
I/O
Data pin for I2C circuitry 5V tolerant
This pin establishes the reference current for the SRCCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
34 IREF
OUT
35 AGND
36 AVDD
PWR Analog Ground pin for Core PLL
PWR 3.3V Analog Power pin for Core PLL
"Complememtary" clocks of differential pair CPU outputs. These open drain outputs need
an external 1.5V pull-up.
37 CPUCLKODC0
OUT
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
PWR Ground pin for the CPU outputs
True clock of differential pair CPU outputs. These open drain outputs need an external
1.5V pull-up.
PWR Ground pin.
38 CPUCLKODT0
39 GNDCPU
40 CPUCLKODT1
41 GND
OUT
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
42 SRCCLKC
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
43 SRCCLKT
OUT
44 VDDSRC
45 GNDAPIC
46 IOAPIC0
47 IOAPIC1
48 VDDLAPIC
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the IOAPIC outputs.
OUT IOAPIC clock outputs, norminal 2.5V.
OUT IOAPIC clock outputs, norminal 2.5V.
PWR Power pin for the IOAPIC outputs. 2.5V.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
0813A—04/01/05
3
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
General SMBus serial interface information for the ICS952703
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
(see Note 2)
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• Controller (host) will need to acknowledge each
byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
starT bit
T
Slave Address D2(H)
Slave Address D2(H)
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
ACK
Data Byte Count = X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
0813A—04/01/05
4
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Table1: Frequency Selection Table
Bit3 Bit2
Bit1
Bit0
CPU
MHz
SRC
MHz
ZCLK
MHz
AGP
MHz
PCI
MHz
Spread %
Bit4
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
200.00 100.00 133.33
200.01 100.00 133.34
200.97 100.00 133.98
190.11 100.00 126.74
100.00 100.00 133.33
100.00 100.00 133.34
100.99 100.00 134.66
66.66
66.67
66.99
63.37
66.66
66.67
67.33
63.33
66.66
66.66
64.64
60.79
66.66
66.67
66.99
63.33
68.67
70.00
71.35
72.63
68.67
70.00
71.33
72.68
65.86
67.17
68.49
69.75
68.66
70.00
71.34
72.66
33.33
33.33
33.49
31.69
33.33
33.33
33.66
31.67
33.33
33.33
32.32
30.39
33.33
33.33
33.49
31.67
34.34
35.00
35.68
36.32
34.34
35.00
35.66
36.34
32.93
33.58
34.24
34.88
34.33
35.00
35.67
36.33
0.5% down
0.35% center
0.35% center
0.35% center
0.5% down
0.35% center
0.35% center
0.35% center
0.5% down
0.35% center
0.35% center
0.35% center
0.5% down
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
0.35% center
95.00
100.00 126.66
166.66 100.00 133.33
166.65 100.00 133.32
161.59 100.00 129.27
151.97 100.00 121.57
133.33 100.00 133.33
133.34 100.00 133.34
133.98 100.00 133.98
126.66 100.00 126.66
206.02 100.00 137.35
210.00 100.00 140.00
214.06 100.00 142.70
217.90 100.00 145.27
103.01 100.00 137.35
105.00 100.00 140.00
106.99 100.00 142.65
109.01 100.00 145.35
164.66 100.00 131.73
167.91 100.00 134.33
171.22 100.00 136.98
174.38 100.00 139.50
137.32 100.00 137.32
140.00 100.00 140.00
142.67 100.00 142.67
145.33 100.00 145.33
0813A—04/01/05
5
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
I2C Table: Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
SS_EN
SEL12_48MHz
SEL24_48MHz
Bit4
Spread Enable
Output Select
Output Select
Freq Select Bit 4
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
RW
RW
RW
RW
RW
RW
RW
OFF
48MHz
48MHz
ON
12MHz
24MHz
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Latch
Latch
0
FS3
Latch
Latch
Latch
Latch
See Table1: Frequency Selection Table
FS2
FS1
FS0
I2C Table: Output Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
PWD
2
3
REF0
REF1
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
REF2
43,42
14
15
16
17
SRCCLKT/C
PCICLK_F0
PCICLK_F1
PCICLK0
PCICLK1
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
20
21
22
23
26
27
30
31
PCICLK2
PCICLK3
PCICLK4
PCICLK5
24_48MHz
12_48MHz
AGPCLK1
AGPCLK0
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
RW
RW
RW
RW
RW
RW
RW
RW
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C Table: Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
-
-
Reserved
Reserved
Reserved
Reserved
RW
RW
-
-
-
-
1
0
Bit 7
Bit 6
-
-
-
-
-
-
IREF Bit1
IREF Bit0
IREF Mulitiplier
Programming Bits
RW
RW
RW
RW
RW
00 = 5 x Iref
10 = 6 x Iref
1
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01 = 4 x Iref
11 = 7 x Iref
Vendor_ID3
Vendor_ID2
Vendor_ID1
-
-
-
-
-
-
-
-
Vendor ID
Vendor_ID0
RW
1
0813A—04/01/05
6
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
I2C Table: Output Skew Control Register
Byte 4
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
PCISkw3
PCISkw2
PCISkw1
PCISkw0
AGPSkw3
AGPSkw2
AGPSkw1
AGPSkw0
RW
0000:0 0100:150 1000:300 1100:450
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU-PCI 7 Step Skew RW 0001:N/A 0101:N/A 1001:N/A 1101:600
Control (ps)
RW 0010:N/A 0110:N/A 1010:N/A 1110:750
RW 0011:N/A 0111:N/A 1011:N/A 1111:900
RW
0000:0 0100:150 1000:300 1100:450
CPU-AGP 7 Step Skew RW 0001:N/A 0101:N/A 1001:N/A 1101:600
Control (ps)
RW 0010:N/A 0110:N/A 1010:N/A 1110:750
RW 0011:N/A 0111:N/A 1011:N/A 1111:900
I2C Table: Output Divider Control Register
Byte 5
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
ZCLKDiv3
ZCLKDiv2
ZCLKDiv1
ZCLKDiv0
AGPDiv3
AGPDiv2
AGPDiv1
AGPDiv0
RW 0000:/2
RW 0001:/3
RW 0010:/5 0110:/10 1010:/20 1110:/40
RW 0011:/7 0111:/14 1011:/28 1111:/56
RW 0000:/2
RW 0001:/3
RW 0010:/5 0110:/10 1010:/20 1110:/40
RW 0011:/7 0111:/14 1011:/28 1111:/56
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZCLK Divider Ratio
Programmaing Bits
0100:/4 1000:/8 1100:/16
0101:/6 1001:/12 1101:/24
AGP Divider Ratio
Programmaing Bits
I2C Table: Output Drive Control Register
Byte 6
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
RW
RW
RW
RW
RW
RW
RW
RW
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
00 = 0.63X
01 = 0.75X
00 = 0.70X
01 = 0.80X
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
10 = 0.88X
11 = 1.00X
10 = 0.90X
11 = 1.00X
1
1
1
1
1
1
1
1
PCIStr1
PCIStr0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLKF (1:0)
Strength Control
PCIStr1
PCIStr0
PCIStr1
PCIStr0
AGPStr1
AGPStr0
PCICLK (2:0) Strength
Control
PCICLK (5:3) Strength
Control
AGPCLK Strength
Control
I2C Table: Reserved Register
Byte 7
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0813A—04/01/05
7
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Byte Count
Programming b(7:0)
I2C Table: WD Time Control & Async Frequency Selection Register
Byte 9
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
Reserved
ASYNC1
Reserved
RW
RW
RW
RW
-
-
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Fix PLL Async Freq
Programming bits
See Table 2: Asynchronous Frequency
Selection Table
ASYNC0
Reserved
Reserved
Reserved
Reserved
Watch Dog Time base
Control
-
290ms Base
1160ms Base
WDTCtrl
RW
RW
0
Bit 3
-
-
-
WD2
WD1
WD0
WD Timer Bit 2
WD Timer Bit 1
1
1
1
These bits represent X*290ms (or 1.16S)
RW the watchdog timer waits before it goes to
alarm mode. Default is 7 X 290ms = 2s.
RW
Bit 2
Bit 1
Bit 0
WD Timer Bit 0
Table 2: Asynchronous Frequency Selection Table
B9 bit6
B9 bit5
SRC
ZCLK
AGP
PCI
0
0
1
1
0
1
0
1
Main PLL Main PLL Main PLL Main PLL
100
100
100
133.33
150.00
133.33
66.66
75
80
33.33
37.5
40
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Control Function
Type
0
1
PWD
M/N Programming
Enable
-
Disable
Enable
M/NEN
RW
0
Bit 7
-
-
-
-
-
-
-
WDEN
WDStatus
WD SF4
WD SF3
WD SF2
WD SF1
Watchdog Enable
WD Alarm Status
RW
R
Disable
Normal
Enable
Alarm
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RW
RW
RW
RW
Watch Dog Safe Freq
Programming bits
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
WD SF0
RW
0
0813A—04/01/05
8
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
I2C Table: VCO Frequency Control Register
Byte 11
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
N Div8
N Div9
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
N Divider Prog bit 8
N Divider Prog bit 9
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
M Divider Programming
bits
I2C Table: VCO Frequency Control Register
Byte 12
Pin #
Name
Control Function
Type
0
1
PWD
-
-
N Div7
N Div6
RW
RW
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table.
VCO Frequency = 14.318 x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
-
-
-
-
-
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
N Divider Programming
b(7:0)
I2C Table: Spread Spectrum Control Register
Byte 13
Pin #
Name
Control Function
Type
0
1
PWD
-
-
-
-
-
-
-
-
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Spread Spectrum
Programming b(7:0)
I2C Table: Spread Spectrum Control Register
Byte 14
Pin #
Name
Control Function
Type
0
1
PWD
-
-
Reserved
SSP14
Reserved
R
-
-
0
Bit 7
RW
X
Bit 6
-
-
-
-
-
-
SSP13
SSP12
SSP11
SSP10
SSP9
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Spectrum
Programming b(14:8)
SSP8
0813A—04/01/05
9
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Absolute Maximum Ratings
Core SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . 4.6V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient OperatingTemperature . . . . . . . . . . . . . 0°C to +70°C
StorageTemperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
CaseTemperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Theseratingsarestress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sectionsofthespecificationsisnotimplied. Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectproduct
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD + 0.3
0.8
UNITS
V
VIL
VSS - 0.3
V
IIH
VIN = VDD
5
mA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
Operating Supply
Current
Power Down Supply
Current
IIL2
-200
IDD(op)
IDDPD
CL = 0 pF; Select @ 100MHz
180
40
mA
mA
CL = 0 pF; With input address to Vdd or
GND
Input frequency
Fi
VDD = 3.3 V;
11
27
16
5
MHz
pF
CIN
Logic Inputs
Input Capacitance1
CINX
Ttrans
TSTAB
X1 & X2 pins
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ns
3
TCPU-PCI VT = 1.5 V
1.5
4
1Guaranteed by design, not 100% tested in production.
0813A—04/01/05
10
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Current Source
Output Impedance
Output High Voltage
SYMBOL
Zo1
CONDITIONS
MIN
3000
2.4
TYP
MAX UNITS
VO = Vx
Ω
VOH3
VOL3
tr3
IOH = -1 mA
IOL = 1 mA
V
Output Low Voltage
Rise Time
0.4
VOL = 0.175V, VOH = 0.525V
VOH = 0.175V VOL = 0.525V
VT = 50%
175
175
45
700
700
55
ps
ps
%
Fall Time
tf3
Duty Cycle
dt3
Skew
tsk3
VT = 50%
100
150
ps
ps
1
Jitter, Cycle to cycle
VT = 50%
tjcyc-cyc
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
tr1
CONDITIONS
MIN
2.1
TYP
MAX UNITS
V
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
0.4
-22
57
V
mA
mA
ns
ns
%
16
45
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
Fall Time1
Duty Cycle1
tf1
2
dt1
55
Skew1
tsk1
VT = 1.5 V
500
500
500
ps
ps
ps
1
tjcyc-cyc
VT = 1.5 V
VT = 1.5 V
Jitter
tjabs1
1Guaranteed by design, not 100% tested in production.
0813A—04/01/05
11
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Electrical Characteristics - AGPCLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
12
55
Ω
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.55
-33
38
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
0.5
0.5
45
2
1
Fall Time
tf1
2
1
Duty Cycle
55
dt1
1
Skew
tsk1
VT = 1.5 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V 3V66
Jitter
Electrical Characteristics - REF
TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
mA
mA
ns
ns
%
IOH5
IOL5
16
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
Fall Time1
Duty Cycle1
dt5
55
tjcyc-cyc5 VT = 1.5 V
tjabs5 VT = 1.5 V
1000
800
ps
ps
Jitter1
0813A—04/01/05
12
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Electrical Characteristics - ZCLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Frequency
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
1
RDSP1
VO = VDD*(0.5)
12
55
Ω
V
1
VOH
IOH = -1 mA
2.4
1
VOL
IOL = 1 mA
0.55
-33
38
V
1
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
mA
mA
ns
ns
%
IOH
1
IOL
1
tr1
0.5
0.5
45
2
1
Fall Time
tf1
2
1
Duty Cycle
55
dt1
1
Skew
tsk1
VT = 1.5 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V
Jitter
0813A—04/01/05
13
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supplyortheGND(logic0)voltagepotential. A10Kilohm(10K)
resistor is used to provide both the solid CMOS programming
voltageneededduringthepower-upprogrammingperiodandto
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0813A—04/01/05
14
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following.All PCI and stoppable PCI_F clocks will latch low in their next
high to low transition.The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP#Waveforms
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.The final state
of the stopped CPU signals is CPUT=Low and CPUC=High.There is to be no change to the output drive current values.The CPUT
will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP#Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
0
Normal
Normal
Float
iref * Mult
0813A—04/01/05
15
Integrated
Circuit
Systems, Inc.
ICS952703
Preliminary Product Preview
In Millimeters
In Inches
c
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
h
L
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
α
0.635 BASIC
0.025 BASIC
h x 45°
D
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
A
A1
VARIATIONS
- C -
D mm.
D (inch)
N
MIN
15.75
MAX
16.00
MIN
.620
MAX
e
SEATING
PLANE
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS952703yFT
Example:
ICS 95XXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0813A—04/01/05
16
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