9DBU0941_17 [IDT]
9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms;
| 型号： | 9DBU0941_17 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer with Zo=100ohms PC |
| 文件： | 总17页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
9-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
with Zo=100ohms
9DBU0941
DATASHEET
Description
Features/Benefits
The 9DBU0941 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100 transmission lines. The device has 9
output enables for clock management, and 3 selectable
SMBus addresses.
• Direct connection to 100 transmission lines; save 36
resistors compared to standard HCSL outputs
• 47mW typical power consumption; eliminates thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
• Spread Spectrum (SS) compatible; allows SS for EMI
reduction
• OE# pins for each output; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
Output Features
• 9 1–167MHz Low-Power (LP) HCSL DIF pairs with
ZO=100
• SMBus-selectable features; optimize signal integrity to
application
Key Specifications
• DIF additive cycle-to-cycle jitter < 5ps
• DIF output-to-output skew < 60ps
• DIF additive phase jitter is < 300fs rms for PCIe Gen3
• DIF additive phase jitter < 350s rms for SGMII
• slew rate for each output
• differential output amplitude
• Device contains default configuration; SMBus interface not
required for device operation
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• 6 × 6 mm 48-VFQFPN; minimal board space
Block Diagram
vOE(8:0)#
9
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
CONTROL
LOGIC
SCLK_3.3
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©2017 Integrated Device Technology, Inc.
9DBU0941 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSADR_tri 1
vOE8# 2
36 DIF5#
35 DIF5
DIF8 3
34 vOE4#
33 DIF4#
32 DIF4
DIF8# 4
VDDR1.5 5
CLK_IN 6
31 VDDIO
30 VDDO1.5
29 GND
9DBU0941
CLK_IN# 7
GNDR 8
epad is GND
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
VDDDIG1.5 12
28 vOE3#
27 DIF3#
26 DIF3
25 vOE2#
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
+
Read/Write bit
SADR
Address
1101011
1101100
1101101
x
x
x
0
M
1
State of SADR on first application of
CKPWRGD_PD#
Power Management Table
SMBus
OEx bit
DIFx
True O/P
Low
CKPWRGD_PD#
CLK_IN
OEx# Pin
Comp. O/P
Low
Low
Running
Low
0
1
1
1
X
X
0
1
1
X
X
0
Running
Running
Running
Low
Running
Low
1
Power Connections
Pin Number
Description
VDD
VDDIO
GND
Input receiver
analog
5
8
12
9
Digital power
DIF outputs
20,30,31,38
13,21,31,39,47
22,29,40
Note: EPAD on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
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9DBU0941 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. It has an internal 120kohm pull down
1
vSADR_tri
IN
IN
resistor. See SMBus Address Selection Table.
Active low input for enabling output 8. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
2
vOE8#
3
4
DIF8
DIF8#
OUT
OUT
Differential true clock output.
Differential complementary clock output.
1.5V power for differential input clock (receiver). This VDD should be treated as an
Analog power rail and filtered appropriately.
5
VDDR1.5
PWR
6
7
8
9
CLK_IN
CLK_IN#
GNDR
IN
IN
GND
GND
IN
I/O
PWR
PWR
True input for differential reference clock.
Complementary input for differential reference clock.
Analog ground pin for the differential input (receiver)
Ground pin for digital circuitry.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
GNDDIG
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.5
13 VDDIO
1.5V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling output 0. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
14 vOE0#
IN
15 DIF0
16 DIF0#
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 1. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Differential true clock output.
Differential complementary clock output.
Power supply, nominally 1.5V
Power supply for differential outputs
Ground pin.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 2. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 3. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Ground pin.
17 vOE1#
IN
18 DIF1
OUT
OUT
PWR
PWR
GND
OUT
OUT
19 DIF1#
20 VDD1.5
21 VDDIO
22 GND
23 DIF2
24 DIF2#
25 vOE2#
IN
26 DIF3
27 DIF3#
OUT
OUT
28 vOE3#
IN
29 GND
GND
PWR
PWR
OUT
OUT
30 VDDO1.5
31 VDDIO
32 DIF4
Power supply for outputs, nominally 1.5V.
Power supply for differential outputs
Differential true clock output.
33 DIF4#
Differential complementary clock output.
Active low input for enabling output 4. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 5. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Power supply, nominally 1.5V
34 vOE4#
IN
35 DIF5
36 DIF5#
OUT
OUT
37 vOE5#
IN
38 VDD1.5
39 VDDIO
40 GND
PWR
PWR
GND
Power supply for differential outputs
Ground pin.
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9DBU0941 DATASHEET
Pin Descriptions (cont.)
PIN #
41 DIF6
42 DIF6#
PIN NAME
TYPE
OUT
OUT
DESCRIPTION
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 6. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 7. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Power supply for differential outputs
46 vOE7#
47 VDDIO
IN
PWR
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This
pin has internal 120kohm pull-up resistor.
48 ^CKPWRGD_PD#
49 EPAD
IN
Connect EPAD to ground.
GND
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100
2pF
2pF
Rs
Note: The device can drive transmission line lengths greater
than those allowed by the PCIe SIG
Driving LVDS
3.3V
R7a
Driving LVDS
R7b
R8b
Cc
Rs
Zo
Cc
R8a
Rs
LVDS Clock
input
Device
Driving LVDS inputs
Component
R7a, R7b
Value
Note
Receiver has Receiver does not
termination have termination
10K ohm
5.6K ohm
0.1µF
140 ohm
75 ohm
0.1µF
R8a, R8b
Cc
Vcm
1.2 volts
1.2 volts
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9DBU0941 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBU0941. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2
VDD+0.5
Supply Voltage
Input Voltage
VDDx
VIN
Applies to VDD, VDDA and VDDIO
V
V
1,2
1,
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.3
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1 Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.0V.
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
725
UNITS NOTES
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
200
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
VSWING
dv/dt
IIN
Differential value
Measured differentially
VIN = VDD , VIN = GND
300
0.4
-5
1450
8
5
mV
V/ns
µA
1
1,2
Input Duty Cycle
dtin
Measurement from differential waveform
45
0
50
55
150
%
1
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
ps
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero.
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Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Supply Voltage
Output Supply Voltage
VDDx
VDDIO
Supply voltage for core and analog
Low voltage supply LP-HCSL outputs
1.425
0.95
1.5
1.05-1.5
1.575
1.575
V
V
1
1
Ambient Operating
Temperature
Input High Voltage
Commercial range
Industrial range
Single-ended inputs, except SMBus
0
-40
0.75 VDD
25
25
70
85
VDD + 0.3
°C
°C
V
TAMB
VIH
VIM
VIL
IIN
Input Mid Voltage
Input Low Voltage
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
0.4 VDD
-0.3
0.6 VDD
0.25 VDD
5
V
V
Single-ended inputs, VIN = GND, VIN = VDD
-5
µA
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
Input Current
IINP
-200
1
200
µA
V
Input Frequency
Pin Inductance
Fin
Lpin
167
7
MHz
nH
pF
2
1
CIN
Logic inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
1
Capacitance
CINDIF_IN
COUT
2.7
6
pF
1,5
1
pF
From VDD power-up and after input clock
Clk Stabilization
TSTAB
fMODINPCIe
fMODIN
1
33
66
3
ms
kHz
kHz
clocks
µs
1,2
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
30
0
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
tLATOE#
tDRVPD
1
1,3
1,3
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
2
2
Trise
tR
Rise time of single-ended control inputs
5
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.6
3.3
0.4
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
at IPULLUP
2.1
V
4
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
at VOL
4
mA
V
Bus Voltage
1.425
3.3
1000
300
(Max VIL - 0.15V) to (Min VIH + 0.15V)
(Min VIH + 0.15V) to (Max VIL - 0.15V)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
Maximum SMBus operating frequency
400
kHz
6
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200 mV.
4 For VDDSMB < 3.3V, VIHSMB > = 0.8xVDDSMB.
5 DIF_IN input.
6 The differential input clock must be running for the SMBus to be active.
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Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
Slew Rate
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
dV/dt
dV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, scope averaging on
1
0.7
2.4
1.7
9
3.5
2.5
20
1,2,3
1,2,3
1,2,4
Slew Rate Matching
Voltage High
dV/dt
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
630
750
26
850
7
7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
763
22
1448
390
11
1150
7
7
1,2
1,5
1,6
mV
-300
300
250
mV
mV
mV
Vcross_abs
Scope averaging off
Scope averaging off
550
140
-Vcross
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
VDDO1.5+VDDR, at 100MHz
VDDx, All outputs active at 100MHz
3
6
mA
mA
mA
IDDA
IDDx
2.3
4.5
Operating Supply Current
VDDIO, All outputs active at 100MHz
VDDO1.5+VDDR, CKPWRGD_PD# = 0
VDDx, CKPWRGD_PD# = 0
40
1
IDDIO
33
0.4
2
2
2
IDDAPD
IDDxPD
IDDIOPD
mA
mA
mA
Powerdown Current
0.2
0.6
0.1
VDDIO, CKPWRGD_PD# = 0
0.001
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
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9DBU0941 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Duty Cycle Distortion
Skew, Input to Output
Skew, Output to Output
Jitter, Cycle to Cycle
tDCD
tpdBYP
tsk3
Measured differentially, at 100MHz
VT = 50%
-1
-0.2
2862
30
0.5
3700
60
%
ps
ps
ps
1,3
1
2400
VT = 50%
1,4
1,2
tjcy c-cy c
Additive Jitter
0.1
5
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform.
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock.
4 All outputs at default slew rate.
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB, Supply voltages per normal operation conditions; see Test Loads for loading conditions
INDUSTRY
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
MIN
TYP
0.1
MAX
5
LIMIT
UNITS Notes
ps (p-p) 1,2,3,5
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
N/A
ps
(rms)
ps
1,2,3,4,
5
0.1
0.1
0.1
0.4
0.7
0.3
N/A
N/A
N/A
tjphPCIeG2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
1,2,3,4
1,2,3,4
(rms)
ps
tjphPCIeG3
Additive Phase Jitter
(2-4MHz or 2-5MHz, CDR = 10MHz)
(rms)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
fs
(rms)
tjphSGMIIM0
200
313
250
350
N/A
N/A
1,6
1,6
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
fs
(rms)
tjphSGMIIM1
1Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2].
5 Driven by 9FGV0831 or equivalent.
6 Rohde & Schwarz SMA100.
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Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
RMS additive jitter: 313fs
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9DBU0941 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a stop bit
• IDT clock sends Byte 0 through Byte X (if X was
(H)
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
T
Slave Address
WR
WRite
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Address is Latched on SADR pin.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
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SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF OE7
DIF OE6
DIF OE5
DIF OE4
DIF OE3
DIF OE2
DIF OE1
DIF OE0
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
1
1
1
1
1
1
1
1
1. A low on these bits will override the OE# pin and force the differential output Low/Low
SMBus Table: Output Enable and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Reserved
Output Enable
Type
0
1
Default
0
1
1
0
1
1
1
0
DIF OE8
RW
Low/Low
Enabled
Reserved
Reserved
Reserved
AMPLITUDE 1
AMPLITUDE 0
RW
RW
00 = 0.55V
10 = 0.7V
01= 0.65V
11 = 0.8V
Controls Output Amplitude
1. A low on the DIF OE bit will override the OE# pin and force the differential output Low/Low
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
SLEWRATESEL DIF7
SLEWRATESEL DIF6
SLEWRATESEL DIF5
SLEWRATESEL DIF4
SLEWRATESEL DIF3
SLEWRATESEL DIF2
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF7
Adjust Slew Rate of DIF6
Adjust Slew Rate of DIF5
Adjust Slew Rate of DIF4
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF2
Adjust Slew Rate of DIF1
Adjust Slew Rate of DIF0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
1
1
1
1
1
1
1
1
SMBus Table: DIF Slew Rate Control Register
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Name
Control Function
Reserved
Type
0
1
Default
1
1
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Adjust Slew Rate of DIF8
SLEWRATESEL DIF8
RW
Slow Setting
Fast Setting
Byte 4 is Reserved and reads back 'hFF
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9DBU0941 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
0
0
0
0
1
Revision ID
A rev = 0000
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx,
10 = DMx, 11= DBx w/oPLL
1
1
0
0
1
0
0
1
Device Type
Device ID
001001binary or 09 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
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9DBU0941 DATASHEET
Marking Diagrams
ICS
DBU0941AL
YYWW
COO
ICS
BU0941AIL
YYWW
COO
LOT
LOT
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. YYWW is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “L” denotes RoHS compliant package.
6. “I” denotes industrial temperature range device.
Thermal Characteristics
TYP
VALUE
33
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
Junction to Case
Junction to Base
1
1
1
1
1
1
θJC
θJb
2.1
37
30
27
26
Junction to Air, still air
θJA0
θ
Thermal Resistance
NDG48
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
θJA1
θJA3
θJA5
1ePad soldered to board
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Package Outline and Dimensions (NDG48)
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MARCH 9, 2017
9DBU0941 DATASHEET
Package Outline and Dimensions (NDG48), cont.
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Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
9DBU0941AKLF
9DBU0941AKLFT
9DBU0941AKILF
9DBU0941AKILFT
Trays
Tape and Reel
Trays
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Tape and Reel
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev. Initiator Issue Date Description
Page #
A
RDW
7/15/2014 Final update and release - front page and electrical tables.
Various
Updated SMBus Input High/Low parameters conditions, MAX values, and
B
RDW
9/19/2014
footnotes.
6
1. Minor updates to front page text for family consistency.
4/17/2015 2. Updated Clock Input Parameters table to be consistent with PCIe
Vswing parameter.
C
D
RDW
RDW
1,5
2, 3
1. Updated pins 30 and 29 from VDDA1.5 and GNDA to VDDO1.5 and
2/16/2017
GND to clearly indicate that this part has no PLL.
1. Removed "Bypass Mode" reference in "Output Duty Cycle..." and
"Phase Jitter Parameters" tables; update note 3 under Output Duty Cycle
table.
E
RDW
3/9/2017
7,8
2. Corrected spelling errors/typos.
3. Change VDDA to VDDO1.5 in Current Consumption table.
4. Update Additive Phase Jitter conditions for PCIe Gen3.
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MARCH 9, 2017
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notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
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IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
9DBU0941 MARCH 9, 2017
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