9DBV0231 [IDT]
2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer;
| 型号： | 9DBV0231 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2-output 1.8V PCIe Gen1/2/3 Zero Delay /Fanout Buffer PC |
| 文件： | 总17页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2-output 1.8V PCIe Gen1/2/3 Zero Delay /
Fanout Buffer
9DBV0231
DATASHEET
Description
Features/Benefits
The 9DBV0231 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 2 output enables for clock
management.
• LP-HCSL outputs; save 4 resistors compared to standard
HCSL outputs
• 35mW typical power consumption in PLL mode; reduced
thermal concerns
• Spread Spectrum (SS) compatible; allows use of SS for
Recommended Application
1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
EMI reduction
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
Output Features
• 2 – 1-200MHz Low-Power (LP) HCSL DIF pairs
• SMBus-selectable features; optimize signal integrity to
application
• slew rate for each output
• differential output amplitude
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms (12k-20MHz)
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
vOE(1:0)#
2
DIF1
CLK_IN
CLK_IN#
SS-
Compatible
PLL
DIF0
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
CONTROL
LOGIC
SCLK_3.3
9DBV0231 REVISION F 04/28/16
1
©2016 Integrated Device Technology, Inc.
9DBV0231 DATASHEET
Pin Configuration
24 23 22 21 20 19
FB_DNC# 1
VDDR1.8 2
CLK_IN 3
CLK_IN# 4
GNDR 5
DIF1#
DIF1
18
17
16
15
14
9DBV0231
epad is Gnd
VDDA1.8
GNDA
DIF0#
GNDDIG 6
13 DIF0
7
8
9 10 11 12
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down
resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
Power Management Table
SMBus
OEx bit
DIFx
True O/P
CKPWRGD_PD#
CLK_IN
OEx# Pin
PLL
Comp. O/P
Low
0
1
1
1
X
X
0
X
X
0
Low
Low
Off
On1
On1
On1
Running
Running
Running
Low
1
1
Running
Low
Running
Low
1
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
SMBus Address Table
Frequency Select Table
+
Read/Write bit
FSEL
Byte3 [4:3]
00 (Default)
01
CLK_IN
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
Address
1101101
(MHz)
100.00
50.00
125.00
Reserved
x
Power Connections
10
11
Pin Number
VDD
2
Description
GND
5
6
10,21
15
Input receiver analog
Digital Power
DIF outputs
PLL Operating Mode
7
Byte1 [7:6] Byte1 [4:3]
Readback
11,20
16
HiBW_BypM_LoBW#
MODE
PLL Lo BW
Bypass
Control
00
PLL Analog
0
M
1
00
01
11
01
11
PLL Hi BW
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
2
REVISION F 04/28/16
9DBV0231 DATASHEET
Pin Descriptions
Pin#
Pin Name
Type
Description
Complement clock of differential feedback. The feedback output
and feedback input are connected internally on this pin. Do not
connect anything to this pin.
1
FB_DNC#
DNC
1.8V power for differential input clock (receiver). This VDD should
be treated as an Analog power rail and filtered appropriately.
True Input for differential reference clock.
Complementary Input for differential reference clock.
Analog Ground pin for the differential input (receiver)
Ground pin for digital circuitry
2
VDDR1.8
PWR
3
4
5
6
7
8
9
CLK_IN
CLK_IN#
GNDR
GNDDIG
VDDDIG1.8
SCLK_3.3
SDATA_3.3
IN
IN
GND
GND
PWR
IN
I/O
GND
PWR
1.8V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ground pin.
Power supply for outputs, nominally 1.8V.
Active low input for enabling DIF pair 0. This pin has an internal pull-
down.
10 GND
11 VDDO1.8
12 vOE0#
IN
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin for the PLL core.
1.8V power for the PLL core.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-
down.
13 DIF0
OUT
OUT
GND
PWR
OUT
OUT
14 DIF0#
15 GNDA
16 VDDA1.8
17 DIF1
18 DIF1#
19 vOE1#
IN
1 =disable outputs, 0 = enable outputs
Power supply for outputs, nominally 1.8V.
Ground pin.
20 VDDO1.8
21 GND
PWR
GND
Input notifies device to sample latched inputs and start up on first
high assertion. Low enters Power Down Mode, subsequent high
assertions exit Power Down Mode. This pin has internal pull-up
resistor.
22 ^CKPWRGD_PD#
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
23 ^vHIBW_BYPM_LOBW#
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and
feedback input are connected internally on this pin. Do not connect
anything to this pin.
24 FB_DNC
25 ePad
DNC
GND
Connect epad to ground.
NOTE: DNC indicates Do Not Connect anything to this pin.
REVISION F 04/28/16
3
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
L
Rs
Zo=100ohm
2pF
2pF
Rs
Device
L = 5 inches
Differential Output Terminations
Rs
33
27
Zo
100
85
Units
Ohms
Alternate Terminations
The 9DBV family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
4
REVISION F 04/28/16
9DBV0231 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0231. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2.5
VDD+0.5V
1.8V Supply Voltage
Input Voltage
VDDxx
VIN
Applies to all VDD pins
V
V
1,2
1, 3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.6V
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
Electrical Characteristics–Clock Input Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1000
UNITS NOTES
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
150
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
VSWING
dv/dt
IIN
Differential value
Measured differentially
300
0.4
-5
1450
8
mV
V/ns
uA
1
1,2
VIN = VDD , VIN = GND
5
dtin
Measurement from differential wavefrom
45
0
55
%
1
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
125
ps
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
REVISION F 04/28/16
5
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Supply Voltage
SYMBOL
VDDx
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
UNITS NOTES
V
Supply voltage for core and analog
Commmercial range
Industrial range
0
25
25
70
85
°C
°C
V
Ambient Operating
Temperature
TAMB
-40
Input High Voltage
Input Mid Voltage
Input Low Voltage
VIH
VIM
Single-ended inputs, except SMBus
0.75 VDD
VDD + 0.3
Single-ended tri-level inputs ('_tri' suffix)
0.4 VDD
0.6 VDD
V
VIL
IIN
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
-0.3
-5
0.25 VDD
5
V
uA
Input Current
V
IN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
IINP
-200
200
uA
Fibyp
Fipll
1
50
200
140
175
65
7
MHz
MHz
MHz
MHz
nH
2
2
100MHz PLL mode
100.00
125.00
50.00
Input Frequency
Fipll
125MHz PLL mode
62.5
25
2
Fipll
50MHz PLL mode
2
Pin Inductance
Capacitance
Lpin
1
CIN
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
1.5
1.5
5
pF
1
CINDIF_IN
COUT
2.7
6
pF
1,5
1
pF
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
Clk Stabilization
TSTAB
1
ms
1,2
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
fMODINPCIe
fMODIN
tLATOE#
tDRVPD
30
0
33
66
3
kHz
kHz
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
1
clocks
us
1,3
1,3
300
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
2
2
Trise
tR
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
5
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.6
3.6
0.4
2.1
V
4
SMBus Output Low Voltage VOLSMB
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
@ VOL
4
mA
V
Bus Voltage
1.7
3.6
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
Maximum SMBus operating frequency
400
kHz
6
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
5DIF_IN input
6The differential input clock must be running for the SMBus to be active
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
6
REVISION F 04/28/16
9DBV0231 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
dV/dt
dV/dt
dV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
1.9
1.4
3.2
2.3
5
4
3.3
20
1,2,3
1,2,3
1,2,4
Slew rate matching
Voltage High
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
660
779
21
850
7
7
mV
Voltage Low
VLOW
-150
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vmax
Vmin
Vcross_abs
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
835
-42
409
14
1150
7
7
1,5
1,6
mV
-300
250
550
140
mV
mV
Crossing Voltage (var)
-Vcross
Scope averaging off
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDA
CONDITIONS
MIN
TYP
4.4
MAX
6
UNITS NOTES
VDDA+VDDR, PLL Mode, @100MHz
VDD, All outputs active @100MHz
VDDA+VDDR, PLL Mode, @100MHz
VDD, Outputs Low/Low
mA
mA
1
Operating Supply Current
IDD
1
14.2
0.014
0.9
18
1
1, 2
1, 2
IDDAPD
IDDPD
mA
mA
Powerdown Current
1.4
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
REVISION F 04/28/16
7
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
2
1
2.7
1.4
1.05
4
2
2
MHz
MHz
dB
1,5
1,5
1
PLL Bandwidth
BW
PLL Jitter Peaking
Duty Cycle
tJPEAK
tDC
Measured differentially, PLL Mode
45
-1
50
55
%
1
Duty Cycle Distortion
Skew, Input to Output
tDCD
Measured differentially, Bypass Mode @100MHz
-0.1
1
%
1,3
tpdBYP
tpdPLL
tsk3
Bypass Mode, VT = 50%
PLL Mode VT = 50%
2600
0
3370
112
4200
200
ps
ps
1
1,4
Skew, Output to Output
Jitter, Cycle to cycle
VT = 50%
PLL mode
Additive Jitter in Bypass Mode
33
13
0.1
50
50
5
ps
ps
ps
1,4
1,2
1,2
tjcyc-cyc
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
INDUSTRY
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
PCIe Gen 1
MIN
TYP
32
MAX
52
LIMIT
86
UNITS Notes
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
ps
0.8
2.4
1.4
2.5
0.6
3
3.1
1
1,2,3,5
(rms)
tjphPCIeG2
ps
1,2,3,5
(rms)
Phase Jitter, PLL Mode
ps
tjphPCIeG3
tjphSGMII
0.5
1,2,3,5
(rms)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
ps
(rms)
1.9
2
NA
N/A
N/A
N/A
N/A
1,6
tjphPCIeG1
PCIe Gen 1
0.1
5
ps (p-p) 1,2,3,5
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
ps
(rms)
ps
(rms)
ps
1,2,3,4,
5
0.2
0.3
0.1
0.1
tjphPCIeG2
0.00
0.00
1,2,3,4
1,2,3,4
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
Additive Phase Jitter,
Bypass Mode
tjphPCIeG3
(rms)
125MHz, 1.5MHz to 10MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
ps
(rms)
tjphSGMII
165
251
200
300
N/A
N/A
1,6
1,6
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
ps
(rms)
tjphSGMII
1Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FG432 or equivalent
6 Rohde&Schartz SMA100
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
8
REVISION F 04/28/16
9DBV0231 DATASHEET
Additive Phase Jitter Plot: 125M (12kHz to 20MHz)
RMS additve jitter:251fs
REVISION F 04/28/16
9
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
General SMBus Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
written to Byte 8)
(H)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
starT bit
T
Slave Address
Slave Address
WRite
WR
WRite
WR
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Beginning Byte = N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus Address is 1101101x, where x is the
read/write bit.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
10
REVISION F 04/28/16
9DBV0231 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Reserved
Output Enable
Reserved
Output Enable
Type
0
1
Default
1
1
1
1
1
1
1
1
DIF OE1
DIF OE0
RW
RW
Low/Low
Low/Low
Enabled
Enabled
Reserved
Reserved
Reserved
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Bit 7
Bit 6
Name
PLLMODERB1
PLLMODERB0
Control Function
PLL Mode Readback Bit 1
PLL Mode Readback Bit 0
Type
R
R
0
1
Default
Latch
Latch
See PLL Operating Mode Table
Values in B1[7:6]
set PLL Mode
Values in B1[4:3]
set PLL Mode
PLLMODE_SWCNTRL
Enable SW control of PLL Mode RW
0
Bit 5
RW1
RW1
PLLMODE1
PLLMODE0
PLL Mode Control Bit 1
0
0
1
1
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
See PLL Operating Mode Table
PLL Mode Control Bit 0
Reserved
RW
Controls Output Amplitude
RW
AMPLITUDE 1
AMPLITUDE 0
00 = 0.6V
10= 0.8V
01 = 0.7V
11 = 0.9V
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Reserved
Reserved
Slew Rate Selection
Reserved
Slew Rate Selection
Type
0
1
Default
1
1
1
1
1
1
1
1
SLEWRATESEL DIF1
SLEWRATESEL DIF0
RW
RW
Slow setting
Slow setting
Fast setting
Fast setting
Reserved
Reserved
Reserved
SMBus Table: Frequency Select Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Type
0
1
Default
Reserved
Reserved
1
1
Enable SW selection of
frequency
SW frequency
change disabled
SW frequency
change enabled
FREQ_SEL_EN
RW
0
Bit 5
RW1
RW1
FSEL1
FSEL0
Freq. Select Bit 1
0
Bit 4
See Frequency Select Table
Freq. Select Bit 0
Reserved
Reserved
Adjust Slew Rate of FB
0
1
1
1
Bit 3
Bit 2
Bit 1
Bit 0
SLEWRATESEL FB
RW
Slow setting
Fast setting
1. B3[5] must be set to a 1 for these bits to have any effect on the part.
Byte 4 is Reserved and reads back 'hFF
REVISION F 04/28/16
11
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
0
0
0
0
1
Revision ID
A rev = 0000
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx,
10 = DMx, 11= Reserved
0
1
0
0
0
0
1
0
Device Type
Device ID
000100 binary or 02 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
12
REVISION F 04/28/16
9DBV0231 DATASHEET
Marking Diagrams
LOT
LOT
031AL
YYWW
031AIL
YYWW
Notes:
1. “LOT” is the lot sequence number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. Line 2: truncated part number
4. “L” denotes RoHS compliant package.
5. “I” denotes industrial temperature range device.
Thermal Characteristics
TYP
VALUE
62
PARAMETER
SYMBOL
CONDITIONS
PKG
UNITS NOTES
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
C/W
°
Junction to Case
Junction to Base
1
1
1
1
1
1
θJC
θJb
θJA0
θJA1
θJA3
θJA5
5.4
50
43
39
38
Junction to Air, still air
NLG20
NLG24
Thermal Resistance
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
1ePad soldered to board
REVISION F 04/28/16
13
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
Package Outline and Dimensions (NLG24)
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
14
REVISION F 04/28/16
9DBV0231 DATASHEET
Package Outline and Dimensions (NLG24), cont.
REVISION F 04/28/16
15
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
9DBV0231 DATASHEET
Ordering Information
Part / Order Number Shipping Packaging
Package
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
9DBV0231AKLF
9DBV0231AKLFT
9DBV0231AKILF
9DBV0231AKILFT
Tubes
Tape and Reel
Tubes
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
24-pin VFQFPN
Tape and Reel
"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev. Initiator Issue Date Description
Page #
1. Updated electrical characteristics tables.
2. Move to final.
A
RDW
8/13/2012
5-8
1. Changed VIH min. from 0.65*VDD to 0.75*VDD
2. Changed VIL max. from 0.35*VDD to 0.25*VDD
3. Added missing mid-level input voltage spec (VIM) of 0.4*VDD to
0.6*VDD.
B
RDW
9/16/2014
Various
4. Changed Shipping Packaging from "Trays" to "Tubes".
5. Reformatted to new template
1. Updated block diagram with new format showing individual outputs
instead of bussed outputs.
2. Updated pin out and pin descriptions to show ePad on package
connected to ground.
3. Updated front page text to standard format for these devices. Added
explicit bullet indicated Spread Spectrum compatibilty. Changed data
sheet title, etc.
4. Added additive phase jitter plot and updated phase jitter spec table.
1. Replaced "Driving LVDS" with "Alternate Terminations", adding
reference to AN-891.
C
RDW
RDW
4/3/2015
1-4,9
2. Updated "Clock Input Parameters Table" correcting inconsistency with
D
8/10/2015 PCIe SIG specifications.
3. Widened allowable input frequency at each PLL mode frequency.
4,5,6,14
4. Updated NLG24 package drawing with actual package info instead of
generic drawing.
1. Minor typographical corrections throughout the data sheet
2. Updated test load diagram to generic diagram. Length of test load
listed outside the drawing.
3. Minor updates to electrical tables for formatting. Removed Schmitt
trigger info and output high/low voltage specifications for single-ended
outputs, since this part does not have any.
4. "Low-Power HCSL Outputs" table: corrected inversion of slew rate
11/5/2015 setting with specifications. Changed reference from 2 V/ns and 3 V/ns to
slow setting and fast setting. Also change references in SMBus
Bytes[3:2]
Various
,4-8,11
E
RDW
5. "Low-Power HCSL Outputs" table: Removed Vswing parameter since
this is an input parameter and is covered in "Clock Input Parameters"
Table.
6. Reduced current consumption limits.
7. Minor updates to other electrical tables.
1. Updated max frequency of 100MHz PLL mode to 140MHz
4/28/2016 2. Updated max frequency of 125MHz PLL mode to 175MHz
3. Updated max frequency of 50MHz PLL mode to 65MHz
F
RDW
6
2-OUTPUT 1.8V PCIE GEN1/2/3 ZERO DELAY / FANOUT BUFFER
16
REVISION F 04/28/16
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.
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