9FGL6251 [IDT]
Intelligent PCIe Clock Buffer/Generator for SSD;
| 型号： | 9FGL6251 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Intelligent PCIe Clock Buffer/Generator for SSD PC |
| 文件： | 总28页 (文件大小：536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intelligent PCIe Clock
Buffer/Generator for SSD
9FGL6241 / 9FGL6251
Datasheet
Description
Features
▪ Supports single or dual-ported nVME drives
The 9FGL6241 / 9FGL6251 are intelligent buffer/clock generators
tailored for single and dual-ported nVME SSDs. They support
Common (CC) and Independent Reference (IR) clocking
architectures and are ideal for U.2 and M.2 form factors. The
devices are also useful in PCIe master/slave and clock
multiplexing applications, with an internal clock generator as a
third input channel.
▪ Automatically detects presence or absence of input clocks
▪ Integrated terminations on LP-HCSL outputs save 8 resistors
▪ Choice of spread off (0% SRnS) or spread on (-0.5% SRIS)
default
▪ Choice of 25MHz or 33 1/3MHz reference clock
▪ REF clock output; saves external XO
▪ 2.5V to 3.3V operating voltage
Typical Applications
▪ 1.8V compatible, 3.3V tolerant single-ended I/O signaling
▪ Open-drain CC_IR output; maximum system flexibility
▪ 4 × 4 mm 28-VQFP-N package with external crystal
▪ 4 × 4 mm 28-LGA package with optional internal crystal
▪ 1 × 4 and 2 × 2 nVME SSDs
▪ 3:2 PCIe clock multiplexing
Output Features
▪ Two 100MHz Low-Power HCSL (LP-HCSL) outputs with Zo =
100Ω or 85Ω
Key Specifications
▪ DIF cycle-to-cycle jitter < 50ps
▪ One 33 1/3MHz or 25MHz 1.8V LVCMOS REF output
▪ One open drain CC_IR output indicates PCIe clock mode
▪ PCIe Gen1–4 (CC) compliant; Gen2–3 (IR) compliant
Block Diagram
VDDIN[A:B]
OSC
VDDDIG VDDA
VDDO1 VDDREF_1p8
XIN/CLKIN
XO
REFOUT
PLL
DIF0#
DIF0
DIF_INA
DIF_INA#
DIF1#
DIF1
DIF_INB
DIF_INB#
Input
Detect
Logic
vePERst0#
vePERst1#
CC_IR
SCLK_3.3
SMBus Engine
Logic
POR
SDATA_3.3
Factory Configuration
GNDIN[A:B] GNDDIG
EPAD
GNDREF GNDO[0:1]
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Output Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Alternate Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Crystal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Spread Spectrum Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General SMBus Serial Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
How to Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
How to Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 4 × 4 mm NDG28 28-VQFP-N Package – Top View
28 27 26 25 24 23 22
•
GNDINA 1
DIF_INA 2
DIF_INA# 3
VDDINA 4
VDDA
DIF0#
DIF0
21
20
19
18
17
9FGL6241
9FGL6251
GNDO0
GNDO1
5
6
7
VDDINB
DIF_INB
16 DIF1#
15 DIF1
DIF_INB#
8
9 10 11 12 13 14
28-VQFP-N, 4 × 4 mm, 0.4mm pitch
^ prefix indicates internal 120kohm pull-up resistor
v prefix indicates internal 120kohm pull-down resistor
Figure 2. Pin Assignments for 4 × 4 mm LTG28 28-LGA Package – Top View
28 27 26 25 24 23 22
•
GNDINA 1
DIF_INA 2
DIF_INA# 3
VDDINA 4
VDDA
DIF0#
DIF0
21
20
19
18
17
9FGL6241Q
9FGL6251Q
GNDO0
GNDO1
5
6
7
VDDINB
DIF_INB
16 DIF1#
15 DIF1
DIF_INB#
8
9 10 11 12 13 14
28-LGA, 4 × 4 mm, 0.4mm pitch
^ prefix indicates internal 120kohm pull-up resistor
v prefix indicates internal 120kohm pull-down resistor
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
Description
1
2
GNDINA
DIF_INA
DIF_INA#
VDDINA
GND
Input
Input
Ground pin for input A.
True input of differential clock.
Complement input of differential clock.
3
4
Power Power supply for input A.
Power Power supply for input B.
5
VDDINB
6
DIF_INB
DIF_INB#
GNDINB
GNDDIG
VDDDIG
SCLK_3.3
SDATA_3.3
Input
Input
GND
GND
True input of differential clock.
Complement input of differential clock.
Ground pin for input B.
7
8
9
Ground pin for digital circuitry.
10
11
12
Power Digital power.
Input
I/O
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Enterprise PCIe Reset for Port B eSSD drives configured as 2 x 2. This active low signal
indicates when the power supply is within specified voltage limits and is used to reset
internal circuitry. The rising edge is used to determine the clocking mode. It is logically
equivalent to PERST# reset signal. See the PCIe CEM specification for additional details.
13
vePERst1#
Input
14
15
16
17
18
VDDO1
DIF1
Power Power supply for output 1.
Output Differential true clock output.
Output Differential complementary clock output.
DIF1#
GNDO1
GNDO0
GND
GND
Ground pin for output 1.
Ground pin for output 0.
19
DIF0
Output Differential true clock output.
20
21
DIF0#
VDDA
Output Differential complementary clock output.
Power Power supply for PLL core. See Power Connections table for additional information.
Output indicating which mode (CC or IR) is active. Input clocks are present and are being
Open
Drain
directed to the outputs in CC mode. Input clocks are absent and internally generated clocks
are being directed to the outputs in IR mode. This pin is an open drain output and requires
22
23
CC_IR
Output an external pull up resistor for proper functionality. The polarity of this pin is programmable.
Consult the General SMBus Serial Interface Information registers for details.
Enterprise PCIe Reset for Port A eSSD drives configured as 1x4 or 2x2. This active low
signal indicates when the power supply is within specified voltage limits and is used to
reset internal circuitry. The rising edge is used to determine the clocking mode. It is
logically equivalent to PERST# reset signal. See the PCIe CEM specification for additional
details.
vePERst0#
Input
24
25
26
VDDREF_1p8
REFOUT
Power Power supply for XTAL and REF clocks, nominally 1.8V.
Output Reference clock output.
GNDREF
GND
Ground pin for the REF outputs.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
Name
Type
Description
[a]
27
XIN/CLKIN
XO
Input
Crystal input or reference clock input.
[a]
28
Output Crystal output.
GND Connect to ground.
29
EPAD
[a] These pins are no connect (NC) on devices with integrated crystal (9FGL6241Q and 9FGL6251Q).
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 9FGL6241 / 9FGL6251 at absolute maximum ratings is not implied. Exposure to absolute maximum
rating conditions may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Conditions
Minimum Maximum Units Notes
Supply Voltage
Input Voltage
V
4.6
+0.5
V
V
1,2
1,3
1
DDx
V
-0.5
-65
V
IN
DD
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD Protection
V
SMBus clock and data pins.
Human Body Model.
3.9
150
125
V
IHSMB
Ts
°C
°C
V
1
Tj
1
ESD prot
2500
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
Thermal Characteristics
Table 3. Thermal Characteristics
Symbol
Parameter
Package
Typical Values
Units
Notes
θ
Junction to case.
51.4
26.9
68.6
63.5
58.6
56.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
JC
θ
Junction to base.
Jb
θ
θ
θ
θ
Junction to air, still air.
JA0
JA1
JA3
JA5
LTG28
Junction to air, 1 m/s air flow.
Junction to air, 3 m/s air flow.
Junction to air, 5 m/s air flow.
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Table 3. Thermal Characteristics (Cont.)
Symbol Parameter
Package
Typical Values
Units
Notes
θ
Junction to case.
42
2.4
39
33
28
27
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
JC
θ
Junction to base.
Jb
θ
θ
θ
θ
Junction to air, still air.
JA0
JA1
JA3
JA5
NDG28
Junction to air, 1 m/s air flow.
Junction to air, 3 m/s air flow.
Junction to air, 5 m/s air flow.
1 EPAD soldered to board.
Electrical Characteristics
TA = TAMB. Supply voltages per normal operation conditions; see Test Loads for loading conditions.
Table 4. SMBus Parameters
Parameter
Symbol
Conditions
Minimum Typical
Maximum Units Notes
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
V
0.63
3.6
V
V
ILSMB
V
1.17
IHSMB
V
At I
0.4
V
OLSMB
PULLUP
PULLUP.
I
At V
4
mA
V
OL.
Nominal Bus Voltage
V
1.8
3.6
1000
300
DDSMB
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating Frequency
t
(Max. V - 0.15V) to (Min. V + 0.15V).
ns
ns
kHz
1
1
2
RSMB
IL
IH
t
(Min. V + 0.15V) to (Max. V - 0.15V).
FSMB
IH
IL
f
SMBus operating frequency.
400
SMB
1 Guaranteed by design and characterization, not 100% tested in production.
2 The device must be powered up for the SMBus to function.
Table 5. Input/Supply/Common Parameters – Normal Operating Conditions
Parameter
Symbol
Conditions
2.5V supply voltage for all V pins
Minimum
Typical
Maximum
Units Notes
DD
V
V
V
2.375
2.5
3.465
V
DDx2.5
DDx3.3
DDREF
except V
DDREF
3.3V supply voltage for all V pins
DD
Supply Voltage
3.135
1.71
-40
3.3
1.8
3.465
1.89
85
V
V
except V
DDREF
Supply voltage for crystal oscillator and
REFOUT.
Ambient Operating
Temperature
T
Industrial range.
25
°C
AMB
Input High Voltage
Input Low Voltage
V
0.65 x V
-0.3
1.6
V + 0.3
DDx
V
V
4
4
IH
DDx
Single-ended inputs, except SMBus and
XIN/CLKIN.
V
0.35 x V
DDx
IL
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Table 5. Input/Supply/Common Parameters – Normal Operating Conditions (Cont.)
Parameter
Symbol
Conditions
Minimum
0.65 x V
Typical
Maximum
V + 0.3
DDREF
Units Notes
Input High Voltage
Input Low Voltage
V
1.6
V
V
6
IHCLKIN
DDREF
XIN/CLKIN.
V
-0.3
0.35 x V
6
5
ILCLKIN
DDREF
Output High Voltage
Output Low Voltage
V
CC_IR at default polarity.
CC_IR at default polarity.
V
V
V
V
OHCC_IR
DDPU
DDPU
V
0.45
OLCC_IR
Single-ended inputs, V = GND,
IN
I
-5
5
μA
IN
V
= V
IN
DD.
Single-ended inputs.
= 0V; inputs with internal pull-up
Input Current
V
IN
I
resistors.
-50
50
μA
INP
V = V ; inputs with internal pull-down
IN
DD
resistors.
Differential inputs (DIF_IN).
Crystal input or clock input, 3xx devices.
Crystal input or clock input, 2xx devices.
100
33 1/3
25
MHz
MHz
MHz
nH
Input Frequency
Pin Inductance
Capacitance
F
IN
L
7
5
1
1
1
1
pin
C
Logic inputs, except DIF_IN.
DIF_IN differential clock inputs.
Output pin capacitance.
1.5
1.5
pF
IN
INDIF_IN
C
2.7
6
pF
C
pF
OUT
From V power-up and after input
DD
Clk Stabilization
t
clock stabilization or deassertion of PD#
to 1st clock.
1
ms
1,2
STAB
Output SS
Modulation
Frequency
Modulation frequency (triangular
modulation).
f
30
31.6
33
kHz
MOD
DIF output enable after PD#
de-assertion.
Tdrive_PD#
t
300
μs
1,3
DRVPD
Tfall
t
Fall time of single-ended control inputs.
Rise time of single-ended control inputs.
5
5
ns
ns
2
2
F
Trise
t
R
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV.
4 The single-ended control inputs are 1.8V compatible and 3.3V tolerant.
5 The VOH of CC_IR is determined by the external pull-up voltage, since this is an open drain output.
6 When driven by an external clock or XO, it must be AC coupled to the CLKIN pin.
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Table 6. Differential Clock Input Parameters
Parameter
Symbol
Conditions
Cross over voltage.
Minimum
Typical
Maximum Units Notes
Input Crossover Voltage – DIF_IN
Input Swing – DIF_IN
V
150
300
0.4
-5
900
mV
mV
V/ns
μA
1
1
CROSS
V
Differential value.
SWING
Input Slew Rate – DIF_IN
Input Leakage Current
dv/dt
Measured differentially.
8
5
1,2
I
V
= V
V = GND.
DD , IN
IN
IN
Measurement from differential
waveform.
Input Duty Cycle
d
45
0
55
%
1
1
tin
Input Jitter –Cycle to Cycle
J
Differential measurement.
125
ps
DIFIn
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through ±75mV window centered around differential zero.
Table 7. Current Consumption
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
I
V
at 1.8V
DDREF
1.7
37
40
23
25
2.6
47
50
28
31
mA
mA
mA
mA
mA
DD_REF
I
I
I
I
2.5V operation in IR mode, V
3.3V operation in IR mode, V
at 1.8V.
at 1.8V.
DD_VDD2.5
DD_VDD3.3
DD_VDD2.5
DD_VDD3.3
DDREF
DDREF
Operating Supply
Current
2.5V operation in CC mode, V
3.3V operation in CC mode, V
at1.8V.
at 1.8V.
DDREF
DDREF
Table 8. Output Duty Cycle, Jitter, Skew and PLL Characteristics
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Duty Cycle
t
Measured differentially, IR Mode.
Measured differentially, CC Mode.
45
49
-0.3
3962
17
55
0.7
4600
50
%
%
1
DC
Duty Cycle Distortion
Skew, Input to Output
Skew, Output to Output
t
-1.5
3300
1,3
1
DCD
t
Fanout Mode, V = 50%.
ps
ps
ps
ps
pdBYP
T
t
IR Mode, V = 50%.
1,4
1,2
1,2
sk3
T
IR Mode.
20
50
Jitter, Cycle to Cycle
t
jcyc-cyc
Additive jitter in CC Mode.
0.3
10
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform.
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operating in Common Clock Mode.
4 All outputs at default slew rate.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Table 9. DIF Low -Pow er HCSL Outputs
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
dV/dt
dV/dt
Scope averaging on, fast setting.
Scope averaging on, slow setting.
Slew rate matching.
1.3
0.7
2.2
1.5
9
3.2
2.5
20
V/ns 1,2,3
V/ns 1,2,3
Slew Rate
Slew Rate Matching
Voltage High
ΔdV/dt
%
1,4
7
V
Statistical measurement on single-ended
signal using oscilloscope math function
(scope averaging on).
660
778
850
mV
HIGH
Voltage Low
V
-150
-4
150
7
LOW
Max Voltage
Min Voltage
Vmax
Vmin
799
-35
412
29
1150
mV
7
7
Measurement on single-ended signal using
absolute value (scope averaging off).
-300
250
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs Scope averaging off.
Δ-Vcross Scope averaging off.
550
140
mV
mV
1,5
1,6
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a ±150mV window around differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average cross
point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the
edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock
rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed.
The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Table 10. PCIe Filtered Additive Phase Jitter Parameters–Common Clocked (CC) Architectures, 3.3V
Fanout Mode
Industry
Limits
Parameter
Symbol
Conditions
Minimum Typical Maximum
Units Notes
ps
t
t
PCIe Gen1.
0.0
4.5
1,2,5
(p-p)
jphPCIeG1-CC
PCIe Gen2 Low Band
10kHz < f < 1.5MHz
ps
0.01
0.02
1,2,4,5
(rms)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
Additive Phase
Jitter, CC (fanout
buffer) Mode
jphPCIeG2-CC
PCIe Gen2 High Band
ps
1.5MHz < f < Nyquist (50MHz)
0.2
0.31
N/A
1,2,4,5
(rms)
V
= 1.8V
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
DDREF
Other V s =
DD
3.3V
PCIe Gen3
ps
t
t
0.10
0.10
0.19
0.19
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
jphPCIeG3-CC
jphPCIeG4-CC
PCIe Gen4
ps
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Table 11. PCIe Filtered Additive Phase Jitter Parameters–Common Clocked (CC) Architectures, 2.5V
Fanout Mode
Industry
Limits
Parameter
Symbol
Conditions
Minimum Typical Maximum
Units Notes
ps
t
t
PCIe Gen1.
0.7
3.9
1,2,5
(p-p)
jphPCIeG1-CC
PCIe Gen2 Low Band
10kHz < f < 1.5MHz
ps
0.01
0.02
1,2,4,5
(rms)
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
Additive Phase
Jitter, CC (fanout
buffer) Mode
jphPCIeG2-CC
PCIe Gen2 High Band
ps
1.5MHz < f < Nyquist (50MHz)
0.2
0.33
N/A
1,2,4,5
(rms)
V
= 1.8V
(PLL BW of 5–16MHz or 8–16MHz,
CDR = 5MHz).
DDREF
Other V s =
DD
2.5V
PCIe Gen3
ps
t
t
0.12
0.12
0.20
0.20
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
jphPCIeG3-CC
jphPCIeG4-CC
PCIe Gen4
ps
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz).
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev 4.0 version 1.0. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12
.
4 For RMS values additive jitter is calculated by solving the following equation for b [a^2 + b^2 = c^2] where “a” is rms input jitter and “c” is rms total
jitter.
5 Driven by 9FGL0841 or equivalent.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
4,5
Table 12. PCIe Filtered Phase Jitter Parameters–3.3V Clock Generator Mode
Industry
Limits
Parameter
Symbol
Conditions
Minimum Typical Maximum
Units Notes
ps
PCIe Gen1 (Common Clock)
t
t
16
28
86
1,2,5
(p-p)
jphPCIeG1-CC
PCIe Gen2 Lo Band (Common Clock)
10kHz < f < 1.5MHz
ps
0.43
0.55
3
1,2,4,5
(rms)
(PLL BW of 5–16MHz or 8–5MHz,
CDR = 5MHz)
jphPCIeG2-CC
PCIe Gen2 High Band (Common Clock)
1.5MHz < f < Nyquist (50MHz)
SSC on or off,
ps
V
V
= 3.3V,
0.9
1.37
0.38
3.1
1
1,2,4,5
(rms)
DDx
DDREF
(PLL BW of 5–16MHz or 8–5MHz,
CDR = 5MHz)
= 1.8V
PCIe Gen3 (Common Clock)
ps
t
t
0.25
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz)
jphPCIeG3-CC
jphPCIeG4-CC
PCIe Gen4 (Common Clock)
ps
0.25
0.7
0.6
0.7
0.4
0.38
0.81
0.67
0.75
0.44
0.5
2
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz)
PCIe Gen2 (SRIS)
ps
1,2
t
jphPCIeG2-IR
jphPCIeG3-IR
jphPCIeG2-IR
jphPCIeG3-IR
(PLL BW of 16MHz, CDR = 5MHz)
(rms)
-0.5% spread,
V
V
= 3.3V,
DDx
DDREF
PCIe Gen3 (SRIS)
ps
1,2
= 1.8V
t
0.7
2
(PLL BW of 2–4MHz or 2–5MHz,
(rms)
CDR = 10MHz)
PCIe Gen2 (SRIS)
ps
1,2
t
t
(PLL BW of 16MHz, CDR = 5MHz)
(rms)
-0.25% spread,
V
V
= 3.3V,
DDx
DDREF
PCIe Gen3 (SRIS)
ps
1,2
= 1.8V
0.7
(PLL BW of 2–4MHz or 2–5MHz,
(rms)
CDR = 10MHz)
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
4,5
Table 13. PCIe Filtered Phase Jitter Parameters–2.5V Clock Generator Mode
Industry
Limits
Parameter
Symbol
Conditions
Minimum Typical Maximum
Units Notes
ps
PCIe Gen1 (Common Clock)
t
t
17
29
86
1,2,5
(p-p)
jphPCIeG1-CC
PCIe Gen2 Lo Band (Common Clock)
10kHz < f < 1.5MHz
ps
0.44
0.56
3
1,2,4,5
(rms)
(PLL BW of 5–16MHz or 8–5MHz,
CDR = 5MHz)
jphPCIeG2-CC
PCIe Gen2 High Band (Common Clock)
1.5MHz < f < Nyquist (50MHz)
SSC on or off,
ps
V
V
= 2.5V,
1.0
1.5
3.1
1
1,2,4,5
(rms)
DDx
DDREF
(PLL BW of 5–16MHz or 8–5MHz,
CDR = 5MHz)
= 1.8V
PCIe Gen3 (Common Clock)
ps
t
t
0.29
0.41
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz)
jphPCIeG3-CC
jphPCIeG4-CC
PCIe Gen4 (Common Clock)
ps
0.29
0.9
0.41
1.1
0.5
2
1,2,4,5
(rms)
(PLL BW of 2–4MHz or 2–5MHz,
CDR = 10MHz)
PCIe Gen2 (SRIS)
ps
1,2
t
jphPCIeG2-IR
jphPCIeG3-IR
jphPCIeG2-IR
jphPCIeG3-IR
(PLL BW of 16MHz, CDR = 5MHz)
(rms)
-0.5% spread,
V
V
= 2.5V,
DDx
DDREF
PCIe Gen3 (SRIS)
ps
1,2
= 1.8V
t
0.62
0.80
0.42
0.70
1.01
0.49
0.7
2
(PLL BW of 2–4MHz or 2–5MHz,
(rms)
CDR = 10MHz)
PCIe Gen2 (SRIS)
ps
1,2
t
t
(PLL BW of 16MHz, CDR = 5MHz)
(rms)
-0.25% spread,
V
V
= 2.5V,
DDx
DDREF
PCIe Gen3 (SRIS)
ps
1,2
= 1.8V
0.7
(PLL BW of 2–4MHz or 2–5MHz,
(rms)
CDR = 10MHz)
1 Applies to all outputs.
2 Based on PCIe Base Specification Rev3.1a. These filters are different than common clock filters. See http://www.pcisig.com for latest specifications.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12
.
4 As of PCIe Base Specification Rev4.0 version 1.0, IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference
no Spread (SRnS). Industry limits for IR clocking are not specified in the Base Specification; limits are commonly agreed upon with major customers.
5 All outputs at default slew rate (fast).
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
Table 14. REF Output
Parameter
Symbol
Conditions
Minimum Typical Maximum Units Notes
Long Accuracy
Long Accuracy
ppm
ppm
Independent Reference Mode.
Common Clock Mode.
-100
0
100
ppm
ppm
ns
1,2
1,2
2
0
T
25MHz reference input.
40
30
period25M
period33M
Clock Period
T
33 1/3MHz reference input.
Slowest slew rate, 20% to 80% of V
ns
2
t
t
0.5
0.8
0.89
1.5
1.5
1.7
48.2
0.00
52
1.6
2.3
2.3
2.4
55
V/ns
V/ns
V/ns
V/ns
%
1
rf1
rf2
rf3
rf4
t1X
DDREF.
DDREF.
Slow slew rate, 20% to 80% of V
Fast slew rate, 20% to 80% of V
1,3
1
Rise/Fall Slew Rate
t
0.8
DDREF.
t
Fastest slew rate, 20% to 80% of V
1.0
1
DDREF.
Duty Cycle
d
V = V /2 V.
45
1,4
1,5
1,4
T
DD
Duty Cycle Distortion
Jitter, Cycle to Cycle
d
V = V /2 V.
-0.75
0
%
tcd
T
DD
t
V = V /2 V.
250
ps
jcyc-cyc
T
DD
1 Guaranteed by design and characterization, not 100% tested in production.
2 Internal crystal, external crystal may be tuned to 0ppm.
3 Default SMBus value.
4 When driven by a crystal.
5 When driven by an external oscillator via the XIN/CLKIN pin, XO should be floating.
Pow er Management
Table 15. Operating Configuration Table (Byte0, bit 5 = 0)
1,2
ePERst0#
DIF_INA
ePERst1#
DIF_INB
DIF0
DIF1
CC_IR
↑
No clock present
0
X
From PLL
Input A
From PLL
Input B
IR Mode
↑
Clock present
0
X
CC Mode
0
0
X
X
↑
↑
No clock present
Clock present
From PLL
Input A
From PLL
Input B
IR Mode
CC Mode
1 Polarity of CC_IR is determined by Byte3[3].
2 CC_IR Mode is determined by the status of the input clock associated with the first ePERstn# to deassert.
3 Rising arrow indicates first ePERst# to deassert. Once an ePERst# has gone high, the other ePERst# is ignored.
Table 16. Operating Configuration Table (Byte0, bit 5 = 1)
1,2
ePERst0#
DIF_INA
ePERst1#
DIF_INB
DIF0
DIF1
CC_IR
↑
↑
No clock present
Clock present
X
X
X
X
From PLL
Input A
From PLL
Input A
IR Mode
CC Mode
1 Polarity of CC_IR is determined by Byte3[3].
2 When set to 1, the device only responds to DIF_INA and ePERst0#. ePERst1# must remain low and never deassert.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
X
Table 17. SMBus Address
Address
+ Read/Write Bit
1101000
X
Table 18. Pow er Connections
Pin Number
V
GND
Description
DD
4
1
8
DIF_INA
DIF_INB
5
10
14
21
24
9
Digital Power, SMBus
DIF1
17
18
25
DIF0, PLL analog
XTAL, REF
Timing Diagrams
Figure 3. Independent Reference Clock Mode from ePERst0# Deassertion
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Figure 4. Common Clock Mode from ePERst0# Deassertion
Clocking Mode set here
Common (pass through) or IR (clocks from internal PLL).
Here we are in Common Mode– DIF_INA present
VDD
REFOUT
ePERst0#
DIF0
<< 1.8ms
= 100ms
= 100us
< 1.8ms
Sourced from PLL
2-3 clks
2-3 clks
Input Clock from Port A
Sourced from PLL
DIF_INA
DIF1
DIF1 follows DIF_INB
ePERst1# never presents rising edge
No Input Clock from Port B
Which is not running in this case
ePERst1#
DIF_INB
CC_IR1
1. CC_IR at default polarity
Figure 5. Common Clock Mode from ePERst1# Deassertion
Clocking Mode set here, first rising edge of ePERst0# OR ePERst1#
Common(pass through) or IR (clocks from internal PLL).
Here we are in Common clock mode – DIF_INB present
VDD
REFOUT
ePERst0#
DIF0
<< 1.8ms
ePERst0# occurs AFTER ePERst1#, so clock mode
determination is made on rising edge of ePERst1#
< 1.8ms
Sourced from PLL
2-3 clks
2-3 clks
Input Clock from Port A
Sourced from PLL
DIF_INA
DIF1
ePERst1# rising edge occurs before
ePERst0# rising edge.
DIF1 now follows DIF_INB and DIF0
now follows DIF_INA. The PLL is
powered down after the switchover
= 100ms
= 100us
ePERst1#
DIF_INB
Input Clock from Port B
1
CC_IR
1. CC_IR at default polarity
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Test Loads
Figure 6. LVCMOS AC/DC Test Load
Test
Point
L
Zo
Rs
CL
Figure 7. LP-HCSL AC/DC Test Load (standard PCIe source-terminated test load)
Rs
CL
L
Test
Points
Differential Zo
CL
Rs
Figure 8. Test Setup for PCIe Jitter Measurements
Real Time Scope (20Gs/sec)
SMA
Connectors
Rs
Coax
Cables
L
Differential Zo
0.1µF
50
50
Rs
Table 19. Terminations
Device
L (inches)
Zo (Ω)
Rs (Ω)
LVCMOS C (pF) LP-HCSL C (pF)
L L
9FGL6241
9FGL6251
9FGL6251
10
10
10
100
100
85
None needed
7.5
4.7
2
None needed
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
“Universal” Low-Power HCSL Outputs” for details.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Crystal Characteristics
Table 20. Recommended Crystal Characteristics
Parameter
Value
Units
Frequency
Resonance Mode
25MHz or 33 1/3MHz
MHz
Fundamental
—
Frequency Tolerance @ 25°C
Frequency Stability, reference at 25°C over operating temperature range
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
±20
±20
-40–85
50
ppm maximum
ppm maximum
°C
Ω maximum
pF maximum
pF maximum
mW maximum
ppm maximum
7
Load Capacitance (CL)
6
Drive Level
0.3
±5
Aging per year
Spread Spectrum Selection
Table 21. Spread Spectrum Selection for 201 and 301 Configurations
Byte 1[4:3]
Description
Spread Amount
Notes
00
01
10
11
SRnS Mode
CC Mode
0
Default configuration at power up.
Accessible via SMBus.
0
CC/SRIS Mode
CC/SRIS Mode
-0.25%
-0.50%
Accessible via SMBus.
Accessible via SMBus.
The 201/301 devices are designed for Separate Reference clock No Spread applications. They power up in a special mode for this
application (configuration 00). Using the SMBus to change to one of the other configurations will require a system reset. Transitioning
back to configuration 00 from one of the other configurations will also require a system reset. Contact the factory if a different default
configuration set is desired.
Table 22. Spread Spectrum Selection for 202 and 302 Configurations
Byte 1[4:3]
Description
Spread Amount
Notes
00
01
10
11
Reserved
CC Mode
0
Reserved.
0
Accessible via SMBus.
CC/SRIS Mode
CC/SRIS Mode
-0.25%
-0.50%
Accessible via SMBus.
Default configuration at power up.
The 202/302 devices are configured for Common Clock/Separate Reference clock Independent Spread applications. They power up in
configuration 11. The SMBus may be used to change cleanly between configuration 01 or 10 without requiring a system reset. Contact
the factory if a different default configuration set is desired.
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
General SMBus Serial Interface Information
How to Write
How to Read
▪ Controller (host) sends a start bit
▪ Controller (host) will send a start bit
▪ Controller (host) sends the write address
▪ IDT clock will acknowledge
▪ Controller (host) sends the write address
▪ IDT clock will acknowledge
▪ Controller (host) sends the beginning byte location = N
▪ IDT clock will acknowledge
▪ Controller (host) sends the beginning byte location = N
▪ IDT clock will acknowledge
▪ Controller (host) sends the byte count = X
▪ IDT clock will acknowledge
▪ Controller (host) will send a separate start bit
▪ Controller (host) sends the read address
▪ IDT clock will acknowledge
▪ Controller (host) starts sending Byte N through Byte N+X-1
▪ IDT clock will acknowledge each byte one at a time
▪ Controller (host) sends a stop bit
▪ IDT clock will send the data byte count = X
▪ IDT clock sends Byte N+X-1
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to
Index Block Write Operation
Byte 8)
Controller (Host)
starT bit
IDT (Slave/Receiver)
▪ Controller (host) will need to acknowledge each byte
▪ Controller (host) will send a not acknowledge bit
▪ Controller (host) will send a stop bit
T
Slave Address
WR WRite
ACK
ACK
ACK
ACK
Index Block Read Operation
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
Controller (Host)
starT bit
IDT (Slave/Receiver)
T
Slave Address
WRite
WR
ACK
ACK
Beginning Byte = N
O
O
O
O
O
O
RT
RD
Repeat starT
Slave Address
ReaD
Byte N + X - 1
ACK
ACK
P
stoP bit
Data Byte Count=X
Beginning Byte N
ACK
ACK
Note: See Ordering Information for additional details on bits
labeled “OTP Configured”.
O
O
O
O
O
O
Byte N + X - 1
N
P
Not acknowledge
stoP bit
©2018 Integrated Device Technology, Inc.
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October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
SMBus Table: Output Enable and Status Readback Register
Byte 0
Name
Control Function
Type
0
1
Default
DIF_INA not
running
Bit 7
DIF_INA Status
Presence of DIF_INA
R
DIF_INA running
Real Time2
DIF_INB not
running
Bit 6
Bit 5
DIF_INB Status
Presence of DIF_INB
R
DIF_INB running
Real Time2
0
DIFN_INA only
RW drives DIF0 in CC
Mode
DIF_INA drives
both DIF[1:0] in
CC Mode
1x4 CC Mode
Configuration3
Allows DIF_INA to drive both DIF0
and DIF1 in CC mode
Pull-down
disabled
Pull-down
enabled
Bit 4
Bit 3
Bit 2
ePERst1# PD_ EN
ePERst0# PD_EN
Enable pull-down on ePERst1#
Enable pull-down on ePERst0#
Specifies input frequency
RW
1
1
Pull-down
disabled
Pull-down
enabled
RW
Part Number
Dependent
Reference Frequency
RW
25MHz
33 1/3MHz
Bit 1
Bit 0
DIF1 OE
DIF0 OE
Output Enable
Output Enable
RW
RW
Disabled1
Disabled1
Enabled
Enabled
1
1
1 The disabled state depends on Byte2[3:2]. '00' = Low, '01' = HiZ, '10' = Low, '11' = High.
2 The state of both of these inputs at the time of the first rising edge of ePERst0# or ePERst1# determines the operating mode of the device.
3 Setting this bit to ‘1’, allows the device to drive both DIF0 and DIF1 from DIF_INA in Common Clock mode. When set to ‘1’, the device only responds
to DIF_INA and ePERst0#. ePERst1# must remain low and never deassert.
SMBus Table: Spread Spectrum and VHIGH Control Register
Byte 1
Name
Control Function
Type
0
1
Default
Common Clock
Mode
Independent
RefClk Mode
Bit 7
CC_IR Status1
CC-IR Readback
R
Latched
Common Clock
Mode
Independent
RefClk Mode
Bit 6
Bit 5
CC_IR_Mode Override2
CC_IR_Override_Enable
Forces desired CC_IR Mode
RW
RW
0
0
Byte1, bit 6
controls CC_IR
Mode
Enable SW override of CC_IR
Mode
CC_IR controlled
by ePERst logic
Spread Spectrum
Default[1]3
Bit 4
Bit 3
Spread Spectrum default
RW
RW
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11' = -0.5% SS
Part Number
Dependent
Spread Spectrum
Default[0]3
Bit 2
Bit 1
Bit 0
Reserved
X
1
0
DIF Amplitude[1]
DIF Amplitude[0]
RW
RW
00 = 0.6V
01 = 0.68V
11 = 0.85V
Controls output amplitude
10 = 0.75V
1 This bit is indicates the state of the input clock (operating mode) associated with the first ePERst# signal to deassert and is latched upon its
deassertion.
2 Byte 1, bit 5 must be set to '1' for this bit to control operation of the part.
3 Setting this bit to ‘1’, allows the device to drive both DIF0 and DIF1 from DIF_INA in Common Clock mode. When set to ‘1’, the device only responds
to DIF_INA and ePERst0#. ePERst1# must remain low and never de-assert.
©2018 Integrated Device Technology, Inc.
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9FGL6241 / 9FGL6251 Datasheet
SMBus Table: Slew Rate and Output Configuration Register
Byte 2
Name
Control Function
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIF[1]_IMP_1
DIF[1]_IMP_0
RW
RW
RW
RW
RW
RW
RW
RW
ZOUT: 00 = 33Ω ZOUT: 10 = 100Ω
ZOUT: 01 = 85Ω 11 = Reserved
ZOUT: 00 = 33Ω ZOUT: 10 = 100Ω
Differential output 1 impedance[a]
Part Number
Dependent
DIF[0]_IMP_1
Differential output 0 impedance[a]
DIF[0]_IMP_0
ZOUT: 01 = 85Ω
00 = Low/Low
01 = HiZ/HiZ
Slow setting
11 = Reserved
10 = High/Low
11 = Low/High
Fast setting
STOP_STOP[1]
STOP_STATE[0]
DIF1 SLEW RATE SEL
DIF0 SLEW RATE SEL
Output stop state
00
(True/Complement)
Adjust slew rate of DIF1
Adjust slew rate of DIF0
1
1
Slow setting
Fast setting
[a] 9FGL624x devices default to '10' (100Ω). 9FGL625x devices default to '01' (85Ω).
SMBus Table: REF and Polarity Control Register
Byte 3
Name
Control Function
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
RW
RW
00 = Slowest
01 = Slow
0
1
X
1
REF Slew Rate
Slew rate control
10 = Fast
11 = Fastest
Reserved
RW
REF OE
REF output enable
Disabled[a]
Enabled
Low when input detected
(Common Mode)
Low when Input is NOT
detected (IR Mode)
Bit 3
CC_IR POLARITY
Determines CC_IR polarity
RW
1
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
X
X
X
[a] The disabled state depends on Byte2[3:2]. '00' = Low, '01' = HiZ, '10' = Low, '11' = High.
SMBus Table: Reserved Register
Byte 4
Name
Control Function
Reserved
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 4 is reserved and reads back 'hFF'.
©2018 Integrated Device Technology, Inc.
20
October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
SMBus Table: Revision and Vendor ID Register
Byte 5
Name
Control Function
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
R
R
R
R
R
R
R
R
0
0
0
1
0
0
0
1
1st silicon = 0000
A revision = 0001
Revision ID
VENDOR ID
0001 = IDT
SMBus Table: Device Type/Device ID
Byte 6
Name
Control Function
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
1
1
x
0
0
Device with external crystal in NDG28 = 1C hex
Device with internal crystal in LTG28 = 18 hex
Device ID
SMBus Table: Byte Count Register
Byte 7
Name
Control Function
Type
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
0
0
0
0
1
0
0
0
Reserved
Reserved
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
Writing to this register will configure
how many bytes will be read back,
default is = 8 bytes.
Byte count programming
©2018 Integrated Device Technology, Inc.
21
October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Package Outline Draw ings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/ndndg28-package-outline-40-x-40-x-09-mm-body-vqpf-n-04-mm-ball-pitch
www.idt.com/document/psc/ltg28-package-outline-40-x-40-mm-body-04-mm-pitch-lga
Marking Diagrams
▪ Line 1 and 2 (Line 1 only on VQFP-N devices) is the truncated part
number.
L6241
▪ “xxx” denotes dash code (201, 202, 301, 302)
4AxxxI
AQxxx
▪ “YWW” or “YYWW” is the last digit(s) of the year and work-week that the
YYWW$
YWW**$
part was assembled.
▪ “**” denotes sequential lot number.
▪ “$” denotes mark code.
(for 9FGL6241
(for 9FGL6241
28-LGA devices)
28-VQFP-N devices)
L6251
AQxxx
YWW**$
5AxxxI
YYWW$
(for 9FGL6251
(for 9FGL6251
28-LGA devices)
28-VQFP-N devices)
©2018 Integrated Device Technology, Inc.
22
October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Ordering Information
Table 23. Ordering Information
Orderable Part Number
Crystal/XO
IR Spread Mode
DIF ZOUT
Package
Carrier Type
Temperature
9FGL6241AQ201LTGI
9FGL6241AQ201LTGI8
9FGL6241AQ202LTGI
9FGL6241AQ202LTGI8
9FGL6241AP201NDGI
9FGL6241AP201NDGI8
9FGL6241AP202NDGI
9FGL6241AP202NDGI8
9FGL6241AQ301LTGI
9FGL6241AQ301LTGI8
9FGL6241AQ302LTGI
9FGL6241AQ302LTGI8
9FGL6241AP301NDGI
9FGL6241AP301NDGI8
9FGL6241AP302NDGI
9FGL6241AP302NDGI8
9FGL6251AQ201LTGI
9FGL6251AQ201LTGI8
9FGL6251AQ202LTGI
9FGL6251AQ202LTGI8
9FGL6251AP201NDGI
9FGL6251AP201NDGI8
9FGL6251AP202NDGI
9FGL6251AP202NDGI8
9FGL6251AQ301LTGI
9FGL6251AQ301LTGI8
9FGL6251AQ302LTGI
9FGL6251AQ302LTGI8
9FGL6251AP301NDGI
9FGL6251AP301NDGI8
9FGL6251AP302NDGI
9FGL6251AP302NDGI8
Trays
Tape and Reel
Trays
SSC off (SRNS)
25MHz
internal
28-LGA
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
SSC off (SRNS)
SSC on (SRIS)
Tape and Reel
Trays
Tape and Reel
Trays
25MHz
external
28-VQFP-N
28-LGA
Tape and Reel
Trays
100Ω
Tape and Reel
Trays
33 1/3MHz
internal
Tape and Reel
Trays
Tape and Reel
Trays
33 1/3MHz
external
28-VQFP-N
28-LGA
Tape and Reel
Trays
-40° to +85°C
Tape and Reel
Trays
25MHz
internal
Tape and Reel
Trays
Tape and Reel
Trays
25MHz
external
28-VQFP-N
28-LGA
Tape and Reel
Trays
85Ω
Tape and Reel
Trays
33 1/3MHz
internal
Tape and Reel
Trays
Tape and Reel
Trays
33 1/3MHz
external
28-VQFP-N
Tape and Reel
“G” indicates RoHS 6 of 6 compliant.
©2018 Integrated Device Technology, Inc.
23
October 11, 2018
9FGL6241 / 9FGL6251 Datasheet
Revision History
Revision Date
Description of Change
October 11, 2018
Initial release.
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2018 Integrated Device Technology, Inc.
24
October 11, 2018
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