9FGU0831AKILFT [IDT]
Processor Specific Clock Generator, 100MHz, CMOS, 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, VFQFPN-48;
| 型号： | 9FGU0831AKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 100MHz, CMOS, 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, VFQFPN-48 时钟 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator
9FGU0831
DATASHEET
General Description
Features/Benefits
The 9FGU0831 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
• LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
• 50mW typical power consumption; reduced thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
Recommended Application
• 1.5V PCIe Gen1-2-3 Clock Generator
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning for
various line length
Output Features
• 8 - 100MHz Low-Power (LP) HCSL DIF pairs
• Programmable output amplitude; allows tuning for various
application environments
• 1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EM
Key Specification
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew < 60ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• REF phase jitter is < 3.0ps RMS
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
Functional Block Diagram
vOE(7:0)#
REF1.5
XIN/CLKIN_25
OSC
DIF7
DIF6
X2
DIF5
SS Capable PLL
DIF4
vSADR
DIF3
DIF2
DIF1
vSS_EN_tri
CONTROL
LOGIC
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF0
9FGU0831 OCTOBER 18, 2016
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©2016 Integrated Device Technology, Inc.
9FGU0831 DATASHEET
Pin Configuration
48 47 46 45 44 43 42 41 40 39 38 37
vSS_EN_tri 1
GNDXTAL 2
XIN/CLKIN_25 3
X2 4
36 DIF5#
35 DIF5
34 vOE4#
33 DIF4#
32 DIF4
5
6
VDDXTAL1.5
VDDREF1.5
31 VDDIO
30 VDDA1.5
29 GNDA
28 vOE3#
27 DIF3#
26 DIF3
9FGU0831
vSADR/REF1.5 7
GNDREF 8
GNDDIG 9
SCLK_3.3 10
SDATA_3.3 11
12
25 vOE2#
VDDDIG1.5
13 14 15 16 17 18 19 20 21 22 23 24
48-pin VFQFPN, 6x6 mm, 0.4mm pitch
vv prefix indicates internal 60KOhm pull down resistor
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
Power Management Table
SMBus
CKPWRGD_PD#
OE bit
DIFx
True O/P
Low
REF
OEx#
Comp. O/P
Hi-Z1
Running Running
Low Low
0
1
1
X
1
0
X
0
1
Low
Running
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRGD_PD# is low, REF is Low.
SMBus Address Selection Table
+
Read/Write Bit
SADR
Address
1101000
1101010
x
x
State of SADR on first application
of CKPWRGD_PD#
0
1
Power Connections
Pin Number
Description
VDD
VDDIO
GND
5
6
2
8
XTAL OSC
REF Power
Digital (dirty)
Power
12
9
13,21,31,39,
47
20,38
30
22,29,40 DIF outputs
29 PLL Analog
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
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OCTOBER 18, 2016
9FGU0831 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
LATCHED Latched select input to select spread spectrum amount at initial power up :
1
vSS_EN_tri
IN
GND
IN
OUT
PWR
PWR
LATCHED
I/O
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND for XTAL
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
2
3
4
5
6
GNDXTAL
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
Power supply for XTAL, nominal 1.5V
VDD for REF output. nominal 1.5V.
7
vSADR/REF1.5
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
8
9
GNDREF
GNDDIG
GND
GND
IN
I/O
PWR
PWR
Ground pin for the REF outputs.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
1.5V digital power (dirty power)
10 SCLK_3.3
11 SDATA_3.3
12 VDDDIG1.5
13 VDDIO
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominally 1.5V
Power supply for differential outputs
14 vOE0#
IN
15 DIF0
16 DIF0#
OUT
OUT
17 vOE1#
IN
18 DIF1
OUT
OUT
PWR
PWR
GND
OUT
OUT
19 DIF1#
20 VDD1.5
21 VDDIO
22 GND
23 DIF2
Ground pin.
Differential true clock output
24 DIF2#
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Ground pin for the PLL core.
25 vOE2#
IN
26 DIF3
27 DIF3#
OUT
OUT
28 vOE3#
IN
29 GNDA
30 VDDA1.5
31 VDDIO
32 DIF4
GND
PWR
PWR
OUT
OUT
1.5V power for the PLL core.
Power supply for differential outputs
Differential true clock output
33 DIF4#
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominally 1.5V
34 vOE4#
IN
35 DIF5
36 DIF5#
OUT
OUT
37 vOE5#
IN
38 VDD1.5
39 VDDIO
PWR
PWR
Power supply for differential outputs
OCTOBER 18, 2016
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8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
Pin Descriptions (cont.)
PIN #
40 GND
41 DIF6
42 DIF6#
PIN NAME
TYPE
GND
OUT
OUT
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
46 vOE7#
47 VDDIO
IN
PWR
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
48 ^CKPWRGD_PD#
IN
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
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OCTOBER 18, 2016
9FGU0831 DATASHEET
Test Loads
Low-Power Differential Output Test Load
5 inches
Rs
Zo=100ohms
2pF
2pF
Rs
Device
Alternate Differential Output Terminations
Rs
33
27
Zo
100
85
Units
Ohms
REF Output Test Load
Zo = 50 ohms
33
5pF
Device
Alternate Terminations
3.3 Volts
R7b
Driving LVDS
R7a
Cc
Zo
Rs
Rs
Cc
R8a
R8b
Device
LVDS CLK
Input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
R7a, R7b
R8a, R8b
Cc
termination
10K ohm
5.6K ohm
0.1 uF
have termination Note
140 ohm
75 ohm
0.1 uF
Vcm
1.2 volts
1.2 volts
OCTOBER 18, 2016
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8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0831. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
UNITS NOTES
MIN
-0.5
-0.5
TYP
MAX
2
VDD+0.5V
Supply Voltage
Input Voltage
VDDxx
VIN
Applies to all VDD pins
V
V
1,2
1,3
Input High Voltage, SMBus
VIHSMB
Ts
Tj
SMBus clock and data pins
3.3V
150
125
V
1
1
1
1
Storage Temperature
Junction Temperature
Input ESD protection
-65
°C
°C
V
ESD prot
Human Body Model
2000
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
Electrical Characteristics – Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
IDDAOP
CONDITIONS
MIN
TYP MAX UNITS NOTES
VDDA, All outputs active @100MHz
6.1
9
mA
All VDD, except VDDA and VDDIO, All outputs
active @100MHz
Operating Supply Current
IDDOP
9.2
14
mA
IDDIOOP
IDDAPD
VDDIO, All outputs active @100MHz
26
38
1
mA
mA
VDDA, DIF outputs off, REF output running
All VDD, except VDDA and VDDIO,
DIF outputs off, REF output running
VDDIO, DIF outputs off, REF output running
0.4
2
2
2
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
IDDPD
4.4
7
mA
IDDIOPD
IDDAPD
IDDPD
0.04
0.4
0.1
1
mA
mA
mA
mA
VDDA, all outputs off
All VDD, except VDDA and VDDIO, all outputs off
VDDIO, all outputs off
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
0.4
1
IDDIOPD
0.0003 0.1
1 Guaranteed by design and characterization, not 100% tested in production.
2 This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics – DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
45
TYP MAX UNITS NOTES
Duty Cycle
tDC
tsk3
Measured differentially, PLL Mode
Averaging on, VT = 50%
50
32
16
55
60
50
%
ps
ps
1,2
1
Skew, Output to Output
Jitter, Cycle to cycle
tjcyc-cyc
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
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OCTOBER 18, 2016
9FGU0831 DATASHEET
Electrical Characteristics – Input/Supply/Common Parameters - Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
TYP
1.5
MAX
UNITS NOTES
V
Supply voltage for core, analog and single-ended
LVCMOS outputs
Supply voltage for differential Low Power Outputs
Comercial range
VDDxx
VDDIO
TAMB
1.425
1.575
Output Supply Voltage
Ambient Operating
Temperature
0.9975
0
1.05-1.5
25
1.575
70
V
°C
°C
V
Industrial range
-40
25
85
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VIH
VIM
VIL
VIH
VIL
IIN
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
0.75 VDD
0.4 VDD
-0.3
VDD + 0.3
0.5 VDD 0.6 VDD
0.25 VDD
V
V
Single-ended outputs, except SMBus. IOH = -2mA VDD-0.45
Single-ended outputs, except SMBus. IOL = -2mA
V
0.45
5
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
IN = 0 V; Inputs with internal pull-up resistors
IN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
-5
-200
23
uA
Input Current
V
IINP
200
uA
V
Input Frequency
Pin Inductance
Fin
Lpin
25
27
7
MHz
nH
pF
pF
1
1
1
CIN
Logic Inputs, except DIF_IN
Output pin capacitance
1.5
5
Capacitance
COUT
6
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Triangular Modulation
Clk Stabilization
TSTAB
1.8
ms
1,2
SS Modulation Frequency
OE# Latency
fMOD
30
1
31.6
33
3
kHz
1
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
tLATOE#
clocks
1,3
Tdrive_PD#
tDRVPD
300
us
1,3
PD# de-assertion
Tfall
tF
Fall time of single-ended control inputs
5
ns
ns
V
2
2
Trise
tR
Rise time of single-ended control inputs
5
SMBus Input Low Voltage
SMBus Input High Voltage
VILSMB
VIHSMB
0.6
3.3
0.4
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
2.1
V
4
SMBus Output Low Voltage VOLSMB
@ IPULLUP
@ VOL
V
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
IPULLUP
VDDSMB
tRSMB
4
mA
V
1.425
3.3
1000
300
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
ns
ns
1
1
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
Maximum SMBus operating frequency
400
kHz
1
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
OCTOBER 18, 2016
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8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
Electrical Characteristics – DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
V/ns
V/ns
%
Scope averaging on fast setting
Scope averaging on slow setting
Slew rate matching, Scope averaging on
1.1
0.9
2.2
1.7
3
3.3
2.6
20
1,2,3
1,2,3
1,2,4
Slew rate
Trf
Slew rate matching
Voltage High
Trf
Δ
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
VHIGH
VLOW
600
735
-16
850
7
7
mV
Voltage Low
-150
150
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Vmax
Vmin
Vswing
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
779
-45
1503
405
12
1150
7
7
mV
-300
300
250
mV
mV
mV
1,2,7
1,5,7
1,6,7
Vcross_abs
Scope averaging off
550
140
Crossing Voltage (var)
-Vcross
Scope averaging off
Δ
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Δ
7 At default SMBus amplitude settings.
Electrical Characteristics – DIF Output Phase Jitter Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
IND.
LIMIT
86
PARAMETER
SYMBOL
tjphPCIeG1
CONDITIONS
MIN
TYP MAX
UNITS Notes
ps (p-p) 1,2,3,5
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
27.7
1.0
40
ps
1.3
3
3.1
1
1,2,3,5
(rms)
tjphPCIeG2
PCIe Gen 2 High Band
ps
2.2
0.6
1.9
0.4
1,2,3,5
(rms)
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
Phase Jitter, PLL Mode
ps
tjphPCIeG3
1,2,3,5
(rms)
tjphPCIeG3SRn
PCIe Gen 3 Separate Reference No Spread (SRnS)
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
ps
0.6
0.7
0.4
1,2,3,5
(rms)
S
1 Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Calculated from Intel-supplied Clock Jitter Tool
5 Applies to all differential outputs
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
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OCTOBER 18, 2016
9FGU0831 DATASHEET
Electrical Characteristics – REF
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Long Accuracy
SYMBOL
ppm
CONDITIONS
see Tperiod min-max values
MIN
TYP
0
MAX
UNITS Notes
ppm
1,2
Clock period
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Rise/Fall Slew Rate
Duty Cycle
Tperiod
trf1
25 MHz output
40
0.7
1.0
1.3
1.4
47.1
2
ns
2
Byte 3 = 1F, 20% to 80% of VDDREF
Byte 3 = 5F, 20% to 80% of VDDREF
Byte 3 = 9F, 20% to 80% of VDDREF
Byte 3 = DF, 20% to 80% of VDDREF
VT = VDD/2 V
0.3
0.5
0.77
0.84
45
1.1
1.6
1.9
2.0
55
V/ns
V/ns
V/ns
V/ns
%
1
trf1
1,3
1
trf1
trf1
1
dt1X
dtcd
1,4
1,5
Duty Cycle Distortion
VT = VDD/2 V, when driven by XIN/CLKIN_25 pin
0
4
%
Jitter, cycle to cycle
Noise floor
tjcyc-cyc
tjdBc1k
VT = VDD/2 V
1kHz offset
51.2
-126
-139
250
-105
-110
ps
1,4
1,4
1,4
dBc
Noise floor
tjdBc10k
10kHz offset to Nyquist
dBc
ps
(rms)
Jitter, phase
tjphREF
12kHz to 5MHz
1.11
3
1,4
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to 25.00 MHz
3 Default SMBus Value
4 When driven by a crystal.
5 X2 should be floating.
Clock Periods - Differential Outputs with Spread Spectrum Disabled
Measurement Window
1 Clock
1us
-SSC
0.1s
- ppm
0.1s
0.1s
+ ppm
Long-Term Short-Term
Average
Max
1us
+SSC
1 Clock
Center
Freq.
MHz
SSC OFF
-c2c jitter
AbsPer
Min
0 ppm
Period
Nominal
+c2c jitter Units Notes
AbsPer
Max
Short-Term Long-Term
Average
Min
Average
Min
Average
Max
DIF
100.00
9.94900
9.99900
10.00000
10.00100
10.05100
ns
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
Measurement Window
1 Clock
1us
-SSC
0.1s
- ppm
0.1s
0.1s
+ ppm
Long-Term Short-Term
Average
Max
1us
+SSC
1 Clock
Center
Freq.
MHz
SSC ON
-c2c jitter
AbsPer
Min
0 ppm
Period
Nominal
+c2c jitter Units Notes
AbsPer
Max
Short-Term Long-Term
Average
Min
Average
Min
Average
Max
DIF
99.75
9.94906
9.99906
10.02406
10.02506
10.02607
10.05107
10.10107
ns
1,2
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is trimmed to
25.00 MHz
OCTOBER 18, 2016
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8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
General SMBUS Serial Interface Information
How to Write
How to Read
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
• IDT clock sends Byte 0 through Byte X (if X was
written to Byte 8)
(H)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Index Block Read Operation
Controller (Host)
starT bit
Slave Address
WR WRite
IDT (Slave/Receiver)
Controller (Host)
T starT bit
IDT (Slave/Receiver)
T
Slave Address
WR
WRite
ACK
ACK
ACK
ACK
ACK
ACK
Beginning Byte = N
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address
ReaD
RD
ACK
O
O
O
O
O
O
Data Byte Count=X
Beginning Byte N
ACK
ACK
Byte N + X - 1
ACK
O
O
O
P
stoP bit
O
O
O
Note: SMBus address is Latched on SADR pin.
Byte N + X - 1
N
P
Not acknowledge
stoP bit
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
10
OCTOBER 18, 2016
9FGU0831 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF OE7
DIF OE6
DIF OE5
DIF OE4
DIF OE3
DIF OE2
DIF OE1
DIF OE0
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Low/Low
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
1
1
1
1
1
1
1
1
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: SS Readback and Control Register
Byte 1
Bit 7
Bit 6
Name
SSENRB1
SSENRB1
Control Function
SS Enable Readback Bit1
SS Enable Readback Bit0
Type
R
R
0
1
Default
Latch
Latch
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
Values in B1[7:6] Values in B1[4:3]
control SS amount control SS amount.
SSEN_SWCNTRL
Enable SW control of SS
RW
0
Bit 5
RW1
RW1
SSENSW1
SSENSW0
SS Enable Software Ctl Bit1
SS Enable Software Ctl Bit0
Reserved
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
0
Bit 4
0
1
1
0
Bit 3
Bit 2
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
RW
RW
00 = 0.55V
10= 0.7V
01 = 0.65V
11 = 0.8V
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
SLEWRATESEL DIF7
SLEWRATESEL DIF6
SLEWRATESEL DIF5
SLEWRATESEL DIF4
SLEWRATESEL DIF3
SLEWRATESEL DIF2
SLEWRATESEL DIF1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF7
Adjust Slew Rate of DIF6
Adjust Slew Rate of DIF5
Adjust Slew Rate of DIF4
Adjust Slew Rate of DIF3
Adjust Slew Rate of DIF2
Adjust Slew Rate of DIF1
Adjust Slew Rate of DIF0
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Slow Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
Fast Setting
1
1
1
1
1
1
1
1
SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register
Byte 3
Bit 7
Bit 6
Name
Control Function
Type
RW
RW
0
1
Default
00 = Slowest
10 = Fast
01 = Slow
11 = Faster
0
1
REF
Slew Rate Control
REF does not run in REF runs in Power
REF Power Down Function
REF OE
Wake-on-Lan Enable for REF
RW
RW
0
Bit 5
Power Down
Low
Down
Enabled
REF Output Enable
Reserved
1
1
1
1
1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Byte 4 is Reserved
OCTOBER 18, 2016
11
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
0
0
0
1
0
0
0
1
Revision ID
C rev = 0001
0001 = IDT
VENDOR ID
SMBus Table: Device Type/Device ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
Device Type1
Device Type0
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
00 = FGx, 01 = DBx ZDB/FOB,
10 = DMx, 11= DBx FOB
0
0
0
0
1
0
0
0
Device Type
Device ID
001000 binary or 08 hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
BC4
BC3
BC2
BC1
BC0
RW
RW Writing to this register will configure how
RW many bytes will be read back, default is
RW
RW
Byte Count Programming
= 8 bytes.
Recommended Crystal Characteristics (3225 package)
PARAMETER
VALUE
UNITS
NOTES
Frequency
Resonance Mode
25
Fundamental
±20
MHz
-
PPM Max
1
1
1
Frequency Tolerance @ 25°C
Frequency Stability, ref @ 25°C Over
Operating Temperature Range
Temperature Range (commerical)
Temperature Range (industrial)
Equivalent Series Resistance (ESR)
±20
PPM Max
1
0~70
-40~85
50
°C
°C
Ω Max
1
2
1
Shunt Capacitance (CO)
Load Capacitance (CL)
7
8
pF Max
pF Max
1
1
Drive Level
Aging per year
0.3
±5
mW Max
PPM Max
1
1
Notes:
1. FOX 603-25-150.
2. For I-temp, FOX 603-25-261.
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
12
OCTOBER 18, 2016
9FGU0831 DATASHEET
Thermal Characteristics
PARAMETER
SYMBOL
CONDITIONS
PKG
TYP.
33
UNITS
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
NOTES
θJC
Junction to Case
1
1
1
1
1
1
θJb
Junction to Base
2.1
37
θJA0
Junction to Air, still air
Junction to Air, 1 m/s air flow
Junction to Air, 3 m/s air flow
Junction to Air, 5 m/s air flow
Thermal Resistance
NDG48
θJA1
30
θJA3
27
θJA5
26
1ePad soldered to board
Marking Diagrams
ICS
GU0831AIL
YYWW
COO
ICS
FGU0831AL
YYWW
COO
LOT
LOT
Notes:
1. Line 2 is the truncated part number.
2. ‘L’ denotes RoHS compliant package.
3. ‘I’ denotes industrial temperature grade.
4. ‘YYWW’ is the last two digits of the year and week that the part was assembled.
5. ‘COO’ denotes country of origin.
6. ‘LOT’ is the lot number.
OCTOBER 18, 2016
13
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGU0831 DATASHEET
Package Outline and Package Dimensions (NDG48, 48-pin VFQFPN)
(Ref)
ND & NE
Even
Seating Plane
(ND-1)x
(Ref)
e
A1
Index Area
(Typ)
If ND & NE
are Even
L
A3
e
2
N
1
2
N
Anvil
Singulation
1
2
(NE-1)x
(Ref)
e
-- or --
E2
E
E2
2
Sawn
Singulation
Top View
b
A
C
(Ref)
ND & NE
Odd
e
Thermal Base
D
D2
2
C
D2
0.08
Millimeters
Symbol
Min
Max
1.0
A
A1
A3
0.8
0
0.05
0.20 Reference
0.18 0.3
b
e
0.40 BASIC
6.00 x 6.00
D x E BASIC
D2 MIN./MAX.
E2 MIN./MAX.
L MIN./MAX.
3.95
3.95
0.30
4.25
4.25
0.50
N
N
12
12
D
E
Ordering Information
Part / Order Number Shipping PaCKaging
PaCKage
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
9FGU0831AKLF
9FGU0831AKLFT
9FGU0831AKILF
9FGU0831AKILFT
Trays
Tape and Reel
Trays
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Tape and Reel
“LF” to the suffix are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate to with the datasheet revision).
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
14
OCTOBER 18, 2016
9FGU0831 DATASHEET
Revision History
Rev.
Issue Date Intiator Description
Page #
1. Updated electrical tables with latest versions for release.
2. Updated SMBus nomenclature for consistency with the family.
3. Removed references to Suspend Mode – and the Suspend Rail.
This is replaced by Power Down with Wake-on-LAN modes in the
current consumption table.
A
9/24/2014
RDW
Various
4. Updated GenDes tab for front page consistency.
5. Move to final.
B
10/18/2016
RDW Removed IDT crystal part number
OCTOBER 18, 2016
15
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
Sales
Tech Support
email: clocks@idt.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2016 Integrated Device Technology, Inc.. All rights reserved.
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