9ZXL0852EKILFT [IDT]
8-Output DB800ZL Derivative PCIe Gen1â4 and UPI;
| 型号： | 9ZXL0852EKILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 8-Output DB800ZL Derivative PCIe Gen1â4 and UPI PC |
| 文件： | 总18页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Output DB800ZL Derivative for
PCIe Gen1–4 and UPI with Write
Lock
9ZXL0832E / 9ZXL0852E
Datasheet
Description
Features
▪ SMBus write lock feature; increases system security
The 9ZXL0832E / 9ZXL0852E are second-generation, enhanced
performance DB800ZL differential buffers. The parts are
pin-compatible to the 9ZXL0831A and 9ZXL0851A while offering a
much improved phase jitter performance. A fixed external feedback
maintains low drift for critical QPI/UPI applications. The 9ZXL0832E
and 9ZXL0852E have an SMBus Write Lockout pin for increased
device and system security.
▪ LP-HCSL outputs; eliminate 16 resistors, save 27mm2 of area
(0832E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save
64mm2 of area (0852E)
▪ 8 OE# pins; hardware control of each output
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
PCIe Clocking Architectures
Supported
▪ Common Clocked (CC)
▪ Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock for EMI
▪ Independent Reference (IR) with and without spread spectrum
reduction
▪ 100MHz & 133.33MHz PLL Mode; UPI and legacy QPI support
▪ 6 × 6 mm 48-VFQFPN package; small board footprint
Typical Application
▪ Servers
▪ Storage
Key Specifications
▪ Cycle-to-cycle jitter < 50ps
▪ Networking
▪ SSDs
▪ Output-to-output skew < 50ps
▪ Input-to-output delay: Fixed at 0ps
▪ Input-to-output delay variation < 50ps
▪ Phase jitter: PCIe Gen4 < 0.5ps rms
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms
▪ Phase jitter: IF-UPI < 1.0ps rms
Output Features
▪ 8 Low-Power (LP) HCSL output pairs (0832E)
▪ 8 Low-Power (LP) HCSL output pairs with 85Ω Zout (0852E)
Block Diagram
VDDR
VDDA
VDD x7
FBOUT_NC#
FBOUT_NC
PLL
DIFIN#
DIFIN
DIF7#
DIF7
^100M_133M#
vSMB_WRTLOCK
SMBCLK
8 outputs
SMBus
Engine Configuration
Factory
SMBDAT
DIF0#
DIF0
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[7:0]#
Control Logic
Resistors are integrated on 9ZXL085x devices and
external on 9ZXL083x devices
GNDR
EPAD/GND
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
^CKPWRGD_PD#
GND
36 DIF6#
35 DIF6
34 VDD
VDDR
DIF_IN
33 DIF5#
32 DIF5
31 vOE5#
30 vOE4#
29 DIF4#
28 DIF4
27 VDD
9ZXL0832
9ZXL0852
EPAD is
pin 49
Connect to GND
DIF_IN#
SMBDAT
SMBCLK
FBOUT_NC#
FBOUT_NC
VDD 10
vOE0# 11
NC 12
26 DIF3#
25 DIF3
13 14 15 16 17 18 19 20 21 22 23 24
48-VFQFPN, 6 x 6 mm, 0.4mm pitch
Pow er Management Table
SMBus
PLL State if not
CKPWRGD_PD#
DIF_IN
EN bit
OE[x]#
DIF[x]
in Bypass Mode
0
X
X
0
0
1
1
X
0
1
0
1
Low/Low
Low/Low
Low/Low
Running
Low/Low
OFF
ON
ON
ON
ON
1
Running
PLL Operating Mode Table
Pow er Connections
HiBW_BypM_LoBW#
MODE
Pin Number
Description
Low
PLL Lo BW
VDD
44
3
GND
49
Mid
High
Bypass
PLL Hi BW
Analog PLL
Analog input
2
NOTE: PLL is OFF in Bypass Mode
10,15,19,
27,34,38,42
49
DIF clocks
PLL Operating Mode Readback Table
Functionality at Pow er Up (PLL Mode)
HiBW_BypM_LoBW# Byte0, bit 7 Byte 0, bit 6
Low (Low BW)
Mid (Bypass)
High (High BW)
0
0
1
0
1
1
DIF_IN
MHz
100.00
133.33
100M_133M#
DIF[x]
DIF_IN
DIF_IN
1
0
SMBus Address
Address
+
Read/Write bit
1101100
x
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Pin Descriptions
Pin #
Pin Name
^CKPWRGD_PD#
GND
Type
IN
Description
Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent
high assertions exit Power Down Mode. This pin has internal pull-up resistor.
Ground pin.
1
2
3
GND
PWR
Power supply for differential input clock (receiver). This VDD should be treated as an analog power rail and filtered
appropriately. Nominally 3.3V.
VDDR
4
5
6
7
DIF_IN
IN
IN
HCSL true input.
DIF_IN#
SMBDAT
SMBCLK
HCSL complementary input.
I/O
IN
Data pin of SMBUS circuitry
Clock pin of SMBUS circuitry
Complementary half of differential feedback output. This pin should NOT be connected to anything outside the chip. It exists to
provide delay path matching to get 0 propagation delay.
True half of differential feedback output. This pin should NOT be connected to anything outside the chip. It ex ists to provide delay
path matching to get 0 propagation delay.
8
9
FBOUT_NC#
FBOUT_NC
OUT
OUT
PWR
IN
10 VDD
Power supply, nominally 3.3V.
Active low input for enabling output 0. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
11 vOE0#
12 NC
N/A
No connection.
13 DIF0
14 DIF0#
15 VDD
16 DIF1
17 DIF1#
OUT
OUT
PWR
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Power supply, nominally 3.3V.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 1. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
18 vOE1#
IN
19 VDD
20 NC
PWR
N/A
Power supply, nominally 3.3V.
No connection.
21 DIF2
22 DIF2#
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 2. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
23 vOE2#
24 vOE3#
IN
IN
Active low input for enabling output 3. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
25 DIF3
26 DIF3#
27 VDD
28 DIF4
29 DIF4#
OUT
OUT
PWR
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Power supply, nominally 3.3V.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 4. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
30 vOE4#
31 vOE5#
IN
IN
Active low input for enabling output 5. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
32 DIF5
33 DIF5#
34 VDD
35 DIF6
36 DIF6#
OUT
OUT
PWR
OUT
OUT
Differential true clock output.
Differential complementary clock output.
Power supply, nominally 3.3V.
Differential true clock output.
Differential complementary clock output.
Active low input for enabling output 6. This pin has an internal pull-down.
1 = disable outputs, 0 = enable outputs.
37 vOE6#
38 VDD
IN
PWR
Power supply, nominally 3.3V.
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9ZXL0832E / 9ZXL0852E Datasheet
Pin Descriptions (cont.)
Pin #
39 DIF7
Pin Name
Type
OUT
OUT
Description
Differential true clock output.
40 DIF7#
Differential complementary clock output.
Active low input for enabling output 7. This pin has an internal 120kohm pull-down.
1 = disable outputs, 0 = enable outputs.
Power supply, nominally 3.3V.
41 vOE7#
IN
42 VDD
43 NC
PWR
N/A
No connection.
44 VDDA
45 NC
PWR
N/A
Power supply for PLL core.
No connection.
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin has an internal 120kohm pull down.
0 = SMBus writes allows, 1 = SMBus writes blocked.
46 vSMB_WRTLOCK
IN
LATCHED
IN
47 ^100M_133M#
3.3V Input to select operating frequency. This pin has an internal 120kohm pull-up resistor. See Functionality Table for definition.
LATCHED Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kohm pull up resistor. See PLL Operating
48 ^HIBW_BYPM_LOBW#
IN
Mode Table for details.
Ground
49
PWR
EPAD
Test Loads
Low-Power HCSL Output Test Load
(standard PCIe source-terminated test load)
Rs
CL
L
Test
Points
Differential Zo
CL
Rs
Parameters for Low -Pow er HCSL Output Test Load
Device
Rs (Ω)
27
33
Internal
7.5
Zo (Ω) L (Inches) CL (pF)
85
100
85
10
10
10
10
2
2
2
2
9ZXL083x
9ZXL085x*
100
*Contact factory for versions of this device with Zo=100Ω.
Alternate Terminations
The LP-HCSL output can easily drive other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
“Universal” Low-Power HCSL Outputs” for termination schemes for LVPECL, LVDS, CML and SSTL.
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZXL0832E / 9ZXL0852E. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage
Input Low Voltage
Symbol
VDDx
VIL
Conditions
Minimum
Typical Maximum Units Notes
3.9
V
V
1,2
1
GND-0.5
Input High Voltage
Input High Voltage
VIH
Except for SMBus interface
SMBus clock and data pins
VDD+0.5
V
V
1,3
1
VIHSMB
3.9
150
125
Storage Temperature
Junction Temperature
Input ESD Protection
Ts
Tj
ESD prot
-65
°C
°C
V
1
1
1
Human Body Model
2500
1 Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 3.9V.
Electrical Characteristics–DIF_IN Clock Input Parameters
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Parameter
Symbol
Conditions
Minimum
Typical Maximum Units Notes
Input Crossover Voltage - DIF_IN VCROSS
Cross over voltage
150
900
mV
1
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
VSWING
dv/dt
IIN
Differential value
Measured differentially
300
0.4
-5
mV
V/ns
μA
1
8
5
1,2
VIN = VDD , VIN =GND
dtin
Measurement from differential waveform
45
0
55
125
%
1
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential measurement
ps
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics–SMBus
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Parameter
Symbol
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
Conditions
Minimum
Typical Maximum Units Notes
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
0.8
VDDSMB
0.4
V
V
2.1
at IPULLUP
at VOL
V
4
mA
V
Nominal Bus Voltage
2.7
3.6
1000
300
1
1
1
5
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating Frequency
(Max VIL - 0.15V) to (Min VIH + 0.15V)
(Min VIH + 0.15V) to (Max VIL - 0.15V)
Maximum SMBus operating frequency
ns
ns
kHz
tFSMB
fMAXSMB
500
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV.
4 DIF_IN input.
5 The differential input clock must be running for the SMBus to be active.
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Input/Supply/Common Output Parameters
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Symbol
VDDx
VDDIO
Parameter
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
Conditions
Supply voltage for core and analog
Supply voltage for DIF outputs, if present
Minimum Typical Maximum
Units Notes
V
V
3.135
0.9975
3.3
1.05
3.465
3.465
TAMB
Industrial range (TIND
)
-40
25
85
°C
VIH
VIL
VIH
VIL
VIL
IIN
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
Single-ended inputs, except SMBus, tri-level inputs
2
VDD + 0.3
0.8
V
V
Single-ended inputs, except SMBus, tri-level inputs GND - 0.3
Tri-level inputs
Tri-level inputs
Tri-level inputs
2.2
1.2
VDD + 0.3
1.8
V
VDD/2
V
GND - 0.3
-5
0.8
V
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
5
μA
Input Current
VIN = 0 V; inputs with internal pull-up resistors
IINP
-50
50
μA
VIN = VDD; inputs with internal pull-down resistors
VDD = 3.3 V, Bypass Mode
Fibyp
Fipll
1
400
102.5
135
7
MHz
MHz
MHz
Input Frequency
Pin Inductance
Capacitance
VDD = 3.3 V, 100MHz PLL Mode
98.5
132
100.00
133.33
Fipll
VDD = 3.3 V, 133.33MHz PLL Mode
Lpin
nH
pF
pF
pF
1
1
CIN
Logic inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
5
CINDIF_IN
COUT
2.7
6
1,4
1
Output pin capacitance
From VDD power-up and after input clock stabilization
TSTAB
Clk Stabilization
1.0
1.8
ms
1,2
or de-assertion of PD# to 1st clock
Allowable frequency for PCIe applications
(Triangular modulation)
Input SS Modulation
Frequency PCIe
fMODINPCIe
tLATOE#
tDRVPD
30
4
33
10
kHz
clocks
μs
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
OE# Latency
Tdrive_PD#
5
1,2,3
1,3
49
300
PD# de-assertion
tF
Tfall
Fall time of control inputs
5
5
ns
ns
2
2
tR
Trise
Rise time of control inputs
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are > 200mV.
4 DIF_IN input.
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Current Consumption
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Symbol
Parameter
Conditions
Minimum
Typical Maximum Units
Notes
IDDA
Operating Supply Current
VDDA, PLL Mode at 100MHz
37
55
3
45
68
4
mA
mA
mA
mA
1
IDD
Operating Supply Current
Powerdown Current
Powerdown Current
All other VDD pins at 100MHz
VDDA, CKPWRGD_PD# = 0
IDDAPD
IDDPD
1
All other VDD pins, CKPWRGD_PD# = 0
1
2
1. Includes VDDR if applicable.
Electrical Characteristics–HCSL/LP-HCSL Outputs
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Specification
Limit
Symbol
Parameter
Conditions
Minimum Typical Maximum
Units Notes
dV/dt
ΔdV/dt
Vmax
Vmin
Vcross_abs
Δ-Vcross
Slew Rate
Slew Rate Matching
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Scope averaging on.
Single-ended measurement.
Measurement on single-ended signal using
absolute value (scope averaging off).
Scope averaging off.
2
2.9
7.1
792
-35
372
15
4
20
850
150
550
140
1
4
V/ns
%
1, 2, 3
1, 4, 7
7
–
20
660
-150
250
1150
-300
250 – 550
140
mV
7
mV
mV
1, 5, 7
1, 6, 7
Scope averaging off.
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform.
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point
where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and
Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to
limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Skew and Differential Jitter Parameters
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Symbol
Parameter
Conditions
Minimum Typical Maximum Units
Notes
Input-to-output skew in PLL Mode
tSPO_PLL
CLK_IN, DIF[x:0]
-100
2
-21.3
2.6
100
4
ps
ns
ps
1,2,4,5,8
at 100MHz, nominal temperature and voltage
Input-to-output skew in Bypass Mode
at 100MHz, nominal temperature and voltage
Input-to-output skew variation in PLL Mode
at 100MHz, across voltage and temperature
tPD_BYP
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
1,2,3,5,8
1,2,3,5,8
tDSPO_PLL
-50
0.0
50
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
TAMB = 0 to 70°C
-250
-350
250
350
ps
ps
1,2,3,5,8
1,2,3,5,8
tDSPO_BYP
CLK_IN, DIF[x:0]
Input-to-output skew variation in Bypass Mode
at 100MHz, across voltage and temperature,
TAMB = -40°C to 105°C
Random differential tracking error between two 9ZX
devices in Hi BW Mode
Random differential spread spectrum tracking error
between two 9ZX devices in Hi BW Mode
Output-to-output skew across all outputs, common to
PLL and Bypass Mode, at 100MHz
ps
(rms)
tDTE
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
DIF[x:0]
3
5
1,2,3,5,8
1,2,3,5,8
1,2,3,8
tDSSTE
23
50
50
ps
ps
tSKEW_ALL
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode at 100MHz
PLL Mode
0
0
1.3
1.3
2.6
1.0
50.3
0
2.5
2
dB
dB
7,8
7,8
8,9
8,9
1
2
4
MHz
MHz
%
0.7
45
-1
1.4
55
1
tDCD
Duty Cycle Distortion
%
1,10
1,11
1,11
14
50
5
ps
t
Jitter, Cycle to Cycle
jcyc-cyc
Additive jitter in Bypass Mode
0.1
ps
Notes for preceding table:
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device.
5
Measured with scope averaging on to find mean value.
6 t is the period of the input clock.
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform.
©2018 Integrated Device Technology, Inc
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9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common
Clocked (CC) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
Specification
Symbol
Parameter
Conditions
Minimum Typical Maximum
Units
Notes
Limit
t
PCIe Gen 1
13.4
0.2
30
86
ps (p-p) 1, 2, 3
jphPCIeG1-CC
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
(rms)
0.7
3
1, 2
t
jphPCIeG2-CC
Phase Jitter,
PLL Mode
ps
(rms)
1.0
0.2
1.5
0.4
3.1
1, 2
ps
(rms)
t
1
1, 2
jphPCIeG3-CC
ps
(rms)
t
0.2
0.4
0.5
1, 2
jphPCIeG4-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
t
PCIe Gen 1
0.01
0.06
ps (p-p) 1, 2, 3, 4
jphPCIeG1-CC
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
PCIe Gen 4
ps
0.01
0.01
0.06
0.06
1, 2, 3, 4
(rms)
t
jphPCIeG2-CC
Additive Phase
Jitter, Bypass
mode
ps
Not Applicable
1, 2, 3, 4
(rms)
ps
t
0.01
0.01
0.06
0.06
1, 2, 3, 4
(rms)
jphPCIeG3-CC
ps
t
1, 2, 3, 4
(rms)
jphPCIeG4-CC
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe
Independent Reference (IR) Architectures
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
Symbol
Parameter
Conditions
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
Minimum Typical Maximum Industry Limit Units
Notes
ps
(rms)
ps
t
0.9
0.6
1.1
2
1, 2, 5
jphPCIeG2-SRIS
Phase Jitter, PLL
Mode
t
0.65
0.05
0.05
0.7
1, 2, 5
2, 4, 5
2, 4, 5
jphPCIeG3-SRIS
(rms)
ps
(rms)
ps
t
Additive Phase
Jitter, Bypass
mode
0.01
0.01
jphPCIeG2-SRIS
Not Applicable
t
jphPCIeG3-SRIS
(PLL BW of 2-4MHz, CDR = 10MHz)
(rms)
Notes for PCIe Filtered Phase Jitter tables (CC) and (IR)
1 Applies to all differential outputs, guaranteed by design and characterization.
2 Calculated from Intel-supplied Clock Jitter Tool, when driven by 9SQL495x or equivalent with spread on and off.
3 Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1-12
.
4 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a 2 ) ], where "a" is rms input jitter and "c" is rms total jitter.
5
IR is the new name for Separate Reference Independent Spread (SRIS) and Separate Reference no Spread (SRNS) PCIe clock
architectures. According to the PCIe Base Specification Rev 4.0 version 0.7 draft, the jitter transfer functions and corresponding jitter limits are
not defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this table.
There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates.
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
Electrical Characteristics–Filtered Phase Jitter Parameters - QPI/UPI
TAMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
Specification
Limit
Symbol
Parameter
Conditions
Minimum Typical Maximum
Units
Notes
1, 2
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & UPI
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
0.14
0.07
0.06
0.30
0.13
0.1
0.5
0.3
0.2
1
t
1, 2
jphQPI_UPI
Phase Jitter, PLL
Mode
(100MHz, 8.0Gb/s, 12UI)
QPI & UPI
(100MHz, ?9.6Gb/s, 12UI)
1, 2
0.1
0.17
0.14
0.2
t
IF-UPI
1, 4, 5
1, 2, 3
1, 2, 3
1, 2, 3
1, 4
jphIF-UPI
QPI & UPI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & UPI
0.0
0.0
0.01
0.01
0.01
0.07
t
Additive Phase
Jitter, Bypass
mode
jphQPI_UPI
(100MHz, 8.0Gb/s, 12UI)
QPI & UPI
(100MHz, ?9.6Gb/s, 12UI)
Not Applicable
0.0
t
IF-UPI
0.06
jphIF-UPI
1 Applies to all differential outputs, guaranteed by design and characterization.
2 Calculated from Intel-supplied Clock Jitter Tool, when driven by 9SQL495x or equivalent with spread on and off.
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a 2 ) ], where "a" is rms input jitter and "c" is rms total jitter.
4 Calculated from phase noise analyzer when driven by Wenzel Associates source with Intel-specified brick-wall filter applied.
5 Top number is when the buffer is in Low BW mode, bottom number is when the buffer is in High BW mode.
Electrical Characteristics–Unfiltered Phase Jitter Parameters - 12kHz to
20MHz
TAMB = over the specified operating range. Supply voltages per normal operation conditions; see Test Loads for loading conditions
Symbol
Parameter
Conditions
Minimum Typical Maximum Industry Limit Units
Notes
1, 2
Phase Jitter, PLL
Mode
Phase Jitter, PLL
Mode
fs
t
PLL High BW, SSC OFF, 100MHz
PLL Low BW, SSC OFF, 100MHz
171
184
225
225
jph12k-20MHi
(rms)
fs
(rms)
t
1, 2
jph12k-20MLo
Not Applicable
Additive Phase
Jitter, Bypass
fs
(rms)
t
Bypass Mode, SSC OFF, 100MHz
107
125
1, 2, 3
jph12k-20MByp
1 Applies to all outputs when driven by Wenzel Associates source.
2 12kHz to 20MHz brick wall filter.
3 For RMS values, additive jitter is calculated by solving for b [b = sqrt(c2 - a 2 )], where "a" is rms input jitter and "c" is rms total jitter.
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Measurement Window
0.1s
1 Clock
SSC OFF Frequency -c2c jitter
1μs
-SSC
0.1s
- ppm
0.1s
+ ppm
1μs
+SSC
Short-Term
Average
Maximum
1 Clock
Center
+c2c jitter Units Notes
AbsPer
Maximum
Short-Term Long-Term 0 ppm Period
Long-Term
Average
Maximum
10.00100
7.50075
MHz
AbsPer
Average
Minimum
Average
Minimum
9.99900
7.49925
Nominal
Minimum
100.00
133.33
9.94900
7.44925
10.00000
7.50000
10.05100
7.55075
ns
ns
1,2,3
1,2,4
DIF
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Measurement Window
1 Clock
SSC ON Frequency -c2c jitter
1μs
-SSC
0.1s
- ppm
0.1s
0.1s
+ ppm
1μs
+SSC
1 Clock
Center
+c2c jitter Units Notes
AbsPer
Maximum
Short-Term Long-Term 0 ppm Period
Long-Term
Average
Maximum
10.02607
7.51955
Short-Term
Average
Maximum
10.05107
7.53830
MHz
AbsPer
Average
Minimum
9.99906
7.49930
Average
Minimum
10.02406
7.51805
Nominal
Minimum
99.75
133.00
9.94906
7.44930
10.02506
7.51880
10.10107
7.58830
ns
ns
1,2,3
1,2,4
DIF
Notes:
1 Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ accuracy requirements (+/-100ppm).
The buffer itself does not contribute to ppm error.
3
Driven by SRC output of main clock, 100MHz PLL Mode or Bypass Mode.
4
Driven by CPU output of main clock, 133MHz PLL Mode or Bypass Mode.
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
General SMBus Serial Interface Information
How to Write
How to Read
▪ Controller (host) will send a start bit
▪ Controller (host) sends a start bit
▪ Controller (host) sends the write address
▪ IDT clock will acknowledge
▪ Controller (host) sends the write address
▪ IDT clock will acknowledge
▪ Controller (host) sends the beginning byte location = N
▪ IDT clock will acknowledge
▪ Controller (host) sends the beginning byte location = N
▪ IDT clock will acknowledge
▪ Controller (host) sends the byte count = X
▪ IDT clock will acknowledge
▪ Controller (host) will send a separate start bit
▪ Controller (host) sends the read address
▪ IDT clock will acknowledge
▪ Controller (host) starts sending Byte N through Byte N+X-1
▪ IDT clock will acknowledge each byte one at a time
▪ Controller (host) sends a stop bit
▪ IDT clock will send the data byte count = X
▪ IDT clock sends Byte N+X-1
▪ IDT clock sends Byte 0 through Byte X (if X(H) was written to
Index Block Write Operation
Byte 8)
Controller (Host)
IDT (Slave/Receiver)
▪ Controller (host) will need to acknowledge each byte
▪ Controller (host) will send a not acknowledge bit
▪ Controller (host) will send a stop bit
T
starT bit
Slave Address
WR
WRite
Index Block Read Operation
ACK
ACK
ACK
ACK
Controller (Host)
starT bit
IDT (Slave/Receiver)
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
T
Slave Address
WR
WRite
ACK
ACK
Beginning Byte = N
O
O
O
RT
Repeat starT
Slave Address
ReaD
O
O
O
RD
Byte N + X - 1
ACK
ACK
P
stoP bit
Data Byte Count=X
Beginning Byte N
ACK
ACK
O
O
O
O
O
O
Byte N + X - 1
N
P
Not acknowledge
stoP bit
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
SMBus Table: PLL Mode and Frequency Select Register
Pin #
48
48
Byte 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
PLL Mode 1
PLL Mode 0
Control Function
PLL Operating Mode Rd back 1
PLL Operating Mode Rd back 0
Reserved
Reserved
Enable S/W control of PLL BW
PLL Operating Mode 1
PLL Operating Mode 1
Frequency Select Readback
Type
R
R
0
1
Default
Latch
Latch
0
See PLL Operating Mode Readback
Table
0
0
1
PLL_SW_EN
PLL Mode 1
PLL Mode 0
100M_133M#
RW
RW
RW
R
HW Latch
See PLL Operating Mode Readback
SMBus Control
Table
1
47
133MHz
100MHz
Latch
Note: Setting bit 3 to '1' allows the user to override the latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode Readback
Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. If the user changes these bits, a warm reset of the system will have to be accomplished.
SMBus Table: Output Control Register
Pin #
32/33
28/29
25/26
21/22
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Type
RW
RW
RW
RW
0
1
Default
DIF_5_En
DIF_4_En
DIF_3_En
DIF_2_En
1
1
1
1
0
1
1
0
Low/Low
OE# Pin Control
Reserved
16/17
13/14
DIF_1_En
DIF_0_En
Output Enable
Output Enable
RW
RW
Low/Low
OE# Pin Control
Reserved
SMBus Table: Output Control Register
Pin #
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
1
0
1
39/40
35/36
OE# Pin Control
OE# Pin Control
DIF_7_En
DIF_6_En
Output Enable
Output Enable
RW
RW
Low/Low
Low/Low
Reserved
SMBus Table: Reserved Register
Pin #
Byte 3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
SMBus Table: Reserved Register
Byte 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
SMBus Table: Vendor & Revision ID Register
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
Default
-
-
-
-
-
-
-
-
0
1
0
0
0
0
0
1
REVISION ID
E rev = 0100
-
-
-
-
-
-
-
-
VENDOR ID
SMBus Table: DEVICE ID
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Device ID 7 (MSB)
Type
R
R
R
R
R
R
R
R
0
1
Default
-
-
-
-
-
-
-
-
1
1
1
x
x
x
x
x
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
0832 is E6 Hex
0852 is F6 Hex
SMBus Table: Byte Count Register
Byte 7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
0
-
-
-
-
-
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
Writing to this register configures how many
bytes will be read back.
Default value is 8 hex, so 9 bytes (0 to
8) will be read back by default.
SMBus Table: Reserved Register
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
Name
Control Function
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
©2018 Integrated Device Technology, Inc
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August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
Package Outline Draw ings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/ndndg-48-package-outline-60-x-60-mm-body-040-mm-pitch-qfn-epad-size-420-x-420-mm
Ordering Information
Orderable Part Number
Package
Carrier Type
Temperature
9ZXL0832EKILF
9ZXL0832EKILFT
9ZXL0852EKILF
9ZXL0852EKILFT
6 x 6 mm, 0.4mm pitch 48-VFQFPN
6 x 6 mm, 0.4mm pitch 48-VFQFPN
6 x 6 mm, 0.4mm pitch 48-VFQFPN
6 x 6 mm, 0.4mm pitch 48-VFQFPN
Tray
Reel
Tray
Reel
-40° to +85°C
-40° to +85°C
-40° to +85°C
-40° to +85°C
“LF” designates PB-free configuration, RoHS compliant.
“E” is the device revision designator (will not correlate with the datasheet revision).
Marking Diagrams
1. “I” denotes industrial temperature range
2. “L” denotes RoHS compliant package.
ICS
XL0852EIL
YYWW
COO
ICS
XL0832EIL
YYWW
COO
3. “YYWW” denotes the last two digits of the year and week the part was
assembled.
4. “COO” denotes country of origin.
5. “LOT” denotes the lot number.
LOT
LOT
Revision History
Revision Date
Description of Change
August 14, 2018
July 17, 2018
Updated block diagram.
Corrected typos in Byte 1, bits 1 and 2.
April 13, 2018
Updated absolute maximum supply voltage rating and VIHSMB to 3.9V.
Removed “5V tolerant” reference in pins 6 and 7 descriptions.
Initial release.
December 1, 2017
September 29, 2017
©2018 Integrated Device Technology, Inc
15
August 14, 2018
9ZXL0832E / 9ZXL0852E Datasheet
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
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www.IDT.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intel-
lectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
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Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2018 Integrated Device Technology, Inc
16
August 14, 2018
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch
NDG48P2, PSC-4212-02, Rev 02, Page 1
© Integrated Device Technology, Inc.
48-VFQFPN Package Outline Drawing
6.0 x 6.0 x 0.90 mm Body, Epad 4.2 x 4.2 mm, 0.40mm Pitch
NDG48P2, PSC-4212-02, Rev 02, Page 2
Package Revision History
Description
July 24, 2018 Rev 02 New Format Change QFN to VFQFPN, Recalculate Land Pattern
Sept 9, 2014
Rev 01 Add Chamfer
Date Created Rev No.
© Integrated Device Technology, Inc.
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