CA95C18-16CP_技术文档

CA95C68/18/09

DES DATA CIPHERING PROCESSORS (DCP)

• Encrypts/Decrypts data using National Bureau

of Standards Data Encryption Standard (DES)

The Tundra Semiconductor Corporation CA95C68/18/09

DES Data Ciphering Processors (DCPs) implement the

National Bureau of Standards Data Encryption Standard

(DES), FIPS PUB 46 (1-15-1977). The DCPs were designed

to be used in a variety of environments where computer and

communications security is essential.

• High speed, pin and function compatible

version of industry standard AMD AM9568,

AM9518 and VLSI VM009

• Supports four standard ciphering modes:

Electronic Code Book (ECB), Cipher Block

Chaining (CBC), as well as 1 and 8 bit Cipher

Feedback (CFB)

The DCPs provide a high throughput rate (up to 14 Mbytes

per second) using ECB or CBC modes of operation. The

DCPs provide a unique 1 bit CFB mode as well as the

standard 8 bit mode. Separate ports for key input, clear data

and enciphered data enhance security for your application.

• Data rates greater than 11 Mbytes per second

(25 MHz) in ECB or CBC modes

• Three separate registers for encryption,

decryption and master keys improve system

security and throughput by eliminating the need

to reload keys frequently

The system communicates with the DCP using commands

entered in the Master Port or through auxiliary control lines.

Once the DCP is set up, data can ﬂow through at high speeds

since input, output and ciphering activities are performed

concurrently. External DMA control can easily be used to

enhance throughput in many system conﬁgurations.

• Fully static CMOS,TTL I/O compatible device,

operates at up to 33MHz

• Low power consumption allows battery back-up

of internal key registers

• Three separate programmable ports (master,

slave and key data)

The CA95C68 is designed to interface directly to the

iAPX86, 88 CPU bus, and with a minimum of external logic,

to the 2900 and 8051 families of processors. The CA95C18

is designed to interface directly with Z8000, 68000 type bus

interfaces.

• Available in 44 pin PLCC and 40 pin PDIP and 44

pin TQFP packages

3

3.2

CA95C68/18/09

The CA95C09 may be conﬁgured to behave as either the

CA95C68 or the CA95C18 (see OPTION pin in Table 3-2),

the only difference being the order of the signal names on

the device package.

Table 3-1 : CA95C68/18/09 Data Transfer Rates

Product

Data Transfer Rates

System Clock

(MHz)

ECB or CBC Mode

(Mbytes/s)

CFB-8 Mode

(Mbytes/s)

CFB-1 Mode

(Mbits/s)

Code

CA95Cxx – 5

CA95Cxx – 10

CA95Cxx – 16

CA95Cxx – 20

CA95Cxx – 25

CA95Cxx-33

2.22

4.44

0.27

0.55

0.88

1.11

1.38

1.85

0.27

0.55

0.88

1.11

1.38

1.85

5

10

16

20

25

33

7.10

8.88

11.11

14.81

Tundra Semiconductor Corporation

3-25

CA95C68/18/09

Tundra Semiconductor Corporation

PAR

PARITY

BIT

KEY

OR

CONTROL

AUX -AUX

AUXILIARY

PORT

7

0

INPUT BUS (8-BITS)

PARITY

CHECK

AFLG

ASTB

AUXILIARY

PORT

CONTROL

I/O

AUXILIARY

PORT

CONTROL

MODE

REGISTER

COMMAND

REGISTER

MASK

REGISTER

INPUT

REGISTER

(64-BITS)

M

KEY

E

KEY

D KEY

REGISTER

(56-BITS)

REGISTER

(56-BITS)

REGISTER

(56-BITS)

MUX/DIRECT

CONTROL

C/K

MASTER

CONTROL

DES ALGORITHM

PROCESSING

UNIT

CLK

CA95C18 CA95C68

(64-BITS)

MCS

MR/W

MDS

MCS

MWR

MRD

MASTER

PORT

CONTROL

I/O

MASTER

PORT

CONTROL

SFLG

SCS

SDS

SLAVE

PORT

CONTROL

I/O

STATUS

REGISTER

OUTPUT

REGISTER

(64-BITS)

IVE

REGISTER

(64-BITS)

IVD

REGISTER

(64-BITS)

SLAVE

PORT

CONTROL

MAS

MALE

MFLG

C BUS (8-BITS)

SP -SP

MP -MP

7

0

KEY

OR

0

OUTPUT BUS (8-BITS)

INPUT BUS (8-BITS)

DATA

SLAVE

PORT

MASTER

PORT

DATA

Figure 3-1 : CA95C68/18/09 Block Diagrams

3-26

Tundra Semiconductor Corporation

CA95C68/18/09

V

1

2

3

4

5

6

7

8

9

V

DD

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

SS

•

SP

0

1

2

3

0

1

2

3

4

5

6

7

6

5

4

3

2

1 44 43 42 41 40

SP

AUX

4

AUX (S/S)

5

AUX (E/D)

6

AUX (K/D)

7

39

38

37

36

35

34

33

32

31

30

29

0

1

2

3

AUX

4

AUX

AUX (S/S)

5

AUX (E/D)

6

AUX (K/D)

7

SFLG

(BSY) AUX

(CP) AUX

(BSY) AUX

(CP) AUX

AFLG

ASTB

PAR

C/K

NC

AFLG

ASTB

PAR

CA95C68

DCP

CA95C68

DCP

10

11

12

13

14

15

16

17

18

19

20

SFLG

SCS

SDS

MWR

MALE

MRD

SCS

SDS

C/K

MWR

MALE

MRD

MCS

CLK

MFLG

NC

MFLG

MP

0

MP

1

MP

2

MP

3

MP

4

MP

5

MP

6

MP

7

18 19 20 21 22 23 24 25 26 27 28

V

SS

Figure 3-5 : CA95C68 44-Pin PLCC

Figure 3-2 : CA95C68 40-Pin PDIP

V

1

2

3

4

5

6

7

8

9

V

DD

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

SS

•

SP

0

1

2

3

0

1

2

3

4

5

6

7

SP

6

5

4

3

2

1 44 43 42 41 40

SP

AUX

4

AUX (S/S)

5

AUX (E/D)

6

AUX (K/D)

7

8

39

38

37

36

35

34

33

32

31

30

29

0

1

2

3

AUX

4

AUX

AUX (S/S)

5

AUX (E/D)

6

AUX (K/D)

7

SFLG

(BSY) AUX

(CP) AUX

9

(BSY) AUX

(CP) AUX

10

11

12

13

14

15

16

17

AFLG

ASTB

PAR

C/K

NC

AFLG

ASTB

PAR

CA95C18

DCP

10

11

12

13

14

15

16

17

18

19

20

CA95C18

DCP

SFLG

SCS

SDS

MR/W

MAS

MDS

SCS

SDS

C/K

MR/W

MAS

MDS

MCS

CLK

MFLG

NC

MFLG

MP

0

MP

1

MP

2

MP

3

MP

4

MP

5

MP

6

MP

7

18 19 20 21 22 23 24 25 26 27 28

V

SS

Figure 3-6 : CA95C18 44-Pin PLCC

Figure 3-3 : CA95C18 40-Pin PDIP

6

5

4

3

2

1 44 43 42 41 40

44 43 42 41 40 39 38 37 36 35 34

7

AUX

39

38

AUX

4

0

AUX

1

2

33

32

31

30

29

28

27

26

25

24

23

AUX

4

0

1

8

9

AUX (S/S)

5

AUX

(BSY)AUX

(CP)AUX

AUX (S/S)

1

2

3

5

(BSY)

3

37

36

AUX (E/D)

6

AUX (E/D)

6

2

(CP) AUX

10

11

4

AUX (K/D)

7

AUX (K/D)

3

7

AFLG

5

SFLG

AFLG

35

34

33

32

31

SFLG

CA95C09

DCP

CA95C09

DCP

V

6

V

SS

12

13

SS

V

SS

ASTB

PAR

7

SCS

ASTB

SCS

8

SDS

PAR

14

15

SDS

DCM

CLK

9

MWR_MR/W

MALE_MAS

MRD_MDS

DCM

MWR_MR/W

10

11

16

17

CLK

30

29

MALE_MAS

MRD_MDS

MFLG

12 13 14 15 16 17 18 19 20 21 22

18 19 20 21 22 23 24 25 26 27 28

Figure 3-7 : CA95C09 44-Pin TQFP

Figure 3-4 : CA95C09 44-Pin PLCC

Tundra Semiconductor Corporation

3-27

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-2 : Pin Description

95C68/18

Symbol

95C09

TYPE

Name and Function

PDIP PLCC PLCC TQFP

CLK

14

15

16

10

I

Clock: An external timing source is input via this pin. The Master and Slave

Port data strobe signals ( MWR , MRD , SDS for CA95C68 and MDS ,

SDS for CA95C18) must change synchronously with the clock input. In

Direct Control Mode the AUX -S/S must also be synchronous. The output

5

SFLG

ﬂags for the three ports ( AFLG , MFLG ,

synchronously with the clock.

) will all change

C/K

13

14

–

I

Control/Key Mode Control: This input controls the mode of operation of

the DCP. The DCP enters into Multiplexed Control Mode when a low input is

placed on the C/K pin, enabling programmed access to internal registers

through the Master Port and enabling input of keys through the Auxiliary

Port. In Direct Control Mode (C/K HIGH), several of the Auxiliary Port pins

become direct control/status signals which can be driven/sensed by high-

speed controller logic, and access to internal registers through the Master

Port is limited to the Input and Output Registers.

DCM

–

15

9

I

Direct Control Mode: (For CA95C09) This input functions identical to the

C/K input. (See C/K pin description).

MP

–

21-24

19-16

23-26

21-18

24-27

21-18

18-21

15-12

I/O

Master Port Bus: These eight bi-directional signals are used to input and

output data, as well as specify the internal register addresses in Multiplexed

Control Mode. The Master Port provides software access to the Status,

Command, Mode, Mask, Input and Output Registers. For the CA95C68, the

tri-state Master Port outputs will be enabled only when the Master Port is

selected by Master Port Chip Select ( MCS ) LOW, and when Master Port

Read ( MRD ) is strobed LOW. For the CA95C18, the Master Port outputs

are enabled when selected by MCS , and when MR/W is HIGH and MDS

7

0

is LOW. MP is the low-order bit. Data and key information are entered into

0

this port with the most signiﬁcant byte ﬁrst.

MCS

25

27

28

22

I

Master Port Chip Select: This active LOW input signal is used to select the

Master Port. In Multiplexed Control Mode (C/K LOW), the level on MCS is

latched internally on the falling edge of Master Port Address Latch Enable

(MALE). This latched level is maintained as long as MALE is LOW; when

MALE is HIGH, the latch becomes transparent and the internal signal will

follow the MCS input. No latching of MCS occurs in Direct Control Mode

(C/K HIGH). The level on MCS is passed directly to the internal select

circuitry regardless of the state of Master Port Address Latch Enable

(MALE).

3-28

Tundra Semiconductor Corporation

CA95C68/18/09

Cont'd

Table 3-2 : Pin Description

95C68/18

95C09

Symbol

TYPE

Name and Function

PDIP PLCC PLCC TQFP

MALE

27

26

30

29

–

I

Master Port Address Latch Enable: (For CA95C68) In Multiplexed Control

Mode (C/K LOW), an active HIGH signal on this pin indicates the presence of

valid address and chip select information at the Master Port. This information

will be latched internally on the falling edge of MALE. When C/K is HIGH

(Direct Control Mode), MALE has no affect on DCP operation.

MRD

–

I

Master Port Read: (For CA95C68) This active LOW input is used with a

valid MCS to indicate that data is to be output on the Master Port bus.

Master Port Read ( MRD ) and Master Port Write ( MWR ) are normally

mutually exclusive; if both become active simultaneously, the DCP is reset to

ECB Mode and all ﬂags go inactive.

MWR

MAS

28

27

31

30

–

I

Master Port Write: (For CA95C68) This active low input signal indicates to

the DCP that valid data is present on MP -MP for an input operation. The

7

0

rising edge of MWR latches the data into the selected internal register. If

MWR and MRD both go LOW simultaneously, the DCP is reset.

Master Port Address Strobe: (For CA95C18) In Multiplexed Control Mode

(C/K HIGH), a LOW on MAS indicates the presence of a valid chip select

signal and address information. This information will be latched on the rising

edge of MAS . In Direct Control Mode, MAS has no affect on the DCP

operation. The DCP will be reset if MAS and MDS both go low

simultaneously.

MDS

26

28

29

31

–

I

Master Port Data Strobe: (For CA95C18) This active low input is used in

conjunction with a valid Master Port Chip Select ( MCS ) to indicate that

valid data is present on the MP -MP bus for an input operation or that data

7

0

is to be placed on the Master Port Bus during output. MDS and MAS are

mutually exclusive; if they both go active simultaneously, the DCP is reset to

ECB mode and all ﬂags go inactive.

MR/W

Master Port Read/Write: (For CA95C18) This input signal indicates to the

DCP whether the current Master Port operation is a read (HIGH) where data

is transferred from the device, or a write (LOW) where data is stored to an

internal register. MR/W is not latched internally and must be held stable while

MDS is LOW.

Tundra Semiconductor Corporation

3-29

CA95C68/18/09

Tundra Semiconductor Corporation

Cont'd

Table 3-2 : Pin Description

95C68/18

Symbol

95C09

TYPE

Name and Function

PDIP PLCC PLCC TQFP

–

29

23

I

Master Port Read or Master Port Data Strobe: (For CA95C09) When the

OPTION pin is HIGH this input functions as MRD . When the OPTION pin is

LOW this input functions as MDS . (See appropriate pin description).

MRD

MDS

MALE –

MAS

_

–

30

24

I

Master Port Address Latch Enable or Master Port Address Strobe: (For

CA95C09) When the OPTION pin is HIGH this input functions as MALE and

when OPTION is LOW it functions as MAS . (See the appropriate pin

description).

MWR –

MR/W

–

31

17

25

11

I

Master Port Write or Master Port Read/Write: (For CA95C09) When the

OPTION pin is HIGH this input functions as MWR and when OPTION is

LOW it functions as MR/W. (See the appropriate pin description).

MFLG

15

16

O

Master Port Flag:This active LOW ﬂag indicates the need for a data transfer

into or out of the Master Port during normal ciphering operation. The Master

Port will be associated with either the Input or Output Register depending

upon the setting of the Control bits in the Mode Register (See Register

Description).

If data is to be transferred through the Master Port to the Input Register, then

MFLG reﬂects the contents of the Input Register. After any Start command

is entered, MFLG will go active (LOW) whenever the Input Register is not

full. MFLG is forced HIGH by any command other than

a Start.

Conversely, if the Master Port is associated with the Output Register,

MFLG reﬂects the contents of the Output Register (except in single port

conﬁguration; see Functional Description). Whenever the Output Register is

not empty MFLG will be active (LOW). In single port mode of operation, the

Master Port ﬂag reﬂects the contents of the Input Register, while the Slave

Port Flag ( SFLG , see below) is associated with the Output Register.

SP –SP

36-39

5-2

40-43

6-3

40-43

6-3

34-37

44-41

I/O

Slave Port Bus: This 8 bit bi-directional data bus provides a second

7

0

input/output interface to the DCP, allowing overlapped input, ciphering and

output operations. The tri-state Slave Port will be accessed only when the

Mode Register is conﬁgured for dual port operation, Slave Port Chip Select

(SCS ) and Slave Port Data Strobe (SDS ) are both LOW and SFLG =0.

Data entered or retrieved through this port is the most signiﬁcant byte in/out

ﬁrst (SP is the most signiﬁcant bit).

7

3-30

Tundra Semiconductor Corporation

CA95C68/18/09

Cont'd

Table 3-2 : Pin Description

95C68/18

95C09

Symbol

TYPE

Name and Function

PDIP PLCC PLCC TQFP

SCS

30

29

33

32

33

32

27

26

I

Slave Port Chip Select: This active LOW signal is logically combined with

the Slave Port Data Strobe (SDS ) to facilitate Slave Port data transfers in a

bus environment. SCS is not latched internally, and may be tied

permanently LOW without impairing Slave Port operation.

SDS

I

Slave Port Data Strobe: This active LOW input, in conjunction with Slave

Port Chip Select (SCS ) LOW indicates to the DCP that valid data is on the

SP -SP lines for an input operation, or that data is to be driven onto SP -

7

0

7

SP lines for output. The direction of data ﬂow is determined by Control bits

0

in the Mode Register. (See Register Description).

SFLG

31

34

35

29

O

Slave Port Flag: This active LOW output indicates the state of either the

Input Register or the Output Register, depending on the Mode Register

conﬁguration. In single port conﬁguration, SFLG will go active whenever

the Output Register is not empty during normal processing. In dual port

conﬁguration, SFLG will reﬂect the content of whichever register is

associated with the Slave Port. If the Input Register is assigned to the Slave

Port, SFLG will go active whenever the Input Register is not full, once any

of the Start commands has been entered; SFLG will be forced inactive if

any other command is entered. Conversely, if the Slave Port is assigned to

the Output Register, SFLG will go active whenever the Output Register is

not empty.

AUX₇-AUX₀

32-35

9-6

36-39

10-7

36-39

10-7

30-33

4-1

I/O

Auxiliary Port Bus: In Multiplexed Control Mode (C/K LOW), these eight

lines form a key byte input port which may be used to enter the Master and

Session Keys. The Master Key can only be entered through this port but

Session Keys may alternatively be entered via the Master Port. AUX is the

0

low-order bit, and is considered to be the Parity bit in key bytes. The most

signiﬁcant byte of the key is entered ﬁrst. When the DCP is operated in

Direct Control Mode, (C/K HIGH), the Auxiliary Port's key-entry function is

disabled and ﬁve of the eight lines become direct control/status lines for

interfacing to high-speed microprogrammed controllers. In this case, AUX ,

0

AUX and AUX have no function (they may be tied HIGH) and the other pins

1

4

are deﬁned on the following pages.

AUX –S/S

5

34

33

38

37

38

37

32

31

I

Start/Stop: In Direct Control Mode, when this pin goes LOW (Stop) the DCP

will follow the sequence that would normally occur when a Stop Command is

entered. Conversely, when this input goes HIGH, a sequence equivalent to a

Start Encryption or Start Decryption command will be followed. At the time

AUX -S/S goes HIGH, the level on AUX -E/D selects either the Start

5

6

Encryption or Start Decryption ciphering operation.

AUX₆–E/D

Encrypt/Decrypt: In Direct Control Mode, this input speciﬁes whether the

ciphering algorithm is to encrypt (E/D HIGH) or decrypt (E/D LOW) when

AUX -S/S goes HIGH to initiate a normal data ciphering operation.

5

When AUX -K/D goes HIGH, initiating entry of key bytes, the level on AUX -

7

6

E/D speciﬁes whether the bytes are to be written into the E Key Register (E/D

HIGH) or the D Key Register (E/D LOW).

The AUX -E/D input is not latched internally, and must be held constant

6

whenever one or more of AUX -S/S, AUX -K/D, AUX -BSY , or AUX -CP are

5

7

2

3

active. Corrupted data in the internal registers will occur if the proper level on

AUX -E/D is not maintained during loading or ciphering operations.

6

Tundra Semiconductor Corporation

3-31

CA95C68/18/09

Tundra Semiconductor Corporation

Cont'd

Table 3-2 : Pin Description

95C68/18

Symbol

95C09

TYPE

Name and Function

PDIP PLCC PLCC TQFP

AUX₇–K/D

32

36

30

I

Key/Data: In Direct Control Mode, when this signal goes HIGH, the DCP

initiates a key-data input sequence as if a Clear E (or D) Key through the

Master Port command had been entered. The level on AUX -E/D will

6

determine whether the subsequently entered clear-key bytes are written into

the E Key Register (E/D HIGH) or the D Key Register (E/D LOW).

AUX -K/D and AUX -S/S are mutually exclusive control lines. When one

7

5

goes active HIGH, the other must be inactive (LOW) and remain in this state

until the ﬁrst signal returns to an inactive state. Whenever a transition occurs

on C/K (switching between Direct Control Mode and Multiplexed Control

Mode) both of these signals must be inactive (LOW).

AUX₂

BSY

–

8

9

3

4

O

0

Busy: In Direct Control Mode, this active LOW status output gives a

hardware indication that the ciphering algorithm is in operation. This status

line is driven by the BSY bit in the Status Register, such that when the BSY

bit is “1” (active), AUX -BSY is LOW.

2

AUX₃–CP

10

Command Pending: In Direct Control Mode, this active LOW status output

gives a hardware indication that the DCP is ready to accept input of key

bytes following a LOW-to-HIGH transition on AUX -K/D. This signal line is

7

driven by the CP bit in the Status Register, such that when the CP bit is “1”

(active), AUX -CP is LOW.

3

ASTB

11

12

13

7

I

Auxiliary Port Strobe: The rising edge of ASTB strobes the key-data on

pins AUX -AUX into the appropriate internal key register in Multiplexed

7

0

Control Mode (C/K LOW). This input is ignored unless AFLG and C/K are

both LOW. One byte of key-data (most signiﬁcant byte ﬁrst) is entered on

each ASTB .

3-32

Tundra Semiconductor Corporation

CA95C68/18/09

Cont'd

Table 3-2 : Pin Description

95C68/18

95C09

Symbol

TYPE

Name and Function

PDIP PLCC PLCC TQFP

AFLG

10

12

–

11

13

–

11

14

1

5

O

Auxiliary Port Flag: This active LOW output signal indicates that the DCP is

expecting key-data to be entered on the Auxiliary Port Bus. This can occur

only when C/K is LOW (Multiplexed Control Mode) and a Load Key Through

AUX Port command has been entered.

AFLG will remain active (LOW)

during input of all eight bytes, and will go inactive with the falling edge of the

eighth ASTB .

PAR

8

O

Parity: The DCP checks all key bytes for correct (odd) parity as they are

entered through either the Master Port (Multiplexed or Direct Control Mode)

or the Auxiliary Port (Multiplexed Control Mode only). If any key byte contains

even parity, the PAR bit in the Status Register is set to a “1” and PAR goes

active (LOW). (See Parity Checking of Keys.). The Parity bit is the least

signiﬁcant bit of the key byte.

OPTION

39

I

Option: (For CA95C09) This input allows the user to conﬁgure the Master

Port Control interface to function as either a CA95C68 or a CA95C18. When

the OPTION pin is tied to V , the device will function with the interface of a

DD

CA95C68. Conversely, tying the OPTION pin to V will cause the DCP to

SS

function as a CA95C18. This OPTION pin must be tied to either V or V

,

SS

DD

or erratic operation of the device will occur. The CA95C09 DCP will perform

identically to the CA95C68 or the CA95C18 (depending on the OPTION pin)

with the only difference being the order of the signal names on the device

package.

V

40

44

44,22

2, 12

16,

38

PWR

GND

Power Supply: +5 Volts.

DD

SS

1, 20

1, 22

6, 17

28,

40

Ground: 0 Volts.

23,

34

Tundra Semiconductor Corporation

3-33

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-3a : AC Characteristics (T + 0 to 70° C, V = +5.0V ± 5%, V = 0V)

A

DD

SS

Number

Clock

Description

t

CLK Width HIGH (t

)

1

2

3

WH

CLK Width LOW (t

)

WL

CLK HIGH to Next Clock HIGH (Clock Cycle, t )

C

Reset

t

MRD • MWR LOW to MRD • MWR HIGH (Reset Pulse Width), (Note 11)

5

Direct Control Mode

t

S/S LOW to C/K HIGH (Setup), (Note 11)

K/D LOW to C/K HIGH (Setup), (Note 11)

C/K HIGH to S/S HIGH (Note 11)

C/K HIGH to K/D HIGH (Note 11)

S/S LOW to E/D INVALID (Hold)

E/D SETUP to K/D HIGH (Setup) (Note 11)

K/D HIGH • CLK ↓ to CP LOW

K/D LOW to E/D INVALID (Hold)

K/D LOW to S/S HIGH

9

10

11

12

13

14

15

17

18

19

20

21

23

24

25

27

28

29

30

S/S LOW to K/D HIGH

E/D SETUP to S/S HIGH (Setup), (Note 11)

S/S HIGH • CLK ↓ to MFLG

(

) LOW (Port Input Flag)

SFLG

S/S LOW to E/D INVALID (Hold) (Note 11)

CLK LOW to BSY LOW

CLK LOW to BSY HIGH

ALGORITHM completed • CLK ↓ to MFLG ( SFLG ) LOW (Port Output Flag)

S/S LOW • CLK ↓ to MFLG ( SFLG ) HIGH (Port Input Flag), (Note 3)

CLK ↓ to K/D HIGH (Notes 11, 16)

CLK ↓ to S/S HIGH (Notes 11, 16)

Multiplexed Control Mode - Master Port

t

For CA95C68: MALE Width (HIGH)

For CA95C18:MAS Width (LOW)

32

34

35

36

37

For CA95C68: MCS LOW to MALE LOW (Setup)

For CA95C18: MCS LOW to MAS HIGH (Setup)

For CA95C68: MALE LOW to MCS HIGH (Hold)

For CA95C18: MAS HIGH to MCS HIGH (Hold)

For CA95C68: Address INVALID to MALE LOW (Address Setup Time)

For CA95C18: Address INVALID to MAS HIGH (Address Setup Time)

For CA95C68: MALE LOW to Address INVALID (Address Hold Time)

For CA95C18: MAS HIGH to Address INVALID (Address Hold Time)

3-34

Tundra Semiconductor Corporation

CA95C68/18/09

Table 3-3b : AC Characteristics (T = 0 to 70°C, V = +5.0V ± 5%, V = 0V

A

DD

10 MHz Limits 16 MHz Limits 20 MHz Limits 25 MHz Limits 33 MHz Limits

Min Max Min Max Min Max Min Max Min Max

SS

Number

5 MHz Limits

Min Max

Unit

Clock

t

85

–

40

–

27

–

20

_

–

17

–

13

–

ns

1

2

3

85

40

27

20

50

17

40

13

30

200

100

62.5

Reset

t

3t

–

3t

–

3t

–

3t

–

3t

–

3t

–

ns

5

C

Direct Control Mode

t

–

t

–

t

–

t

–

t

–

t

–

ns

9

C

10

11

12

13

14

15

17

18

19

20

21

23

24

25

27

28

29

30

C

2t

5

2t

3

C

40

20

15

10

t

C

–

75

–

60

–

45

–

40

–

5

–

5

–

1

30

–

3

–

3

–

1

10

–

40

–

20

–

15

–

10

–

75

–

60

–

45

–

40

–

30

–

10

–

40

–

20

–

15

–

10

–

75

100

75

60

75

60

45

60

45

40

50

40

30

40

30

10

–

3

t -25

3

t -25

3

t -25

1

t -20

t -13

C

3

t -25

3

t -25

3

t -25

C

1

t -20

C

t -20

C

t -15

C

Multiplexed Control Mode - Master Port

t

75

–

50

–

30

–

20

–

12

–

6

–

ns

32

34

35

36

37

25

–

15

–

5

–

0

–

0

–

0

–

ns

35

–

30

–

20

–

15

–

10

–

6

–

ns

35

–

30

–

20

–

15

–

10

–

5

–

ns

35

–

30

–

20

–

15

–

15

–

8

–

ns

Tundra Semiconductor Corporation

3-35

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-3a (con’t): AC Characteristics (T + 0 to 70° C, V = +5.0V ± 5%, V = 0V)

A

DD

SS

Number

Description

Master/Slave Port Read/Write

t

For CA95C68: MCS LOW to MRD , MWR LOW (Select Setup), (Note 4)

For CA95C18: MCS LOW to MDS LOW (Select Setup), (Note 4)

For CA95C68/18: SCS LOW to SDS LOW (Select Setup)

40

41

For CA95C68: MRD , MWR HIGH to MCS HIGH (Select Hold), (Note 4)

For CA95C18: MDS HIGH to MCS HIGH (Select Hold), (Note 4)

For CA95C68/18: SDS HIGH to SCS HIGH (Select Hold)

t

MR/W VALID to MDS LOW (Setup)

MDS HIGH to MR/W INVALID (Hold)

42

43

44

For CA95C68: MRW LOW to MRW HIGH (Width-Write)

For CA95C68: MRD , LOW to MRD HIGH (Width-Read)

For CA95C18: MDS LOW to MDS HIGH (Width-Write, Read)

For CA95C68/18: SDS LOW to SDS HIGH (Read, Write)

t

For CA95C68: CLK LOW to MWR HIGH (Notes 11,16)

For CA95C68: CLK LOW to MRD HIGH (Notes 11, 16)

For CA95C18: CLK LOW to MDS HIGH (Notes 11, 16)

45

For CA95C68/18: CLK LOW to SDS HIGH (writes to the slave port) (Notes 11, 16)

For CA95C68/18: CLK LOW to SDS HIGH (reads from the slave port) (Notes 11, 16)

For CA95C68: MRD , MWR HIGH to MRD , MWR LOW (Data Strobe Recovery Time)

For CA95C18: MDS HIGH to MDS LOW (Data Strobe Recovery Time)

For CA95C68/18: SDS HIGH to SDS LOW (Data Strobe Recovery Time)

46

t

For CA95C68: Write Data VALID to MWR (SDS ) HIGH (Write Setup Time)

For CA95C18: Write Data VALID to MDS (SDS ) HIGH (Write Setup Time)

47

48

For CA95C68: MWR HIGH to Write Data INVALID (Hold Time)

For CA95C18: MDS HIGH to Write Data INVALID (Hold Time)

For CA95C68/18: SDS HIGH to Write Data INVALID (Hold Time)

t

For CA95C68: MRD LOW to Read Data VALID (Read Access Time) (Note 15)

For CA95C18: MDS LOW to Read Data VALID (Read Access Time) (Note 15)

For CA95C68/18: SDS LOW to Read Data VALID (Read Access Time) (Note 15)

49

t

For CA95C68: MRD (SDS ) HIGH to Read Data INVALID (Hold Time)

For CA95C18: MDS (SDS ) HIGH to Read Data INVALID (Hold Time)

50

51

52

53

54

55

57

58

For CA95C68: MRD , MWR , (SDS ) LOW • CLK ↓ to MFLG ( SFLG ) HIGH (Last Strobe), (Note 5)

For CA95C18: MDS , (SDS ) LOW • CLK ↓ to MFLG ( SFLG ) HIGH (Last Strobe), (Note 5)

For CA95C68: MWR HIGH • CLK ↓ toCP HIGH (Note 4,11), (Last Strobe-Key Load)

For CA95C18: MDS HIGH • CLK ↓ to CP HIGH (Note 4,11), (Last Strobe-Key Load)

For CA95C68: MRD , MWR (SDS ) HIGH to S/S LOW (Hold Time) (Note 11)

For CA95C18: MDS (SDS ) HIGH to S/S LOW (Hold Time) (Note 11)

For CA95C68: MWR HIGH • CLK ↓ to PAR VALID (Key Write)

For CA95C18: MDS HIGH • CLK ↓ to PAR VALID (Key Write)

For CA95C68: S/S HIGH to MRD , MWR , (SDS ) LOW (Setup Time) (Note 11)

For CA95C18: S/S HIGH to MDS , (SDS ) LOW (Setup Time) (Note 11)

MRD , MWR HIGH to MALE HIGH

MDS HIGH to MAS LOW

MALE LOW to MRD , MWR LOW

MAS HIGH to MDS LOW

3-36

Tundra Semiconductor Corporation

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-3b (con’t): AC Characteristics (T = 0 to 70°C, V = +5.0V ± 5%, V = 0V)

A

DD

10 MHz Limits 16 MHz Limits 20 MHz Limits 25 MHz Limits 33 MHz Limits

Min Max Min Max Min Max Min Max Min Max

SS

Number

5 MHz Limits

Min Max

Master/Slave Port Read/Write

Unit

t

30

–

20

–

10

–

5

–

0

–

0

–

ns

40

20

10

t

35

–

30

–

20

–

10

–

5

–

3

–

ns

41

t

35

–

30

–

20

–

15

–

10

15

–

3

5

–

ns

42

43

44

140

–

70

–

50

–

35

–

30

–

15

24

19

–

ns

t

5

t -25

5

t -25

5

t -25

2

t -25

2

t -25

0

1

t -20

ns

45

C

t -25

t -15

C

t -25

t -20

C

t -25

t -20

t -16

C

t -25

C

t -25

C

t -25

C

t -20

C

t -20

C

t -8

C

30

–

20

–

15

–

10

–

10

–

10

–

ns

46

t

60

–

30

–

20

–

15

–

10

–

5

–

ns

47

48

20

–

20

–

15

–

15

–

10

–

3

–

ns

t

–

60

–

50

–

45

–

35

–

35

–

27

23

ns

49

t

5

20

5

20

5

20

5

20

5

20

5

20

ns

50

51

52

53

54

–

75

–

50

–

40

–

35

–

30

–

15

ns

–

75

–

50

–

40

–

35

–

30

–

15

ns

t

–

t

–

t

–

t

–

t

–

t

–

ns

C

–

75

–

50

–

40

–

35

–

30

–

20

ns

t

–

t

–

t

–

t

–

t

–

t

C

–

ns

55

C

140

70

30

20

10

15

57

t

80

–

40

–

20

–

20

–

20

–

10

–

ns

58

3-37

Tundra Semiconductor Corporation

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-3a (con’t): AC Characteristics (T + 0 to 70° C, V = +5.0V ± 5%, V = 0V)

A

DD

SS

Number

Description

Auxiliary Port Key Entry

t

ASTB LOW to ASTB HIGH (Width)

61

62

63

64

65

66

67

CLK LOW to ASTB HIGH (Notes 11, 16)

ASTB HIGH to Next ASTB LOW (Recovery Time)

Write-Data VALID to ASTB HIGH (Data Setup TIme)

ASTB HIGH to Write-Data INVALID (Data Hold TIme)

ASTB HIGH • CLK ↓ toPAR VALID

ASTB LOW • CLK ↓ to AFLG HIGH (Last Strobe)

3-38

Tundra Semiconductor Corporation

CA95C68/18/09

Table 3-3b (con’t): AC Characteristics (T = 0 to 70°C, V = +5.0V ± 5%, V = 0V)

A

DD

10 MHz Limits 16 MHz Limits 20 MHz Limits 25 MHz Limits 33 MHz Limits

Min Max Min Max Min Max Min Max Min Max

SS

Number

5 MHz Limits

Min Max

Auxiliary Port Key Entry

Unit

t

80

5

–

40

–

30

–

20

–

20

–

15

–

ns

61

62

63

64

65

66

67

t -20

C

5

t -20

C

5

t -20

C

5

t -20

C

5

t -20

C

-12

8

t -20

C

30

40

20

–

20

–

15

–

10

15

–

10

5

–

3

–

5

–

3

–

75

50

40

35

–

30

–

25

20

–

Notes:

1) All input transition times assumed <5ns, except clock which is <3ns (for 25 and 33MHz timing).

2) The appropriate input ﬂag ( ^MFLG, ^SFLG, ^AFLG) goes active LOW after 1 CLK ↓ +30ns from the writing of a “Load” or

“Start” command.

3) When ^S/S goes inactive (LOW) in Direct Control Mode, the ﬂag associated with the Input Port will turn off.

4) Direct Control Mode only ( ^MCSmust be LOW for one falling edge during a read/write cycle).

5) In Cipher Feedback, the Port Flag ( ^MFLGor ^SFLG) will go inactive following the leading edge of the ﬁrst data strobe

( ^MRD, ^MWR, ^MDS, or ^SDS), in all other modes and operations, the ﬂags go inactive on the eighth data strobe.

6) Do not change ^K/D until CP is inactive (HIGH).

7) Do not change E/D until MFLG ( SFLG ) is inactive (HIGH).

8) In Cipher Feedback, ^BSYmust be inactive (HIGH) before ^S/S goes inactive (LOW).

9) AFLG must go active (LOW) before ASTB goes active (LOW).

10) t is the clock width LOW (number t ).

WL

2

11) t is the clock cycle time (number t ).

C

3

12) All output timing speciﬁcations reﬂect the following: High output >1.5V, Low output <1.5V.

13) All output timings assume C = 50pF.

LOAD

14) When operating in Direct Control Mode, you must ensure that the K/D input is valid one clock cycle before you begin to load

the key, or perform any data operations with the device.

15) Timing numbers for parameter t with C

= 25 pF are shown below for a 33 MHz device:

49

LOAD

For CA95C68: MRD LOW to Read Data VALID (Read Access Time): 23.5 ns

For CA95C18: MDS LOW to Read Data VALID (Read Access Time): 23.5 ns

For CA95C68/18: SDS LOW to Read Data VALID (Read Access Time): 19 ns

16) These input signals must be externally synchronized to the CA95C09’s clock. As a result, there is less timing margin as the

frequency increases (ie: @ 33 MHz). Designers should review these timing parameters early on in the design cycle to ensure

that their interface logic to the CA95C09/18/68 will be able to meet these timing requirements.

Tundra Semiconductor Corporation

3-39

CA95C68/18/09

Tundra Semiconductor Corporation

t

2

t

1

CLK

CA95C18 CA95C68

t

3

MAS,

MWR

t

5

MDS,

MRD

Figure 3-8 : CA95C68/18 Clock and Reset Timing

CLK

C/K

t

11

20

t

23

t

13

AUX

S/S

-

5

t

9

30

t

12

t

18

t

19

AUX

-

t

7

10

t

K/D

29

t

17

14

AUX

E/D

-

6

t

15

t

52

AUX

CP

-

3

t

24

25

AUX

-

2

BSY

t

21

t

28

MFLG

SFLG

(INPUT PORT)

t

51

27

MFLG

SFLG

(OUTPUT PORT)

KEY LOADING

DATA CIPHERING

Figure 3-9 : CA95C68/18 Control and Status Signals Timing (Direct Control Mode)

3-40

Tundra Semiconductor Corporation

CA95C68/18/09

CLK

t

32

t

57

t

58

MALE

MCS

t

34

t

35

t

37

36

ADDRESS

DATA OUT

MP (7-0)

READ

t

50

t

49

45

MRD

t

37

44

36

ADDRESS

DATA IN

MP (7-0)

t

47

t

48

WRITE

t

45

MWR

t

44

Figure 3-10 : CA95C68 Master Port, Multiplexed Control Mode Read/Write

CLK

t

55

1

S/S

CP

t

53

t

52

1

t

51

MFLG

SFLG

t

41

1

t

40

MCS

SCS

WRITE

DATA

MP (7-0)

SP (7-0)

t

45

48

t

47

MRD

MWR

SDS

t

50

t

44

46

READ

DATA

MP (7-0)

SP (7-0)

t

49

PAR

54

1

These signals are only used for

Read/Write Timing in Direct Control

Mode of operation.

Figure 3-11 : CA95C68 Master (Slave) Port Read/Write Timing

Tundra Semiconductor Corporation

3-41

CA95C68/18/09

Tundra Semiconductor Corporation

CLK

t

67

62

AFLG

BYTE 1

BYTE 8

AUX (7-0)

t

65

t

64

t

61

ASTB

PAR

t

63

t

66

t

66

Figure 3-12 : CA95C68/18 Auxiliary - Port Key Entry Timing

CLK

t

32

MAS

MCS

t

34

t

35

t

37

36

ADDRESS

DATA OUT

MP (7-0)

MR/W

MDS

t

50

READ

42

t

49

t₄₅

t

43

t

37

44

36

ADDRESS

DATA IN

MP (7-0)

MR/W

t

47

t

48

t

42

WRITE

t

45

t

43

MDS

t

44

Figure 3-13 : CA95C18 Master Port, Multiplexed Control Mode, Read/Write Timing

3-42

Tundra Semiconductor Corporation

CA95C68/18/09

CLK

t

55

1.

S/S

t

53

t

52

1.

CP

MFLG

SFLG

t

51

t

41

1.

t

40

MCS

SCS

t

42

t

43

MR/W

WRITE

DATA

MP (7-0)

SP (7-0)

t

45

48

t

47

MDS

SDS

t

50

t

44

46

READ

DATA

MP (7-0)

SP (7-0)

t

49

PAR

54

1.

These Signals are only used for Read/Write timing in Direct Control Mode of operation.

Figure 3-14 : CA95C18 Master (Slave) Port Read/Write Timing

Tundra Semiconductor Corporation

3-43

CA95C68/18/09

Tundra Semiconductor Corporation

Table 3-4 : DC Characteristics (T = 0 to 70˚C, V = +5.0V ± 5%, V = 0V)

A

DD

SS

Limits

Test

Conditions

Symbol

Parameter

Units

µA

Min

Max

+1.0

I

Input leakage current

0 V ≤ V ≤ V

-1.0

IL

IN

DD

Output leakage current

Operating supply current

Standby supply current

0 V ≤ V ≤ V

-10.0

+10.0

3.0

µA

OZ

IN

DD

–

mA/MHz

µA

DDOP

DDSB

V

=V or V

SS

100.0

IN

DD

= 5.50V, Outputs open

DD

V

Input low voltage

Note 2

Note 1

-0.3

2.0

-0.3

2.1

0.4

–

0.8

V

pF

IL

Input high voltage

V

+ 0.3

IH

DD

Schmitt trigger input low voltage

Schmitt trigger input high voltage

Schmitt trigger hysteresis

Output low voltage

0.7

TL

TH

HY

OL

OH

V

–

DD

I

= 4.0mA

= -4.0mA

0.4

–

OL

Output high voltage

2.4

–

OH

C

Maximum input capacitance for any input or bidirectional pin.

10

IN

Note:

1) Applies to the following inputs:

For CA95C68: CLK, C/K, MCS , MRD , MWR , MALE, SCS , SDS , ASTB .

For CA95C18: CLK, ^C/K, MCS , MAS , MDS , MR/W, SCS , SDS , ASTB .

For CA95C09: CLK, DCM, MCS , MRD _ MDS , MALE_MAS , MWR _MR/W, SCS , SDS , ASTB , OPTION.

2) Applies to the following inputs: MP , SP , AUX .

7-0

Table 3-5 : Recommended Operating Conditions

DC Supply Voltage (V

+4.5V to +5.5V

0.5 W

)

DD

Power Dissipation (P ), (Note 1)

DD

0 to 70˚ C

Ambient Operating Temperature (T Commercial)

A

Note:

1) The power dissipation ﬁgure is based on typical internal logic dissipation plus the worst case set of outputs simultaneously

active with maximum rated loads.

Table 3-6 : Absolute Maximum Ratings

DC Supply Voltage (V

)

-0.3 to +7.0V

-10 to +10 mA

-65˚ to +150˚C

DD

Input Voltage (V

)

IN

DC Input Current (I

)

IN

Storage Temperature, plastic (T

)

STG

Stresses beyond those listed above may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of this speciﬁcation

is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

3-44

Tundra Semiconductor Corporation

CA95C68/18/09

FUNCTIONAL DESCRIPTION

Multiple Key Registers

The design of the DCP, as shown in Figure 3-1 is optimized

for high data throughput. The cryptography key bytes can be

written through both the Auxiliary and Master Ports. Three

56-bit, write-only key registers are provided for the Master

(M) Key, the Encryption (E) Key and the Decryption (D)

Key. Parity checking is provided on each incoming key byte.

Two 64-bit registers are provided for the initialization

Vectors (IVE and IVD) required for chained (feedback)

ciphering modes. Clear and cipher data bytes can be

transferred through both the Master and Slave Ports to the

Input Register; conversely, data can be transferred from the

Output Register to either port. Four 8-bit registers (Mode,

Command, Status and Mask) are accessible through the

Master Port for interfacing to a host microprocessor.

The DCP provides the necessary registers to implement a

multiple-key system. In such an arrangement, a single

Master Key, stored in the DCP M Key Register, is used only

to encrypt session keys for transmission to remote DES

equipment, and to decrypt session keys received from such

equipment. The M Key Register may only be loaded with

plain text through the Auxiliary Port, using the Load Clear M

Key command.

In addition to the Master Key Register, the DCP contains two

Session Key Registers; the E Key Register, used to encrypt

clear text, and the D Key Register, used to decrypt cipher

text. All three registers are loaded by writing commands

through the Master Port (Multiplexed Control Mode) into the

Command Register, and then writing the eight bytes of key

data to the port when the Command Pending bit = “1” in the

Status Register (see Command Description Section).

Algorithm Processing

The DCP's Algorithm Processing Unit (see Figure 3-1) is

designed to encrypt and decrypt data according to the

National Bureau of Standards Data Encryption Standard

(DES), as speciﬁed in Federal Information Processing

Standards Publication FIPS PUB 46 (1-15-1977).

Operating Modes: Multiplexed Control vs. Direct

Control

The DCP can be operated in either of two basic interfacing

modes, determined by the logic level on the C/^Kinput pin. In

Multiplexed Control Mode (C/K LOW), the DCP is internally

connected to allow a host CPU to directly address six

internal (Mode, Command, Status, Mask, Input, Output)

registers and thereby control the device by writing and

reading these registers. In Multiplexed Control Mode, the

Auxiliary Port is also enabled for entering keys.

The DES speciﬁes a method for encrypting 64-bit blocks of

clear data (plain text) into corresponding 64-bit blocks of

cipher text. The DCP offers four ciphering methods:

Electronic Code Book (ECB), Cipher Block Chaining

(CBC), one (CFB-1) and eight bit Cipher Feedback (CFB-8).

Electronic Code Block (ECB) is

a straightforward

implementation of the DES algorithm; 64 bits of clear data

in, 64 bits of cipher text out, with no cryptographic

dependence between blocks. Cipher Block Chaining (CBC)

also operates on blocks of 64 bits, but includes a feedback

step which chains consecutive blocks so that repetitive data

in the plain text (such as ASCII blanks) does not yield

identical cipher text. CBC also provides an error extension

characteristic which protects against fraudulent data

insertions and deletions. Cipher Feedback is an additive

stream cipher method in which the DES generates a pseudo

random binary stream which is then exclusive-ORed with the

clear text to form the cipher text. The cipher text is then fed

back to form a portion of the next DES input block. The DCP

implements both 1-bit and 8-bit cipher feedback which is

useful for low speed bit and byte oriented serial

communications.

If the logic level of C/K is brought HIGH, the DCP enters

Direct Control Mode, and the Auxiliary Port pins are

converted into direct hardware control or status signals that

are capable of instructing the DCP to perform a functionally

complete subset of its cipher processing at very high

throughputs. This operating mode is especially well suited

for ciphering data for high-speed peripheral devices.

Initialization

The DCP can be reset in several ways:

1) By the “Software Reset” command,

2) By a hardware reset:

(CA95C68) Assertion of MRD and MWR LOW

simultaneously for 3 clock cycles,

(CA95C18) Assertion of MAS and MDS LOW

simultaneously for 1 clock cycle.

3) By writing to the Mode Register,

4) By aborting any command.

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All these sequences are identical internally, except that

loading the Mode Register doesn't subsequently reset the

Mode Register. Once the reset process starts, the DCP is

unable to respond to any further commands for

approximately ﬁve clock cycles. If a power-up reset is used,

the rising edge of the reset signal should not occur until

aren't affected by data transfers. Any number of reads or

writes to this selected register can be accomplished without

intervening address cycles.

Loading Key and Initialization Vector (IV) Registers

The Key and Initialization Vector Registers are not directly

addressable through any of the DCP's ports, therefore keys and

vector data must be loaded through “command data

sequences” (see Command Description Section). Most of the

commands recognized by the DCP are of this type: a load or

read command is written to the Command Register through the

Master Port; the command processor responds by asserting the

Command Pending bit in the Status Register; the user then

either writes eight bytes of key or initial vector data through

the Master or Auxiliary Port, as selected by the speciﬁc

command, or reads eight bytes of initial vector data from the

Master Port.

approximately 1 ms after V

has reached the normal

DD

operating voltage. This delay time is required for internal

nodes to stabilize.

Master Port Read/Write Timing

The DCP's Master Port is designed to operate with

multiplexed address-data buses. The Master Port can be

optimized to interface with either a Latched Address Enable

(CA95C68) or a Strobed (CA95C18) microprocessor.

Several features of the CA95C68 interface should be

stressed.

In Direct Control Mode, only the E Key and D Key Registers

can be loaded; the M Key and IV Registers are inaccessible.

Loading the E and D Key Registers is accomplished by

•

The level on Master Port Chip Select ( ^MCS) is latched

internally on the falling edge of Master Port Address

Latch Enable (MALE) in Multiplexed Control Mode only.

This relieves external address decode circuitry of the

responsibility for latching chip select at address time.

asserting the proper state on the AUX -E/D input (HIGH for E

6

Key, LOW for D Key) and subsequently raising the AUX -K/D

7

input, indicating that key loading is required. The command

•

The levels on MP1, MP2 are also latched internally on the

falling edge of MALE and are subsequently decoded to

enable reading and writing of the DCP's internal registers

(Mode, Command, Status, Mask, Input and Output).

Again, this eliminates the need for external address

latching and decoding. The Mask Register is only

accessible when the DCP is programmed for one-bit CFB

mode via the Mode Register's Cipher Type bits.

processor will assert the AUX -CP (Command Pending)

3

signal, then the eight key bytes may be written through the

Master Port to the appropriate register. In Multiplexed Control

Mode, all Key and Initial Vector Registers, except the Master

(M) Key, may be loaded with encrypted, as well as clear, data.

Before loading an encrypted key or initial vector, the clear

Master Key must ﬁrst be loaded through the Auxiliary Port. If

the operation is a Load Encrypted command, the subsequent

data is written to either the Master or Auxiliary Port and is

routed ﬁrst to the Input Register and decrypted before being

stored in the speciﬁed Key or Initial Vector Register. After

loading the last byte of an encrypted key or initial vector, no

reading or writing of internal registers is allowed for the

subsequent 60 clock cycles.

•

Data transfers through the Master Port are controlled by

the levels and transitions on the Master Port Read ( ^MRD)

and Master Port Write ( ^MWR) pins. Master Port data

transfers do not disturb either the chip-select or address

latches, so that once the DCP and a particular register have

been selected, unlimited writing and reading of that

register can be done without intervening address cycles.

Given the required transfer control external to the DCP,

this feature could greatly speed up loading keys and data.

Parity Checking of Keys

Key bytes are considered to contain seven bits of key

information and one Parity bit. By DES designation, the low-

order bit is the Parity bit. The parity checking circuit is enabled

whenever a byte is written to one of the three key registers.

The output of the parity detection circuit is connected to

thePAR pin, as well as the state of this pin being reﬂected by

the Status Register PAR (S3) bit. Status Register bit PAR goes

to “1” whenever a byte with even parity (an even number of

“1”s) is detected. The Status Register also has a Latched

Parity bit (LPAR, S4) which is set to “1” whenever the Status

Register PAR bit goes to “1”. Once it is set to “1”, the LPAR

bit is not cleared until a reset occurs or a new Load Key

command is issued.

The CA95C18 interface is similar with the following

exceptions:

•

The level on ^MCSis latched internally on the rising edge

of ^MASin Multiplexed Control Mode only.

•

The levels on MP1, MP2 are also latched internally on the

rising edge of ^MASand are then decoded to enable reading

and writing of internal registers.

•

Data transfers through the Master Port are controlled by

Master Port Data Strobe ( ^MDS) and Master Port

Read/Write (MR/^W). The chip-select and address latches

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When an encrypted key has been loaded, the parity detect

logic operates only after the decrypted key is available. The

encrypted data is not checked for parity. The ^PARsignal will

reﬂect the state of the decrypted bytes on a byte-to-byte basis,

as they are clocked through the parity check logic on their

way to the appropriate key register. Therefore, the time ^PAR

indicates the status of a byte of decrypted key data may be as

short as four clock cycles. The LPAR bit in the Status Register

will indicate if any byte contained errors.

Dual Port, Master Port Clear Conﬁguration

In the dual port conﬁgurations, entering and removing data

is accomplished with both the Master and Slave Ports. In

the Master Port Clear conﬁguration, clear text for

encryption or clear text resulting from decryption can pass

only through the Master Port. Cipher text can be handled

only through the Slave Port. The direction of data ﬂow is

controlled either by the Encrypt/Decrypt bit (M4) in the

Mode Register, or by the Start Encryption or Start

Decryption commands. For encryption, clear data is written

through the Master Port to the Input Register, and cipher

data can be read from the Output Register through the Slave

Port at the appropriate time. If decryption is selected, the

process is reversed, cipher data being written to the Input

Register through the Slave Port, and the clear data being

read from the Output Register through the Master Port.

Data Flow

The Mode Register contains two bits, M2 and M3, which

control the ﬂow of data into and out of the DCP through the

Master and Slave Ports. Three basic conﬁgurations are

provided: single port, and two dual port conﬁgurations.

Single Port Conﬁguration

Dual Port, Slave Port Clear Conﬁguration

The simplest conﬁguration occurs when the Mode Register

Data Flow Control bits are set to Master Port only. Data to be

encrypted/decrypted (depending on the value loaded into the

Encrypt/Decrypt bit (M4) of the Mode Register) is written to

the Input Register through the Master Port. To facilitate

monitoring of the Input Register status, the ^MFLGsignal

goes LOW when the Input Register is not full. Clear or cipher

data is ready to be read by the host CPU through the Master

Port Output Register address when SFLG goes LOW.

Therefore, MFLG is redeﬁned as Master Input Flag and

^SFLGis redeﬁned as Master Output Flag.

This conﬁguration is identical to the Dual Port, Master Port

Clear conﬁguration described above, except that the

direction of ciphering is reversed. That is, all data written,

or read at the Master Port is cipher text, and all data at the

Slave Port is clear text

.

MASTER

KEY

MASTER

KEY

AUXILIARY

PORT

AUXILIARY

PORT

CA95C18

CA95C68

DCP

CA95C18

CA95C68

DCP

8-BIT

CPU BUS

MASTER

PORT

8-BIT

CPU BUS

MASTER

PORT

SLAVE

PORT

PERIPHERAL

DEVICE OR

BUFFER

COMMANDS

ENCRYPT AND DECRYPT

KEYS, CLEAR OR CIPHER TEXT

COMMANDS

ENCRYPT AND DECRYPT

KEYS, CLEAR TEXT

CIPHER TEXT

CIPHER OR

CLEAR TEXT

DUAL-PORT CONFIGURATION

MULTIPLEXED CONTROL

SINGLE-PORT CONFIGURATION

MULTIPLEXED CONTROL

HIGH SPEED

INTERFACE

AUXILIARY

PORT

COMMANDS

AND STATUS

CA95C18

CA95C68

DCP

8-BIT

CPU BUS

MASTER

PORT

SLAVE

PORT

PERIPHERAL

DEVICE OR

BUFFER

ENCRYPT AND DECRYPT

KEYS, CLEAR OR

CIPHER OR CLEAR

TEXT

^{CIPHER TEXT}DUAL-PORT CONFIGURATION

DIRECT CONTROL

Figure 3-15 : CA95C68 and CA95C18 Data Flow Options

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REGISTER DESCRIPTION

The registers in the DCP which can be directly addressed

through the Master Port are shown with their addresses in

Table 3-7. A brief description of these registers and others

not directly accessible is given below.

Description section. In this conﬁguration, ^MFLGgives the

status of the Input Register and ^SFLGthe Output Register.

Both the Master and Slave Ports are available for input and

output operations when the Conﬁguration bits are set to one

of the dual port conﬁgurations (M3,M2 = 00 or 01). When

M3,M2 = 01 (the default conﬁguration), the Master Port

handles clear data while the Slave Port handles ciphered

data. Conﬁguration M3,M2 = 00 reverses this assignment.

The data direction at any particular moment is controlled by

the Encrypt/Decrypt bit (M4).

Table 3-7 : Master Port Register Address

Cipher

Type

MRD MWR MR/W

Register

Addressed

C/K

MP2 MP1

MCS

9568

9568 9518

0

all

0

1

0

1

0

1

0

Input

Register

0

1

0

Output

Register

The Encrypt/Decrypt bit instructs the DCP algorithm

processor to encrypt or decrypt the data from the Input

Register using the ciphering method speciﬁed by the Cipher

Type bits. The Encrypt/Decrypt bit also controls the data

ﬂow direction within the DCP. For example, when the

Encrypt/Decrypt bit is “1” (encrypt) and the Conﬁguration

bits are “01” (Dual Port, Master Clear, Slave Encrypted),

clear data will enter the DCP through the Master Port and

encrypted data will be removed from the Slave Port. When

the Encrypt/Decrypt bit is set to “0” (decrypt), the direction

of data ﬂow reverses.

Command

Register

0

all

0

1

0

1

0

1

0

Status

Register

ECB/

CBC/

Input

Register

CFB-

8

0

ECB/

CBC/

1

0

1

0

Output

Register

The CFB-1 Mask Direction bit (M5) determines the direction

in which the Mask Register's bits and the input data are

interpreted. When the CFB-1 Mask Direction bit is set to “0”

the DCP will read the Mask Direction and data to be

ciphered from most signiﬁcant bit (MSB) to least signiﬁcant

bit (LSB). When the CFB-1 Mask Direction bit is set to “1”

the DCP will read the Mask Register and data from LSB to

MSB. The CFB-1 Mask Direction bit is only accessible

when the DCP is set to 1-bit Cipher Feedback mode via the

Mode Register.

CFB-

8

0

X

CFB-

1

X

0

1

X

0

1

Mask

Register

all

Mode

Register

all

No Register

Accessed

The CFB-1 Default Output bit (M6) deﬁnes the sense of

output bits which are masked off in the Mask Register. If the

Default Output bit is set to “1” then output bits, which are

masked (not used), will be set to “1”. If the Default Output

bit is cleared to “0” then output bits, which are masked (not

used), will be cleared to “0”.

1

all

X

1

0

1

0

1

0

Input

Register

Output

Register

Mode Register

Figure 3-16 shows the bit assignments in this 7-bit read/write

register. The Cipher Type bits (M1, M0) indicate to the DCP

which ciphering algorithm is to be used. After a reset, the

Cipher Type defaults to the Electronic Code Book.

Mask Register

The 8-bit read/write Mask Register determines which Input

and Output Register bits are signiﬁcant during One-bit

Cipher Feedback mode (CFB-1). If any Mask Register bit is

set to “1” then the corresponding bit of the Input Register

will be used as an input to the one-bit cipher feedback

encryption/decryption process and its one bit result will

likewise be placed in the corresponding bit of the Output

Register. If any Mask Register bit is cleared to “0” then the

corresponding bit of the Input Register will be ignored.

Conﬁguration bits (M3, M2) indicate which data ports are to

be associated with the Input and Output Registers and ﬂags.

When these bits are set to the Single Port Master Only

conﬁguration (M3, M2=10), the Slave Port is disabled and

no manipulation of Slave Port Chip Select (^SCS) or Slave

Port Data Strobe (^SDS) can cause data movement through

the Slave Port. All data transfers are accomplished through

the Master Port, as described more fully in the Functional

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In one-bit cipher feedback mode, if a single byte is written to

the Input Register (when requested by the DCP via the Input

Flag) then the ciphering algorithm unit will remain busy

until all bits in the Input Register, corresponding to set bits in

the Mask Register, are processed. For example, if the Mask

Register is set to “01101001” and the Mode Register's CFB-

1 Mask Direction bit is set for MSB to LSB Mask

followed by bits 5, 3, and 1. The corresponding results will

be placed in bits 6, 5, 3 and 1 of the Output Register. All

other bits in the Input Register will be ignored and all other

bits in the Output Register will be set to the state indicated

by the Default Output bit (M6) of the Mode Register. The

ciphering algorithm unit will remain busy until all four bits

are ciphered. Zero to eight bits of the Mask Register may be

set to “1”. If zero bits are set to “1” then any subsequent

writes to the Input Register will be ignored.

interpretation,

then

the

DCP

will

perform

Encryption/Decryption on bit 6 of the Input Register,

M7 M6 M5 M4 M3 M2 M1 M0

Reserved

Cipher Type

00 = Electronic Code Book (ECB) (default)

01 = 8-bit Cipher Feedback (CFB-8)

10 = Cipher Block Chaining (CBC)

11 = 1-bit Cipher Feedback (CFB-1)¹

*CFB-1 Default Ouput

1 = Masked output bits

are set (default)

0 = Masked output bits are

Port Configuration

cleared¹

00 = Dual Port, Master Encrypted, Slave Clear

01 = Dual Port, Master Clear, Slave Encrypted (default)

10 = Single Port, Master Only

Encrypt/Decrypt

1 = Encrypt

0 = Decrypt

11 = Reserved

*CFB-1 Mask Direction

0 = MSB to LSB₁

(default)

1 = LSB to MSB

*

The CFB-1 Mask Direction and Default Output bits are only accessible when the

DCP is in CFB-1 mode, otherwise these bits are high.

1.) This mode is Newbridge Microsystems specific.

Figure 3-16 : Mode Register Bit Assignments

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Table 3-9 : Implicit Command Sequences in Direct

Control Mode

Command Register

Data written to the 8-bit, write only Command Register

through the Master Port is interpreted as an instruction. A

detailed description of each command is given in the

Command Description section, and the commands and their

binary representations are summarized in Table 3-8 and

Table 3-9.

Aux - AUX - AUX -

7

6

5

C/K

Command Initiated

K/D

E/D

S/S

H

L

↑

L

↑

↓

L

Start Decryption

Start Encryption

Stop

H

X

L

Table 3-8 : Command Codes in Multiplexed Control Mode

Load Clear D Key through

Master Port

Hex

Command

Code

90

91

92

11

12

Load Clear M Key through Auxiliary Port

Load Clear E Key through Auxiliary Port

Load Clear D Key through Auxiliary Port

Load Clear E Key through Master Port

Load Clear D Key through Master Port

H

↑

H

L

Load Clear E Key through

Master Port

H

L

↓

X

L

End Load Key Command

Not Allowed

H

Data

AUX Pins become Key byte

Inputs

B1

B2

31

32

Load Encrypted E Key through Auxiliary Port

Load Encrypted D Key through Auxiliary Port

Load Encrypted E Key through Master Port

Load Encrypted D Key through Master Port

The Busy bit will be a “1” whenever the ciphering algorithm

unit is actively encrypting or decrypting data. For example,

the Busy bit is set in response to a Load Encrypted Key

command (the Command Pending bit will go HIGH as well)

or in the ciphering of regular text (indicated by the Start/Stop

bit being a “1”). If the ciphered data cannot be transferred to

the Output Register (due to the presence of data from a

previous ciphering cycle), then the Busy bit will remain a

“1”. The Busy bit will be “0” at all other times, including if

no ciphering is possible because no data has been loaded into

the Input Register.

85

84

A5

A4

Load Clear IVE through Master Port

Load Clear IVD through Master Port

Load Encrypted IVE through Master Port

Load Encrypted IVD through Master Port

8D

8C

A9

A8

Read Clear IVE through Master Port

Read Clear IVD through Master Port

Read Encrypted IVE through Master Port

Read Encrypted IVD through Master Port

39

41

40

C0

Encrypt with Master Key

Start Encryption

Start Decryption

Start

The Command Pending bit is set to “1” by any instruction

which requires the transfer of data to or from a non-

addressable internal register, such as when writing key bytes

to the E Key Register or reading bytes from the IVE Register.

Therefore, the Command Pending bit will be set following

all commands except the three Start Commands, the Stop

command and the software Reset command. The Command

Pending bit will return to an inactive state (“0”) after all eight

bytes have been transferred following Load Clear, Read

Clear or Read Encrypted commands. In addition the inactive

state (“0”) only returns after data has been entered, decrypted

and placed into the desired register following Load

Encrypted commands.

E0

00

Stop

Software Reset

Status Register

The bit assignments for the read-only Status Register are

shown in Figure 3-17. The PAR, AFLG, SFLG and MFLG

bits indicate the status of the similarly named output pins, as

do the Busy and Command Pending bits when the DCP is the

Direct Control Mode (C/K HIGH). In each case, the output

signal will be active LOW when the corresponding Status bit

is a “1”. The Parity bit indicates the parity of the most

recently entered key byte. The LPAR bit, on the other hand,

indicates whether any key byte with even parity has been

encountered since the last Reset or Load Key command.

The Start/Stop bit is set to “1” when one of the Start

commands is entered, and is reset to “0” whenever a reset

occurs or when a new command other than a Start is entered.

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S7 S6 S5 S4 S3 S2 S1 S0

Master Port Flag (MFLG)

0 = Inactive

1 = Active

Slave Port Flag (SFLG)

0 = Inactive

1 = Active

Auxiliary Port Flag (AFLG)

0 = Inactive

1 = Active

Parity (PAR)

0 = Odd parity

1 = Even Parity

Latched Parity (LPAR)

0 = All bytes had odd parity

1 = One or more bytes had even parity

Busy (BSY)

0 = Not busy

1 = Busy

Command Pending (CP)

0 = Inactive

1 = Active

Start/Stop

0 = Stop entered

1 = Start entered

Figure 3-17 : Status Register Bit Assignments

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Input Register

M,E,D Key Registers

The 64-bit, write-only Input Register is organized to appear

to the user as eight bytes of push-down storage. The number

of bytes stored in the register is monitored by a status circuit.

The register is considered full when eight bytes of data have

been loaded with the ECB or CBC ciphering algorithm in

use, or when one byte of data has been entered in either CFB

mode. It is considered empty when the data stored in it has

been or is being processed. The data in the register won't be

destroyed if the user attempts to write data into the Input

Register when it is full. Table 3-10 gives a summary of the

port ﬂag associated with this register depending on the mode

of operation.

There are three 64-bit, write-only key registers in the DCP;

the Master (M) Key Register, the Encrypt (E) Key Register,

and the Decrypt (D) Key Register. These registers are not

directly addressable, but can be loaded or read in response to

a command (See Command Descriptions). The Master key

can be loaded only with clear data through the Auxiliary

Port. The Encrypt and Decrypt Keys can be loaded as either

clear or cipher text through the Master or Auxiliary Port. If

the key data is encrypted, it is ﬁrst routed to the Input

Register where it is decrypted using the M Key, and then

written to the target key register from the Output Register.

Initialization Vector Registers

Output Register

Two 64-bit registers are provided to store feedback from

Cipher Feedback and Cipher Block Chaining modes of

operation. One Initialization Vector (IVE) Register is used

during encryption, the other (IVD) during decryption. Both

registers can be loaded with either clear or encrypted data

through the Master Port. If encrypted data is loaded, it is ﬁrst

decrypted before being written into the corresponding IV

Register. Both registers may be read out through the Master

Port as either clear or encrypted text (see Command

Description Section).

The 64-bit, read-only Output Register is setup to appear to

the user as eight bytes of pop-up storage. A status circuit

detects the number of bytes stored in the Output Register.

The register is considered empty when all the data stored in it

has been read out by the host CPU, and is considered full if it

still contains one or more bytes of output data. If an attempt

is made to read data from the Output Register when it is

empty, the output buffers will remain in a tri-state condition.

Table 3-10 : Association of Master Port Flag

( ^MFLG) and Slave Port Flag (^SFLG) with

Input and Output Registers

Encrypt/

Decrypt

M4

Port Conﬁguration

Input

Output

Register Register

M2

M3

Flag

MFLG

SFLG

MFLG

SFLG

MFLG

Flag

SFLG

MFLG

SFLG

MFLG

SFLG

0

1

0

1

0

1

0

1

0

1

0

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PROGRAMMING INSTRUCTIONS FOR MULTIPLEXED CONTROL MODE

4) One of the three Start commands is then written to the

Command Register to begin the ciphering session.

This section describes the registers that need programming

prior to using the DCP in ECB, CBC, or CFB ciphering

modes in Multiplexed Control Mode (MCM) of operation.

The programming ﬂow charts for each mode are

implemented for a single 8 bit port interface (see the

pipelining section for the dual port programming ﬂow chart).

5) Once a Start command is entered, the DCP will indicate

that it is ready for data input by activating the

corresponding ﬂag bit in the Status Register, as well as

the associated input ﬂag pin. Data can now be input

through the assigned Input Port. The two ﬂags, ^MFLG

and ^SFLG, which are associated with the Data Registers

can be sensed by hardware or software to know when

data is to be entered or removed from the DCP.

ECB Operation

Figure 3-18 illustrates the programming sequence for ECB.

1) A hardware or software reset must be implemented to

bring the device to a known state. A reset clears all bits

in the Status Register and programs the Mode Register

to it's default setting.

6) As soon as the Input ﬂag is active, the DCP is ready to

accept data (MSB ﬁrst). This bit is deactivated once eight

bytes of data have been entered.

7) The Output ﬂag goes active whenever the DES algorithm

is completed and data is ready to be removed from the

Output Register.

2) Program the Mode Register (see Figure 3-16) with the

cipher type and the port conﬁguration. For further

explanation see the Mode Register description.

8) Data is removed from the Output Port one byte at a time

with the most signiﬁcant byte ﬁrst. The Output ﬂag

becomes inactive upon the removal of the eighth byte.

3) The clear Encryption or Decryption Keys can be loaded

through either the Master or Auxiliary Ports. The

Command Pending bit in the Status Register will go

active once a command has been entered in the

Command Register. This bit will be active until all eight

bytes of the key have been loaded into the Input

Register of the DCP.

9) Loop through steps 5 through 9 until the ciphering

session should be terminated.

10) The session can now be terminated by issuing the Stop

command to the Command Register.

Upon termination, all remaining processed data is available in

the Output Register until the DCP is reset. This allows you to

enter the Stop command immediately upon entering the last

input block. When all the data has been removed from the

Output Register, all the ﬂags will be inactive. If the DCP is

restarted, any data that was not read out from the previous

ciphering session will be lost.

An alternative method to Step 3 is to load a Master Key

into the DCP through the Auxiliary Port. When this

command is entered the AFLG bit in the Status Register

will go active (^AFLGoutput pin will be active low) until

all 8 bytes have been entered. One key byte is loaded on

each rising edge of the Auxiliary Strobe (^ASTB).

A Load Encrypted Session Key command is then

entered into the DCP. The Session Key is then decrypted

by the Master Key before being stored in the

corresponding register. This use of the Master Key

allows you to enhance security by frequently changing

the session keys over a communication link.

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1.

RESET

PROGRAM MODE

REGISTER

2.

LOAD

3A.

3B.

4.

MASTER KEY

LOAD CLEAR

E/D KEY

3.

LOAD

ENCRYPTED

E/D KEY

ENTER

START COMMAND

IS

INPUT FLAG

ACTIVE

NO

5.

?

YES

ENTER DATA

6.

IS

OUTPUT FLAG

ACTIVE

NO

7.

?

YES

8.

REMOVE DATA

AT

NO

END OF

SESSION

9.

?

YES

ENTER

10.

STOP COMMAND

Figure 3-18 : Multiplexed Control Mode ECB Programming Flow Chart

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CA95C68/18/09

CBC Operation

Figure 3-19 illustrates the DCP programming sequence for

implementing the CBC method of ciphering. The

programming sequence is identical to the ECB programming

sequence except for an extra step included between steps 3

and 4. The Initialization Vectors (IVs) must be loaded before

beginning to cipher data. These IVs can be loaded in either

clear (step 3.1) or ciphered form (steps 3.1.A and 3.1.B).

1.

RESET

PROGRAM MODE

REGISTER

2.

LOAD

3A.

3B.

MASTER KEY

LOAD CLEAR

3.

E/D KEY

3.1

Load in eight bytes (MSB ﬁrst) of the

Initialization Vector through the Master Port.

LOAD

ENCRYPTED

E/D KEY

3.1.A(B) If the Initialization Vector is entered in encrypted

form, it is decrypted using the Decrypt Session

Key in ECB mode before being stored in the

appropriate register. Load the D Key (if not

already done) prior to executing an encrypted IV

command. The eight IV bytes are then loaded

into the Input Register and decrypted. The bits

(Cipher Type and Encrypt/Decrypt bit) in the

Mode Register are not affected by the decrypting

of the IVs.

LOAD

D KEY

3.1.A

3.1.B

LOAD CLEAR

IVE/IVD

3.1

LOAD

ENC. 1VE/IVD

ENTER

4.

START COMMAND

CFB Operation

IS

INPUT FLAG

ACTIVE

NO

5.

The ﬂow chart for the instruction sequence in CFB mode is

very similar to CBC mode. The DCP can be programmed to

execute in either 1-bit or 8-bit CFB mode. The Input and

Output Registers hold between one and 8 bits depending on

the cipher type and the setting of bits in the Mask Register.

In both modes, the IV is ﬁrst ciphered by the algorithm unit

and the result is then XORed with the input byte or bit (see

explanation of Mask Register for CFB-1 mode). The XOR

result is then loaded into the Output Register to be read out

by the CPU. This result is also shifted into the current IV

Register to be used in the next cipher session. When

operating in CFB mode, the Output Register must ﬁrst be

emptied before issuing a Stop command to the DCP. If you

must stop in the middle of inputting a block of data while

using ECB or CBC ciphering in Multiplexed Control Mode,

follow this instruction sequence to avoid erroneous data:

?

YES

ENTER DATA

6.

IS

OUTPUT FLAG

ACTIVE

NO

7.

?

YES

8.

REMOVE DATA

AT

END OF

SESSION

NO

9.

?

YES

ENTER

1) Issue a Stop command.

10.

STOP COMMAND

2) Read all available data from the Output Register.

3) Reload the Mode Register.

Figure 3-19 : Multiplexed Control Mode CBC

Programming Flow Chart

4) Issue a Start command.

5) Wait for the input ﬂag to go active and resume data

input.

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PROGRAMMING INSTRUCTIONS FOR DIRECT

CONTROL MODE

1) While in Multiplexed Control Mode, any key load

commands can be executed before switching back to

Direct Control Mode (DCM). Alternatively, the session

keys may be loaded while in DCM. When operating in

DCM, the DCP does not automatically latch the

This section describes how the DCP functions in Direct

Control Mode (DCM), (C/K pin is high). Only a subset of

the commands that are available in Multiplexed Control

Mode can be executed by controlling and monitoring the

status of the Auxiliary Port pins. While in DCM, you are

unable to access the Mode or Mask Register. The state of

the E/D and K/D pins should be held constant throughout

the entire key or data loading process. The state of the S/S

pin must also be held constant during the entire data

ciphering process.

Input/Output Register's address. Before beginning to load

any data into the Input Register, you must latch this

address using the address latch enable strobe. Driving the

K/^Dpin of the Auxiliary Port high sets up the DCP for key

entry (the S/S pin must stay low for the entire key loading

process). The level of the E/D pin determines whether the

Encryption or Decryption Session Key will be loaded. As

soon as the CP output pin goes low you may begin to

strobe in the eight key bytes using the Master Port Write

Strobe (MCS must be held low throughout the entire byte

loading process).

ECB Operation

2) Once the key loading process is complete, you may now

enter a Start command by driving the S/^Sline high. The

level on the E/D pin at this time will determine whether the

data is encrypted or decrypted. The levels on the K/D and

S/S) pins must be low throughout the data ciphering

process. The DCP responds to this command by lowering

the Input Port ﬂag (see Table 3-10).

A ﬂow chart of ECB operation in Direct Control Mode is

illustrated in Figure 3-20. A detailed explanation of each

step is described below:

In most DCM applications it is desirable to switch back

and forth between MCM and DCM; therefore, C/K must be

programmable. Before using the device, either a hardware

or software reset should be performed to set the device to

it's default state. If the default mode of operation and the

Direct Control Mode instruction set is sufﬁcient for your

requirements, then C/K may be permanently tied high. If

your application does not work in the default mode of

operation, the Mode Register must be programmed while

in Multiplexed Control Mode (which requires C/^Kto be

low).

3) Whenever the Input ﬂag is active, data can be entered

through the Master or the Slave Port, depending on the

selected mode of operation. To achieve the highest

throughput, the DCP must be conﬁgured to work in the

pipeline mode of operation. When the DCP has processed

the data, the Output ﬂag will become active and the data

may be removed from the Output Port.

4) Once all the data has been ciphered and read from the

output port, the DCP should be returned to the inactive

state by driving the S/^Spin low.

Note: You must remove all the data from the output port before

stopping the DCP or the data will be lost. Similarly, the key

reloading process can not begin until all the data from the

previous ciphering session has been removed from the output

port.

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CA95C68/18/09

PROGRAM

C / K LOW

RESET

1.

PROGRAM MODE

REGISTER

LATCH THE

INPUT / OUTPUT

REGISTER

ADDRESS

USE DCM TO

LOAD KEYS

NO

LOAD KEYS

YES

PROGRAM

C / K = HIGH

SET UP FOR

KEY ENTRY

2.

DOES

CP = LOW

NO

( AUX

?

)

3

YES

LOAD KEYS

ENTER

START COMMAND

IS

INPUT FLAG

ACTIVE

NO

?

YES

ENTER DATA

3.

IS

NO

OUTPUT FLAG

ACTIVE

?

YES

REMOVE DATA

AT

END OF

SESSION

NO

?

YES

ENTER

4.

STOP COMMAND

Figure 3-20 : Direct Control Mode ECB Programming Flow Chart

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CBC and CFB Operation

PROGRAM

C / K LOW

The instruction sequence to perform CBC or CFB operation

in Direct Control Mode (DCM) is similar to ECB mode of

operation. When operating in these modes, the C/^Kpin must

be programmable because the IV needed for CBC and CFB

can only be loaded while in Multiplexed Control Mode. If

you are using CFB-1 ciphering, the Mask Register must also

be loaded before entering DCM. When operating in this

mode you must ensure that a Stop command is not issued

while the Command Pending or Busy pins are active, or

when there is data still remaining in the Output Register. (see

Figure 3-21 for a programming ﬂow chart).

RESET

PROGRAM MODE

REGISTER

LOAD CLEAR

IVE / IVD

CFB-1

NO

MODE

?

YES

LOAD

MASK REGISTER

LATCH THE

INPUT / OUTPUT

REGISTER

ADDRESS

SET UP FOR

USE DCM TO

LOAD KEYS

NO

IS

NO

INPUT FLAG

ACTIVE

KEY ENTRY

?

YES

PROGRAM

C / K = HIGH

YES

DOES

NO

CP = LOW

( AUX

)

3

ENTER DATA

?

YES

SET UP FOR

KEY ENTRY

IS

LOAD KEYS

NO

OUTPUT FLAG

ACTIVE

?

DOES

CP = LOW

YES

NO

PROGRAM

( AUX

?

)

3

C / K = HIGH

REMOVE DATA

YES

LOAD KEYS

AT

NO

END OF

SESSION

?

ENTER

YES

START COMMAND

ENTER

STOP COMMAND

Figure 3-21 : Direct Control Mode CBC/CFB

Programming Flow Chart

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CA95C68/18/09

Maximum Throughput

The pipelined architecture of the DES DCPs allows

simultaneous input, ciphering, and output operations.

Maximum throughput is obtained when the device is

conﬁgured for one of the dual port conﬁgurations. Figure 3-

22 shows the timing for ciphering one block of 64 bits in

either ECB or CBC modes of encryption. The inputting of

the 64 bits of data takes 8 clock cycles to complete with one

data strobe being issued per clock cycle. This data must then

be transferred from the Input Register to the algorithm

processing unit and the ﬂags updated, which requires 5

additional clock cycles. The algorithm unit begins ciphering

concurrently with the transfer and once the ﬂags have been

updated another 64 bit block may be entered. The ciphering

of the ﬁrst block is completed after 18 clock cycles have

elapsed from the last byte having been written to the Input

Register. Another 5 clock cycles are required to transfer the

ciphered data to the Output Register and update ﬂags.

Transferring of data from the algorithm processing unit to

the Output Register can be performed concurrently with

loading new data into the DES algorithm unit. Removing the

data from the Output Register involves 8 clock cycles with

one data strobe per clock cycle. The whole procedure of

ciphering one block takes 39 cycles but because the different

operations can be overlapped, the DCP can process one

block every 18 clock cycles once fully loaded.

Encryption/Decryption in

progress in the algorithm

unit

Input

Bytes

8

Out

Flags

Output

8 Bytes

In

Flags

Clock

39 Finished reading 64-bit Block out of Output Port

31 Output Port FLAG becomes active

26 Algorithm Unit finishes processing block

13 Input Port FLAG becomes active for next Input Block

8

0

Algorithm Unit starts processing block

Start writing 64-bit Block into Input Port

0

8

13

26

31

39

Time in clock periods

Note: CA95C68 minimum clock period = 40 nanoseconds

Figure 3-22 : Detailed Timing of One Block

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Pipelining

Once the device has been initialized for dual port

conﬁguration, two data blocks are loaded into the device to

ﬁll the Output Register and the DES algorithm processing

unit. Now blocks of data can be strobed in and out

concurrently. When the ciphering session is completed the

DCP must be emptied by reading out the last two bytes.

START

IS

INPUT FLAG

ACTIVE

NO

Figure 3-23 illustrates

a programming ﬂow chart for

programming the DCP for pipelined mode of operation.

?

YES

Figure 3-24 shows the minimum timing conﬁguration for

maximum throughput for this device. The total time to

transfer “n” blocks is (n+1)x18+3 clock cycles. The DCP can

also be operated in pipelined mode when conﬁgured for

signal port operation. Once initialized, one block of data is

loaded into the device. Then, in a loop, one block of data is

strobed in and one block is read out. The ﬁrst block of data

loaded before entering the loop is ciphered while the input of

the second block is occurring.

LOAD FIRST

BLOCK OF DATA

IS

INPUT FLAG

ACTIVE

NO

?

YES

LOAD NEXT

BLOCK OF DATA

IS

OUTPUT FLAG

ACTIVE

NO

?

YES

READ

LOAD

OUTPUT DATA*

INPUT DATA

AT

END OF

SESSION

NO

?

YES

READ REMAINING

2 BLOCKS OF DATA

ENTER

STOP COMMAND

* DATA INPUT AND OUTPUT CONCURRENTLY

Figure 3-23 : Pipelining Operational Flow Chart

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8

5

8

18

In 1

Algorithm Flags

Out 1

Flags

5

In 2

Algorithm Flags

Out 2

Flags

In 3

Algorithm Flags

Out 3

Flags

Note: In this scheme, the reading out

of output block n leads the writing in

of input block n+2 by 5 clock cycles.

In 4

Algorithm Flags

Out 4

5

Flags

5

8

In 5

Algorithm Flags

Out 5

Flags

CLOCK

CYCLES

18

3

For n blocks, total number of clock pulses = (n+1)x18+3

Figure 3-24 : Pipelined Minimum Timing Operation

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COMMAND DESCRIPTION

AUX -K/D control input while the AUX -S/S input is LOW

All operations of the DCP result from command inputs,

which are entered in Multiplexed Control Mode by writing a

command byte to the Command Register. Command inputs

are entered in Direct Control Mode by raising and lowering

7

5

and the level on AUX -E/D determines which key register is

loaded.

6

When the command has been recognized, the Command

Pending bit (S6 in the Status Register) will go to “1” and in

Direct Control Mode AUX -CP will go active (LOW),

indicating that key loading may proceed. The host system

then writes exactly eight bytes to the Input Register through

the Master Port. When the Key Register has been loaded, the

Command Pending bit will return to “0”, and in Direct

the logic levels on the AUX - K/D, AUX -E/D and AUX -S/S

7

6

5

pins. Table 3-8 shows all commands that may be given in

Multiplexed Control Mode and Table 3-9 shows the subset

executable in Direct Control Mode.

3

Load Clear M Key Through Auxiliary Port (90 )

H

Control Mode the AUX -CP output will go inactive,

indicating that the DCP can accept the next command.

3

Load Clear E Key Through Auxiliary Port (91 )

H

Load Clear D Key Through Auxiliary Port (92 )

H

Load Encrypted E Key Through Auxiliary Port (B1 )

H

These commands override data ﬂow speciﬁcations set in the

Mode Register and cause the Master (M), Encrypt (E), or

Decrypt (D) Key Register to be loaded with eight bytes

written to the Auxiliary Port. Once the load command is

written to the Command Register, the Auxiliary Port ﬂag

( AFLG ) pin will go active (LOW), as well as the Auxiliary

Port Flag bit (S2) in the Status Register being set to “1”,

indicating that the device is able to accept key bytes at the

Auxiliary Port bus. In addition, the Command Pending bit

(S6) will go to “1” during the entire loading process.

Load Encrypted D Key Through Auxiliary Port (B2 )

H

These commands are only available in Multiplexed Control

Mode. They are similar to the Load Clear E (or D) Key

through Auxiliary Port commands, except that key bytes are

initially decrypted using the Electronic Code Book algorithm

and the Master (M) Key. The key bytes then pass through the

parity checking logic and into the appropriate key register.

The Command Pending bit (S6) will be “1” during the entire

decrypt-and-load operation. The Busy bit (S5) will be “1”

during the actual decrypting of the key.

When data has been setup on the Auxiliary Port pins, each

byte is written by placing an active LOW signal on the

Auxiliary Port Strobe ( ASTB ). The actual write occurs on

the rising edge of ^ASTB. The Auxiliary Port Flag ( ^AFLG)

will go inactive immediately after the eighth strobe goes

active (LOW). However, the Command Pending bit (S6) will

remain “1” for several more clock cycles, until the key

loading process is completed. All key bytes are checked for

correct (odd) parity as they are entered.

Load Encrypted E Key Through Master Port (31 )

H

Load Encrypted D Key Through Master Port (32 )

H

These commands (available in Multiplexed Control Mode

only) are similar in effect to Load Clear E (or D) Key

Through Master Port, except that key bytes are ﬁrst

decrypted using the Electronic Code Book algorithm and the

Master (M) Key. The bytes are then loaded into the target key

register, after having passed through the parity checking

logic.

Load Clear E Key Through Master Port (11 )

H

Load Clear D Key Through Master Port (12 )

H

The Command Pending bit (S6) will be “1” during the entire

decrypt-and-load operation. As well, the Busy bit (S5) will

be “1” during the actual decryption process.

These commands are available in both Multiplexed Control

and Direct Control Modes. They override the data ﬂow

speciﬁcations set in the Mode Register (bits M2 and M3) and

allow eight bytes of data to be written to the appropriate key

register through the Master Port. The input register must be

addressed before beginning to load the eight key bytes. In

Multiplexed Control Mode, the command is initiated by

writing the instruction to the Command Register. In Direct

Control Mode, the command is initiated by raising the

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CA95C68/18/09

Load Clear IVE Register Through Master Port (85 )

Read Encrypted IVE Register Through Master Port

H

(A9 )

H

Load Clear IVD Register Through Master Port (84 )

H

Read Encrypted IVD Register Through Master Port

These commands (available in Multiplexed Control Mode

only) are virtually identical to Load Clear E (or D) Key

Through Master Port, except that the data written to the Input

Register address is transferred to either the Initialization

Vector for Encryption (IVE) or Decryption (IVD) Register

instead of a Key Register and no parity checking takes place.

The Command Pending bit (S6) is a “1” during the entire

loading process.

(A8 )

H

The effect of these commands (in Multiplexed Control Mode

only) is to override the speciﬁcations set in the Mode

Register and to encrypt the contents of the speciﬁed

Initialization Vector Register using the Electronic Code Book

algorithm and the Encrypt (E) Key. The resulting eight bytes

of cipher text can be read from the Output Register through

the Master Port. The Busy bit (S5) will be “1” during the

encryption process, when it goes to “0, “the encrypted

initial vector bytes are ready to be read out. The Command

Pending bit (S6) will be “1” during the entire encryption-

and-output process, and will go to “0” when the eighth byte

is read out. The host system is responsible for reading out

exactly eight bytes.

Load Encrypted IVE Register Through Master Port

(A5 )

H

Load Encrypted IVD Register Through Master Port

(A4 )

H

These commands are similar to the Load Encrypted E (or D)

Key Through Master Port commands. The data ﬂow

speciﬁcation set in the Mode Register is overridden and the

eight initial vector bytes are decrypted using the Decryption

(D) Key and the Electronic Code Book algorithm. The

resulting clear initial vector bytes are routed into the

appropriate Initialization Vector Register, and no parity

checking occurs. The Busy bit (S5) does not go to “1” during

the decryption process, but Command Pending bit (S6) will

be “1” during the entire decryption-and-load operation.

Encrypt with Master (M) Key (39 )

H

This command (available in Multiplexed Control Mode only)

overrides the data ﬂow speciﬁcations set in the Mode

Register and causes the DCP to write eight bytes of data to

the Input Register via the Master Port. After the eighth byte

has been received, the data is encrypted using the Master (M)

Key and then routed to the Output Register, where it may be

read out through the Master Port. The Command Pending

(S6) and Busy (S5) bits are used to sense the three phases of

this operation. Command Pending goes to “1” as soon as the

Input Register can accept data. When exactly eight bytes

have been entered, the Busy bit will got to “1” until the

encryption process is complete. When Busy goes to “0”, the

encrypted data is available to be read out. Command Pending

will return to “0” when the eighth byte has been read.

Read Clear IVE Register Through Master Port (8D )

H

Read Clear IVD Register Through Master Port (8C )

H

The effect of these commands (available in Multiplexed

Control Mode only) is to override the data ﬂow speciﬁcations

set in the Mode Register and to allow the appropriate

Initialization Vector Register to be read from the Output

Register through the Master Port. When executing this

instruction, each IV Register appears as eight bytes of FIFO

storage. The ﬁrst byte of data will be available six clocks

after the loading of the Command Register. The Command

Pending bit will be set to “1” and will remain a “1” until

sometime after the eighth byte is read out. The host system

has the responsibility to read out exactly eight bytes.

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CA95C68/18/09

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Start Encryption (41 )

Stop (E0 )

H

The Stop command sets the Start/Stop bit (S7) in the Status

Register to “0.” This causes the input ﬂag ( MFLG or SFLG )

to become inactive and inhibits the loading of any further

data. Any ciphering in progress (Busy bit (S5) is “1” or

Start Decryption (40 )

H

Start (C0 )

H

The three “Start” commands begin normal data ciphering by

setting the Start/Stop bit (S7) in the Status Register to “1.”

The Start Encryption and Start Decryption commands

specify the ciphering direction by forcing the

Encrypt/Decrypt bit (M4) in the Mode Register to “1” or “0”,

respectively. Whereas Start uses the current state of the Mode

Register Encrypt/Decrypt bit, as speciﬁed in a previous

Mode Register load. When any Start command has been

entered, the port status ﬂag (MFLG or SFLG) associated

with the Input Register will become active (LOW),

indicating that data may be written to the Input Register to

begin ciphering.

AUX -BSY is active) will be completed and any data in the

2

Output Register will remain accessible (except in CFB

Mode). In either CFB Mode, the last byte of data must be

read out before issuing the Stop command.

In Direct Control Mode, the Stop command is implied when

the signal level on the AUX -S/S input goes from HIGH to

5

LOW.

Software Reset (00 )

H

This command is similar to a hardware reset (CA95C68:

MRD and MWR low, CA95C18: MAS and MDS low) in that

it forces the DCP back to its default conﬁguration, and all the

processing ﬂags go inactive. The default conﬁguration for

the Mode Register is: Electronic Code Book cipher type and

dual port conﬁguration with Master Port clear, Slave Port

encrypted.

In Direct Control Mode, the Start command is issued by

raising the level of the AUX -S/S input. If AUX -E/D is high

5

6

when AUX -S/S goes HIGH, the command is Start

5

Encryption; if AUX -E/D is low, it is Start Decryption.

6

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Tundra Semiconductor Corporation

CA95C68/18/09

CA95C68/18/09 NOTES

This listing describes known operating variants between the

CA95C68/18/09 devices and both the AMD AM9568/18 and

VLSI VM009 devices. Also contained here are some

CA95C68/18/09 operating idiosyncrasies.

4) Synchronization for CA95C68/18/09 and VM009

Read/Write: Compared to the VLSI VM009 device, the

CA95C68/18/09 has a narrower window in which the

read and write strobes must synchronize to the clock

input. The CA95C68/18/09 AC parameter in question is

t

which is speciﬁed as a minimum of 2ns and a

45

1) CA95C68/18/09 Reset: The CA95C68/18/09 device

does not operate in the default mode of operation until

one of the reset operations are performed on it. Either a

hardware reset, a software reset, or a write to the Mode

Register must be performed before beginning to

program the CA95C68/18/09 to ensure that the device is

operating in the default mode.

maximum of t -25ns. Therefore, the CA95C68/18/09

c

read and write strobes must be driven HIGH between 2

and 15ns after the falling edge of the clock if you are

using the DCP at 25MHz. With the VLSI device, the

read and write synchronization occurs on the rising edge

of the clock and there is only a 4ns region in which the

strobes can not go HIGH for any clock frequency.

2) CA95C68/18/09 Direct Control Mode: When the

CA95C68/18/09 is programmed for Direct Control

Mode (DCM) operation, the Input and Output Register

address and ^MCSmust be manually latched immediately

before or immediately after DCM is entered. The device

does not automatically address the Input and Output

Registers (Address 0) when DCM is entered. This

should be done before any operations are performed.

5) Clock Frequency: The clock input frequency for the

various devices are:

AM9568

1.0 MHz to 4.0 MHz

1.0 MHz to 3.1 MHz

AM9518

CA95C68/18/09 0 MHz to 33MHz

VM009 0 MHz to 33 MHz

3) CA95C68/18/09 Busy Bit in CFB-8 Cipher Mode:

When the CA95C68/18/09 is programmed for eight bit

cipher feedback (CFB-8), ciphering in either

6) One-Bit Cipher Feedback Mode: This is a mode of

encryption supported by the CA95C68/18/09 that the

AMD and VLSI devices do not provide.

Multiplexed Control or Direct Control Mode of

operation, the Busy bit (bit 5 in the Status Register) and

the ^BSYpin (AUX -BSY in DCM) go active before the

2

Input Register is addressed. The Busy bit and the BSY

pin go active immediately after the Mode Register is

programmed for the CFB-8 cipher type. This bit (and

pin in DCM) is not of great importance and should be

ignored in this mode of operation.

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7) Flag Output Assertion Timing Variant: The

AM9568/18 devices set and clear the ﬂag output lines

immediately after the corresponding event has occurred.

The CA95C68/18/09 devices synchronize all internal

events with respect to the falling edge of the clock input.

Therefore, the ﬂag output lines are set or cleared on the

next falling clock edge after the corresponding event has

occurred.

10) Key Parity in Direct Control Mode: The AM9568/18

erroneously indicates a parity error during the loading of

keys of correct parity in Direct Control Mode. The

CA95C68/18/09 devices do not indicate a parity error in

this scenario.

11) Encrypted Key Load Parity Variant: The AM9568/18

will clear a parity error regardless of whether the last

byte of an encrypted key load has a parity error. The

CA95C68/18/09 devices will indicate the parity of the

last byte of an encrypted key load correctly, and if

required, the parity error must be cleared by one of the

speciﬁed methods.

8) IVE in Pipelined CBC Mode of Encryption: The

AM9568/18 presents the previous IVE instead of the

current IVE during a read IVE operation after a series of

CBC encryptions in which more than one round of data

was in the encryption pipeline. In the CA95C68/18/09

devices, the correct IVE is presented for the pipelined

CBC mode encryption scheme.

12) Mode Register’s Encrypt/Decrypt Bit Status on a

Command Abort Reset: The AM9568/18 will not set

the Encrypt/Decrypt bit high if that bit is low and a

command is aborted. The CA95C68/18/09 devices will

reset this bit high when the Mode Register is reset

during a command abort sequence.

9) Direct Control Mode, Mode Register

Encrypt/Decrypt Bit Variant: In Direct Control Mode

(DCM), the AM9568/18 adjusts the sense of the Mode

Register’s Encrypt/Decrypt bit (M4) inconsistently;

based on whether encryption or decryption is performed.

The CA95C68/18/09 always sets the Encrypt/Decrypt

bit to be the same sense as the AUX -E/D input line in

6

this case.

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Tundra Semiconductor Corporation


型号：	CA95C18-16CP
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Data Encryption Circuit, MOS, PDIP40, PLASTIC, DIP-40 电信光电二极管电信集成电路
文件：	总42页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CA95C18-16CP [IDT]

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