CPS-1848 [IDT]
IDT Serial RapidIO Switch Feature ComparisonChart; IDT串行RapidIO交换机特性ComparisonChart
| 型号： | CPS-1848 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | IDT Serial RapidIO Switch Feature ComparisonChart |
| 文件： | 总1页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated DeviceTechnology
IDT Serial RapidIO® Switch Feature ComparisonChart
FEATURES
CPS-1848
CPS-1432
CPS/SPS-1616
CPS-6Q
/10Q
CPS-8
/ 12
/ 16
Tsi572
/ 574
/ 578
Tsi577
Tsi620
Performance and Configurability
Serial RapidIO specifications
2.1
240
√
2.1
160
√
2.1
80
√
1.3
60
√
1.3
1.3
20
√
1.3
30
√
1.3
40
√
1.3
30
√
1.3
40
√
1.3
80
√
1.3
40
√
1.3
50
√
Aggregate peak throughput (Gbps)
Full mesh non-blocking fabric
Asymmetric non-blocking fabric
Maximum of number of x4 ports
Maximum of number of x2 ports
Maximum of number of x1 port
Cut-through latency (ns)
100
√
12
8
4
6
10
2
3
4
2
4
8
4
3
18
18
14
14
8
16
16
190
16
190
8
190
√
12
16
190
√
8
110
√
8
16
110
√
16
110
6
110
100
100
100
190
√
110
Store and forward mode
√
√
√
√
√
√
√
√
Configurable by speed
Each Quad
Each Quad
CPS/SPS - Each Lane
Each Quad
Each Quad
Each Lane Pair
Each MAC
Each Quad
Each MAC
SerDes and Power
Power per 10 Gbps link (typical, mW)
Identical long and short reach power
Per port power down
<300
<385
CPS/SPS <440
<500
<500
<500
√
<500
√
<500
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Programmable transmit drive strength and pre-emphasis
Programmable receive equalization
On-die scope capability
√
√
√
√
√
√
√
√
√
Multicast and Routing
Per port multicast architecture
Parallel multicast engine with QoS support
Per port multicast masks/groups
8- and 16-bit addressing
√
√
√
√
√
√
√
√
√
8
√
8
√
8
√
8
√
8
40
√
40
√
40
√
40
√
40
√
10
√
10
√
10
√
√
√
√
√
√
√
√
√
√
√
Programmable watermarks on ingress buffers
RapidIO Standard and Non-Standard Features
Packet/trace/mirror/ filter for debug
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Traffic management through user selectable
scheduling algorithms
√
√
√
√
√
√
√
√
√
√
Receiver controlled flow control
Transmitter controlled flow control
Performance counters/monitors
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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√
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√
√
√
√
√
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√
√
Dedicated maintenance path for “5th priority”
Error Management features exceeding S-RIO specification
Error log (history) and broad error detection coverage
Link-layer AES-128 encryption
√
√
√
√
√
√
√
√
SPS on 4 1x Ports
BOM Reduction and Clocking Options
Clocking options (MHz)
156
156
156
156
156
√
156 or 125
156 or 125
156 or 125
No power-up sequence or ramp rate requirements
Run RapidIO at CPRI and OBSAI speeds
Lane swap for board design simplification
Debug packet generator
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Debug packet capture
Other Bridging and Unique features
Built-in hardware bridging from RapidIO to PCI
Built-in bridging options to non-SerDes FPGA
√
√
Package (mm)
29 X 29
25 x 25
21 X 21
27 X 27
27 X 27
19 X 19
19 X 19
19 X 19
21 X 21
21 X 21
27 X 27
21 X 21
27 X 27
GD_S-RIO Switches_REVB0311
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IDT THE ANALOG DIGITAL COMPANY
IDT Serial RapidIO Switch Feature Comparison
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