CSP2510DPGI8 [IDT]

TSSOP-24, Reel;


型号：	CSP2510DPGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	TSSOP-24, Reel
文件：	总9页 (文件大小：76K)
中文：	中文翻译
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IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

IDTCSP2510D

3.3V PHASE-LOCK LOOP

CLOCK DRIVER

ZERO DELAY BUFFER

DESCRIPTION:

FEATURES:

TheCSP2510Dis ahighperformance,low-skew,low-jitter,phase-lock

loop(PLL)clockdriver.Ituses a PLLtopreciselyalign,inbothfrequency

andphase,the feedback(FBOUT)outputtothe clock(CLK)inputsignal.

ItisspecificallydesignedforusewithsynchronousDRAMs.TheCSP2510D

operates at3.3V.

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

• No external RC network required for PLL loop stability

• Operates at 3.3V VDD

• tpd Phase Error at 166MHz: < ±150ps

• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz

• Spread Spectrum Compatible

One bank of ten outputs provide low-skew, low-jitter copies of CLK.

Outputsignaldutycyclesareadjustedto50percent,independentoftheduty

cycleatCLK.TheoutputscanbeenabledordisabledviathecontrolGinput.

Whenthe Ginputis high,the outputs switchinphase andfrequencywith

CLK;whentheGinputislow,theoutputsaredisabledtothelogic-lowstate.

UnlikemanyproductscontainingPLLs,theCSP2510Ddoesnotrequire

external RC networks. The loop filter for the PLL is included on-chip,

minimizingcomponentcount,boardspace,andcost.

• Operating frequency 50MHz to 175MHz

• Available in 24-Pin TSSOP package

Because it is based on PLL circuitry, the CSP2510D requires a

stabilization time to achieve phase lock of the feedback signal to the

referencesignal.Thisstabilizationtimeisrequired,followingpowerupand

application of a fixed-frequency, fixed-phase signal at CLK, as well as

followinganychanges tothe PLLreference orfeedbacksignals.The PLL

can be bypassed for the test purposes by strapping AVDD to ground.

TheCSP2510Disspecifiedforoperationfrom0°Cto+85°C. Thisdevice

is alsoavailable(onspecialorder)inIndustrialtemperaturerange(-40°C

to+85°C). See orderinginformationfordetails.

APPLICATIONS:

• SDRAM Modules

• PC Motherboards

• Workstations

FUNCTIONALBLOCKDIAGRAM

CLK

PLL

FBIN

AV^DD

FBOUT

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

0ºC TO 85ºC TEMPERATURE RANGE

OCTOBER 2001

2001 Integrated Device Technology, Inc.

DSC-5874/3

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

Rating

Max

Unit

VDD

SupplyVoltageRange

InputVoltageRange

Voltagerangeappliedtoany

outputinthehighorlowstate

Inputclampcurrent

–0.5to+4.6

–0.5to+6.5

–0.5 to VDD + 0.5

(1)

AGND

VDD

CLK

AVDD

VDD

(1,2)

IIK

–50

(VI <0)

IOK

TerminalVoltagewithRespect

to GND (inputs VIH 2.5, VIL 2.5)

±50

(VO <0 or

VO > VDD)

ContinuousOutputCurrent

±50

GND

(VO = 0 to VDD)

VDD or GND

TSTG

ContinuousCurrent

±100

– 65 to +150

+150

° C

StorageTemperatureRange

JunctionTemperature

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative-voltage ratings may be exceeded if the input and output

clamp-current ratings are observed.

3. The maximum package power dissipation is calculated using a junction temperature

VDD

FBIN

FBOUT

of 150°C and a board trace length of 750 mils.

TSSOP

TOP VIEW

CAPACITANCE

Parameter

Description

InputCapacitance

VI = VDD or GND

OutputCapacitance

VO = VDD or GND

LoadCapacitance

Min.

Typ. Max.

Unit

CIN

⎯

NOTE:

1. Unused inputs must be held HIGH or LOW to prevent them from floating.

RECOMMENDEDOPERATINGCONDITIONS

Symbol

VDD, AVDD

Description

Min.

Max.

3.6

Unit

Power Supply Voltage

OperatingFree-AirTemperature

+85

°C

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

PINDESCRIPTION

Terminal

Name

No.

Type

Description

CLK

Clockinput. CLKprovidestheclocksignaltobedistributedbytheCSP2510Dclockdriver. CLKisusedtoprovidethereferencesignal

totheintegratedPLLthatgeneratestheclockoutputsignals.CLKmusthaveafixedfrequencyandfixedphaseforthePLLtoobtainphase

lock. OncethecircuitispoweredupandavalidCLKsignalisapplied,astabilizationtimeisrequiredforthePLLtophaselockthefeedback

signaltoitsreferencesignal.

FBIN

Feedbackinput. FBINprovidesthefeedbacksignaltotheinternalPLL. FBINmustbehard-wiredtoFBOUTtocompletethePLL. The

integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.

Outputbankenable. GistheoutputenableforoutputsY(0:9). WhenGislow,outputsY(0:9)aredisabledtoalogic-lowstate. When

G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.

FBOUT

Feedbackoutput. FBOUTis dedicatedforexternalfeedback. Itswitches atthesamefrequencyas CLK. Whenexternallywiredto

FBIN, FBOUT completes the feedbackloop ofthe PLL.

Y (0:9) 3, 4, 5, 8, 9,

15, 16, 17,

Clockoutputs. Theseoutputsprovidelow-skewcopiesofCLK. OutputbankY(0:9)isenabledviatheGinput. Theseoutputscanbe

disabledtoalogic-lowstatebyde-assertingtheGcontrolinput.

20,21

AVDD

Power

Analogpowersupply. AVDD provides thepowerreferencefortheanalogcircuitry.Inaddition,AVDD canbeusedtobypass thePLL

fortestpurposes. WhenAVDD is strappedtoground, PLLis bypassedandCLKis buffereddirectlytothedeviceoutputs.

AGND

VDD

Ground Analogground. AGNDprovidesthegroundreferencefortheanalogcircuitry.

Power supply

6, 7, 18, 19 Ground Ground

2, 10, 14, 22 Power

GND

STATIC FUNCTION TABLE (AVDD = 0V)

DYNAMIC FUNCTION TABLE (AVDD = 3.3V)

Inputs

Outputs

Inputs

Outputs

CLK

Y(0:9)

FBOUT

CLK

Y(0:9)

FBOUT

running

runningin

phase with CLK

runningin

phase with CLK

runningin

phase with CLK

running

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

DCELECTRICALCHARACTERISTICSOVEROPERATINGFREE-AIRTEMPERA-

TURERANGE⁽¹⁾

Symbol

Description

Test Conditions

VDD

⎯

Min.

⎯

Typ.⁽²⁾Max.

Unit

VIK

InputClampVoltage

Input HIGH Level

InputLOWLevel

II = -18mA

⎯

– 1.2

⎯

VIH

VIL

⎯

0.8

⎯

IOH = -100μA

Min. to Max. VDD – 0.2

VOH

VOL

HIGH Level Output Voltage

LOWLevelOutputVoltage

IOH = -12mA

2.1

2.4

⎯

IOH = -6mA

⎯

IOL = 100μA

Min. to Max.

0.2

0.8

0.55

±5

IOL = 12mA

IOL = 6mA

InputCurrent

VI = VDD or GND

3.6V

μA

IDD

SupplyCurrent

VI = VDD or GND, AVDD = GND,

IO = 0, Outputs: LOW or HIGH

One input at VDD - 0.6V, other inputs at VDD or GND

3.6V

ΔIDD

Change inSupplyCurrent

3.3V to 3.6V

3.6V

⎯

500

μA

CPD

(3)

IDDA

PowerDissipationCapacitance

AVDD Power Supply Current

AVDD = 3.3V

⎯

NOTES:

1. For Industrial devices, operating free-air temperature = -40°C to +85°C.

2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions.

3. For IDD of AVDD, see TYPICAL CHARACTERISTICS.

TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND

OPERATINGFREE-AIRTEMPERATURE⁽¹⁾

Min.

Max.

175

60%

Unit

Clockfrequency

MHz

fCLOCK

Input clock duty cycle

Stabilizationtime⁽²⁾

40%

⎯

NOTES:

1. For Industrial devices, operating free-air temperature = -40°C to +85°C.

2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase

reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics

table are not applicable.

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

SWITCHINGCHARACTERISTICSOVEROPERATINGRANGEOFSUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF⁽¹⁾

VDD = 3.3V ± 0.3V

Parameter ⁽²⁾

From (Input)

To (Output)

FBIN↑

Min.

–150

–50

⎯

Typ.

⎯

Max.

150

Unit

tPHASE error

100MHz < CLK↑ < 166MHz

CLK↑ = 166MHz

Any Y (166MHz)

CLK = 166MHz

(3)

tPHASEerror–jitter

FBIN↑

tSK(o)⁽⁴⁾

Jitter(cycle-cycle)

(peak-to-peak)

Duty cycle reference ⁽⁵⁾

Any Y

150

Any Y or FBOUT

–75

CLK = 166MHz

Any Y or FBOUT

0.8

⎯

2.1

2.5

NOTES:

1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION.

2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

3. Phase error does not include jitter.

4. The tSK(O) specification is only valid for equal loading of all outputs.

5. See TYPICAL CHARACTERISTICS.

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

PARAMETERMEASUREMENTINFORMATION⁽¹⁾

From Output

Under Test

50% VDD

Input

500Ω

CL = 30pF⁽²⁾

tPHASE ERROR

VOH

50% VDD

0.4V

VOL

0.4V

Output

FBIN

Load Circuit and Voltage Waveforms

CLK

FBIN

tPHASE ERROR

CLK

500Ω

CL = 30pF⁽²⁾

on each

FBOUT

Y output

CSP2510D

FBOUT

FBIN

Any Y

tSK(o)

PCBTRACE

Any Y

tSK(o)

Phase ERROR and Skew Calculations ^(3,4)

NOTES:

1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF≤ 1.2 ns.

2. CL includes probe and jig capacitance.

3. The outputs are measured one at a time with one transition per measurement.

4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN ≅ 6pF.

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

TYPICALCHARACTERISTICS

Phase Error vs Clock Frequency

AV and V = 3.3V

Ta = 25C

200

150

100

133

166

175

-50

-100

-150

-200

Clock Frequency (MHz)

Analog Supply Current vs Clock Frequency

AV and V = 3.3V

Ta = 25C

100

133

166

175

Clock Frequency (MHz)

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

TYPICALCHARACTERISTICS(CONT.)

Output Duty Cycle vs Clock Frequency

AV and V = 3.3V

Ta = 25C

100

133

166

175

Clock Frequency (MHz)

Jitter vs Clock Frequency

AV and V = 3.3V

Ta = 25C

140

120

100

Peak-to-Peak

Cycle-to-Cycle

100

133

166

175

Clock Frequency (MHz)

IDTCSP2510D

3.3VPHASE-LOCKLOOPCLOCKDRIVER

0°CTO85°CTEMPERATURERANGE

ORDERINGINFORMATION

IDTCSP XXXXX

Device Type Package

Process

Blank

0°C to +85°C (Standard)

-40°C to +85°C (Industrial)

Thin Shrink Small Outline Package

Phase-Lock Loop Clock Driver

2510D

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

CSP2510DPGI8 [IDT]

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