CV133PAG8 [IDT]
Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56;
| 型号： | CV133PAG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Processor Specific Clock Generator, 400MHz, PDSO56, GREEN, TSSOP-56 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总26页 (文件大小：140K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
IDTCV133
DESCRIPTION:
FEATURES:
IDTCV133is a 56pinclockdevice, incorporatingbothIntelCK410Mand
CKSSCD requirements, for Intel advance P4 processors. The CPU output
bufferisdesignedtosupportupto400MHzprocessor. ThischiphasfourPLLs
insideforCPU,SRC/PCI,LVDS,and48MHz/DOT96IOclocks. Thisdevice
alsoimplementsBand-gapreferencedIREFtoreducetheimpactofVDDvariation
ondifferentialoutputs,whichcanprovidemorerobustsystemperformance.
EachCPU/SRC/LVDShasitsownSpreadSpectrumselection.
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less execution-
intensive
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 5*0.7V current –mode differential SRC CLK pair
• One CPU_ITP/SRC selectable CLK pair
• 6*PCI, 2 free running, 33.3MHz
• 1*96MHz,1*48MHz
• Smooth transition for N programming
• Available in TSSOP package
• 1*REF
• One 100/96 MHz differential LVDS
KEYSPECIFICATION:
• CPU CLK cycle to cycle jitter < 100ps
• SRC CLK cycle to cycle jitter < 125ps
• PCI CLK cycle to cycle jitter < 500ps
FUNCTIONALBLOCKDIAGRAM
PLL1
SSC
N Programmable
CPU[1:0]
CPU CLK
Output Buffer
Stop Logic
X1
CPU_ITP/SRC7
IREF
XTAL
Osc Amp
REF
X2
ITP_EN
LVDS CLK
Output Buffer
Stop Logic
PLL2
SSC
LVDS
SDATA
SCLK
SM Bus
Controller
IREF
SRC CLK
Output Buffer
Stop Logic
PLL3
SSC
N Programmable
SRC[5:1]
VTT_PWRGD#/PD
SEL100/96#
CLKREQA#
CLKREQB#
FSA.B.C
PCI[3:0], PCIF[1:0]
IREF
SEL
100/96MHz
48MHz
DOT96
Control
Logic
PLL4
48MHz/96MHz
Output BUffer
PCI_STOP#
CPU_STOP#
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
JANUARY 2005
1
© 2005 Integrated Device Technology, Inc.
DSC 6564/14
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
VDD_PCI
VSS_PCI
PCI1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI0
VDD
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
2
PCI_STOP#
CPU_STOP#
FSC/TEST_SEL
REF
TSTG
Storage Temperature
–65
0
+150
+70
+115
° C
° C
° C
V
3
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
PCI2
4
PCI3
5
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
VSS_PCI
VDD_PCI
PCIF0/ITP_EN
(1)PCIF1/SEL100/96#
VTT_PWRGD#/PD
VDD48
6
VSS_REF
XTAL_IN
XTAL_OUT
VDD_REF
SDA
7
8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SCL
USB48/FSA
VSS48
VSS_CPU
CPU0
DOT96
CPU0#
DOT96#
FSB/TEST_MODE
LVDS
VDD_CPU
CPU1
CPU1#
LVDS#
IREF
SRC1
VSSA
SRC1#
VDDA
VDD_SRC
SRC2
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
VDD_SRC
CLKREQA#(2)
CLKREQB#(2)
SRC2#
SRC3
SRC3#
SRC4
SRC5
SRC4#
SRC5#
VSS_SRC
VDD_SRC
NOTES:
1. 130K pull-up resistor.
2. 130K pull-down resistor.
TSSOP
TOP VIEW
FREQUENCYSELECTIONTABLE
FSC, B, A
101
CPU
100
SRC[7:0]
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
DOT
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
001
133
100
48
96
011
166
100
48
96
010
200
100
48
96
000
266
100
48
96
100
333
100
48
96
110
400
100
48
96
111
Reserve
100
48
96
2
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PINDESCRIPTION
Pin Number
Name
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/O
Description
1
2
VDD_PCI
3.3V
VSS_PCI
GND
3
PCI1
PCI clock
PCI clock
PCI clock
GND
4
PCI2
5
PCI3
6
VSS_PCI
7
VDD_PCI
3.3V
8
PCIF0/ITP_EN
PCIF1/SEL100/96#
VTT_PWRGD#/PD
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
PCIclock,freerunning.SEL100/96MHz(sampledonVTT_PWRGD#assertion)HIGH,LVDS =100MHz.
9
I/O
10
IN
Level-sensitivestrobeusedtolatchtheFSA,FSB,FSC/TEST_SEL,andPCIF0/ITP_ENinputs. After
VTT_PWRGD#assertion,becomesareal-timeinputforassertingpowerdown. (ActiveHIGH). LatchPCIF1/
SEL100/96#input.
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
VDD48
USB48/FSA
VSS48
PWR
I/O
3.3V
48MHz clock/FSA for CPU frequency selection
GND
OUT
OUT
IN
GND
DOT96
96MHz0.7currentmodedifferentialclockoutput
DOT96#
FSB/TEST_MODE
LVDS
96MHz0.7currentmodedifferentialclockoutput
CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
IN
Differentialserialreferenceclock
LVDS#
Differentialserialreferenceclock
SRC1
Differentialserialreferenceclock
SRC1#
Differentialserialreferenceclock
VDD_SRC
SRC2
3.3V
Differentialserialreferenceclock
SRC2#
Differentialserialreferenceclock
SRC3
Differentialserialreferenceclock
SRC3#
Differentialserialreferenceclock
SRC4
Differentialserialreferenceclock
SRC4#
Differentialserialreferenceclock
VDD_SRC
VSS_SRC
SRC5#
3.3V
GND
Differentialserialreferenceclock
SRC5
Differentialserialreferenceclock
CLKREQB#
CLKREQA#
VDD_SRC
CPU2_ITP#/SRC7#
CPU2_ITP/SRC7
VDDA
SRC clock enable (Active LOW, see Byte 21)
IN
SRC clock enable (Active LOW, see Byte 21)
PWR
OUT
OUT
PWR
GND
OUT
OUT
OUT
PWR
3.3V
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
3.3V
VSSA
GND
IREF
Referencecurrentfordifferentialoutputbuffer
Host0.7currentmodedifferentialclockoutput
Host0.7currentmodedifferentialclockoutput
3.3V
CPU1#
CPU1
VDD_CPU
3
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PINDESCRIPTION(CONT.)
Pin Number
Name
CPU0#
Type
OUT
OUT
GND
IN
Description
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Host0.7currentmodedifferentialclockoutput
CPU0
Host0.7currentmodedifferentialclockoutput
VSS_CPU
SCL
GND
SM bus clock
SDA
I/O
SM bus data
VDD_REF
XTAL_OUT
XTAL_IN
VSS_REF
REF
PWR
OUT
IN
3.3V
XTALoutput
XTALinput
GND
OUT
IN
GND
14.318MHzreferenceclockoutput
FSC/TEST_SEL
CPU_STOP#
PCI_STOP#
PCI0
CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW.
IN
Stop all stoppable CPU CLK
Stop all stoppable PCI, SRC CLK
PCI clock
IN
OUT
INDEXBLOCK WRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
D2h
2-9
Bit
1
# of bits
From
Master
Master
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
D2h
11-18
19
Master
Slave
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
Master
Slave
11-18
19
Master
Slave
29-36
37
Master
Slave
20
Master
Master
Slave
21-28
29
D3h
38-45
46
Master
Slave
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Slave
Byte count, N (block read back of N
bytes), power on is 8
38
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
39-46
47
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Settingbit[11:18]=startingaddress. Afterreadingbackthe firstdata byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
4
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
RESOLUTION
SSC MAGNITUDE CONTROL FOR CPU,
CPU (MHz)
100
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N =
150
200
125
150
200
125
150
SRC, AND SMC
SMC[2:0]
133
000
001
010
011
100
101
110
111
-0.25
-0.5
166
200
-0.75
-1
266
333
±0.125
±0.25
±0.375
±0.5
400
S.E.CLOCKSTRENGTHSELECTION
(PCI, REF, USB48)
SEL100/96#CONFIGURATION
SEL100/96#
LVDS Frequency
Unit
MHz
MHz
Str[1:0]
Level
0
1
96
00
1
100
01
0.8
0.6
1.2
10
11
SPREADSPECTRUMCONTROL
SELECTIONFORLVDS(SSC-2)
SPREADSPECTRUMCONTROL
SELECTIONFORLVDS(SSC-1)
S[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Spread
-0.8%
-1%
S[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Spread
-0.8%
-1%
-1.25%
-1.5%
-1.75%
-2%
-1.25%
-1.5%
-1.75%
-2%
-2.5%
-3%
-0.3%
-0.5%
±0.3%
±0.4%
±0.5%
±0.6%
±0.8%
±1%
±0.3%
±0.4%
±0.5%
±0.6%
±0.8%
±1%
±1.25%
±1.5%
±1.25%
±1.5%
5
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
CONTROLREGISTERS
N PROGRAMMING PROCEDURE
•
•
Use Index byte write.
For N programming, the user only needs to access Byte 12, Byte 13, and Byte 10.
1.
2.
3.
Write Byte 12 for CPU PLL N, CPU f = N* Resolution (see resolution table).
Write Byte 13 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.
Enable N Programming bit, Byte 10 bit 1. Once this bit is enabled, any N value will be changed on the fly.
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
LVDS, LVDS#
SRC1, SRC1#
SRC2, SRC2#
SRC3, SRC3#
SRC4, SRC4#
SRC5, SRC5#
Reserved
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
CPU2, CPU2#/
SRC7, SRC7#
OutputEnable
Tristate
Enable
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
CPU[2:0], SRC[7,5:1],
PCI[3:0], PCIF[1:0]
SpreadSpectrummodeenable
Spreadoff
Spreadon
RW
0
1
2
3
4
5
6
7
CPU0, CPU0#
CPU1, CPU1#
Reserved
REF
OutputEnable
OutputEnable
Tristate
Tristate
Enable
Enable
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
USB48
DOT96
PCIF0
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
PCIF1
Reserved
Reserved
Reserved
PCI0
OutputEnable
Tristate
Enable
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
OutputEnable
OutputEnable
OutputEnable
OutputEnable
Tristate
Tristate
Tristate
Tristate
Enable
Enable
Enable
Enable
PCI1
PCI2
PCI3
6
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
LVDS
SRC1
SRC2
SRC3
SRC4
SRC5
Reserved
SRC7
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Allowcontrolledby
Freerunning,not
Stoppedwith
PCI_STOP#
PCI_STOP# assertion
affected by PCI_STOP#
Allowcontrolledby
PCI_STOP# assertion
Freerunning,not
affected by PCI_STOP#
Stoppedwith
PCI_STOP#
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
CPU0, CPU0#
Allow control of CPU0
Notstopped
Stoppedwith
RW
1
with assertion of CPU_STOP#
by CPU_STOP#
CPU_STOP#
1
2
CPU1, CPU1#
CPU2, CPU2#
Allow control of CPU1
with assertion of CPU_STOP#
Notstopped
by CPU_STOP#
Stoppedwith
CPU_STOP#
RW
RW
1
1
Allow control of CPU2
Notstopped
Stoppedwith
with assertion of CPU_STOP#
by CPU_STOP#
CPU_STOP#
3
4
5
6
7
PCIF0
PCIF1
Allowcontrolledby
Notstopped
Stoppedwith
PCI_STOP#
RW
RW
RW
RW
RW
0
0
0
0
0
PCI_STOP# assertion
by PCI_STOP#
Reserved
DOT96
DOT96powerdowndrive mode
Driven in power down
Tristate
Reserved
BYTE 5
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU0, CPU0#
CPU1, CPU1#
CPU2, CPU2#
SRCS
CPU0 PD drive mode
CPU1 PD drive mode
Driven in power down
Driven in power down
Driven in power down
Driven in power down
Driven in CPU_STOP#
Driven in CPU_STOP#
Driven in CPU_STOP#
Driven in PCI_STOP
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristateinpowerdown
Tristatewhenstopped
Tristatewhenstopped
Tristatewhenstopped
Tristatewhenstopped
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
CPU2 PD drive mode
SRC PD drive mode
CPU0
CPU0 CPU_STOP drive mode
CPU1 CPU_STOP drive mode
CPU2 CPU_STOP drive mode
SRC PCI_STOP drive mode
CPU1
CPU2
SRCS
7
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE 6
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
CPU[2:0]
CPU[2:0]
CPU[2:0]
PCI, SRC
FSA latched value on power up
FSB latched value on power up
FSC latched value on power up
R
R
FSA
FSB
FSC
1
R
SoftwarePCI_STOPcontrolfor
PCI and SRC CLK
Stop all PCI, PCIF, and
SRC which can be stopped
by PCI_STOP#
SoftwareSTOP
Disabled
RW
4
5
6
REF
REFdrivestrength
1x drive
2x drive
RW
RW
RW
1
0
0
Reserved
Testclockmodeentrycontrol
Normaloperation
Hi-Z
Testmode,controlled
by Byte 6, Bit 7
7
CPU, SRC, PCI
PCIF, REF,
Only valid when Byte 6, Bit 7
is HIGH
REF/N
RW
0
USB48, DOT96
BYTE 7
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
VendorID
VendorID
VendorID
VendorID
Revision ID
Revision ID
Revision ID
Revision ID
R
R
R
R
R
R
R
R
1
0
1
0
0
0
0
0
BYTE 8, BLOCK READ BYTE COUNT
Bit
0
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
1
0
1
0
0
0
1
2
3
4
5
6
7
8
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTE 9, LVDS CONTROL BYTE
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
(1)
0
1
2
3
4
5
6
7
LVDS
HW/ SMBus control
HW
Off
SW
On
RW
RW
RW
RW
RW
RW
RW
RW
0
LVDS SSC EN
Spreadspectrumenable
1
Reserved
0
SEL100/96#
SelectLVDSfrequency
see SSC table
96MHz
100MHZ
SEL 100/96#
S3
S2
S1
S0
0
1
1
1
see SSC table
see SSC table
see SSC table
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
BYTE10
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
NProgrammingenable
LVDS PLL power down
Disable
Normal
Enable
Power Down
Reserved
Reserved
USB PLL power down
SRC PLL power down
CPU PLL power down
Normal
Normal
Normal
Power Down
Power Down
PowerDown
BYTE11
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC SMC0
SRC SMC1
SRC SMC2
Reserved
SRC/PCI SSC control
see SMC table
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
0
0
0
CPU SMC0
CPU SMC1
CPU SMC2
Reserved
CPU PLL SSC control
see SMC table
BYTE12
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
CPU_N0, LSB
CPU_N1
CPU CLK = N* Resolution
seeResolutiontable
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
CPU_N2
CPU_N3
CPU_N4
CPU_N5
CPU_N6
CPU_N7, MSB
9
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
BYTE13
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC_N0, LSB
SRC_N1
SRC f = N*SRC Resolution
Resolution=0.666667
100MHz N= 150
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
SRC_N2
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
BYTE14
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
48MHzStr0
48MHStr1
REFStr0
RW
RW
RW
RW
RW
RW
RW
RW
1
1
0
0
0
0
0
0
USB48MHz0strengthselection
REFstrengthselection
REFStr1
PCIStrC0
PCIStrC1
PCIFStr0
PCIFStr1
PCIstrengthselection
PCIFstrengthselection
BYTE15
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
PCI0
PCI1
RW
RW
RW
RW
1
1
1
1
0
0
0
0
Allowcontrolledby
Freerunning,not
Stoppedwith
PCI_STOP#
PCI2
PCI_STOP# assertion
affected by PCI_STOP#
PCI3
Reserved
Reserved
Reserved
Reserved
BYTES 16 - 20 ARE NOT TO BE USED
BYTE18
Bit
0
Output(s)Affected
Description / Function
keepthisbit0
0
1
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power On
0
0
0
0
0
0
0
0
1
keepthisbit0
2
keepthisbit0
3
keepthisbit0
4
keepthisbit0
5
keepthisbit0
6
LVDS
SSCDSpreadTableSelection
keepthisbit0
SSC-1
SSC-2
7
10
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
BYTES 19 - 20 ARE NOT TO BE USED
BYTE 21(1,2)
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
LVDS
SRC2
RW
RW
RW
RW
RW
RW
RW
RW
0
0
1
0
0
0
1
0
Controlled by CLKREQA#. When CLKREQA#
is HIGH, output is Hi-Z
NotControlled
Controlled
SRC4
Reserved
SRC1
SRC3
Controlled by CLKREQB#. When CLKREQB#
is HIGH, output is Hi-Z
NotControlled
Controlled
SRC5
Reserved
NOTES:
1. When SRCCLK outputs controlled by CLKREQA# and CLKREQB# are enabled, clock output behavior will follow SMBus control bits (per CK410 spec).
2. Assertion/de-assertion time of CLKREQ# pins will match PCI_STOP# timing of the CK410 spec. This is 15ns from the assertion/de-assertion of CLKREQ# to the drive/tie-state
of the respective SRCCLK output.
11
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
VIH
Parameter
Input HIGH Voltage
Test Conditions
Min.
2
Typ.
—
Max.
Unit
V
3.3V ± 5%
3.3V ± 5%
VDD + 0.3
VIL
Input LOW Voltage
VSS - 0.3
0.7
VSS - 0.3
–5
—
0.8
V
VIH_FS
VIL_FS
IIH
LOW Voltage, HIGH Threshold
LOW Voltage, LOW Threshold
Input HIGH Current
For FSA.B.C test_mode
For FSA.B.C test_mode
VIN = VDD
—
VDD + 0.3
V
—
0.35
5
V
—
µ A
µ A
µ A
mA
mA
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
Full active, CL = full load
All differential pairs driven
All differential pairs tri-stated
VDD = 3.3V
–5
—
—
—
400
70
12
—
7
IIL2
Input LOW Current
–200
—
—
IDD3.3OP
IDD3.3PD
Operating Supply Current
Powerdown Current
—
—
—
—
—
(1)
FI
Input Frequency
—
14.31818
—
MHz
nH
LPIN
Pin Inductance(2)
—
CIN
Logic inputs
—
—
5
COUT
CINX
COUTX
TSTAB
Input Capacitance(2)
Output pin capacitance
—
—
6
pF
XTAL_IN
—
—
5
XTAL_OUT
—
—
12
1.8
33
15
300
5
Clock Stabilization(2,3)
From VDD power-up or de-assertion of PD to first clock
Triangular modulation
—
—
ms
KHz
ns
(2)
Modulation Frequency
30
—
TDRIVE_SRC(2)
SRC output enable after PCI_STOP# de-assertion
CPU output enable after PD de-assertion
Fall time of PD
—
—
(2)
TDRIVE_PD
—
—
us
(2)
TFALL_PD
—
—
ns
(3)
TRISE_PD
Rise time of PD
—
—
5
ns
TDRIVE_CPU_STOP#(2)
TFALL_CPU_STOP#(2)
TRISE_CPU_STOP#(3)
CPU output enable after CPU_STOP# de-assertion
Fall time of CPU_STOP#
Rise time of CPU_STOP#
—
—
10
5
us
—
—
ns
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
12
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
ZO
Parameter
Test Conditions
Min.
3000
2.4
Typ.
—
—
—
—
—
—
—
—
—
Max.
—
Unit
Ω
Current Source Output Impedance(2) VO = VX
VOH3
VOL3
Output HIGH Voltage
Output LOW Voltage
IOH = -1mA
IOL = 1mA
—
V
—
0.4
V
(2)
VHIGH
VLOW
VOVS
Voltage HIGH
Statistical measurement on single-ended signal using
oscilloscope math function
660
–150
—
900
150
1150
—
mV
(2)
Voltage LOW
Max Voltage(2)
Min Voltage(2)
Measurement on single-ended signal using absolute value
mV
VUDS
–300
250
—
VCROSS(ABS) Crossing Voltage (abs)(2)
550
140
mV
mV
ppm
d - VCROSS
ppm
Crossing Voltage (var)(2)
Static Error(2,3)
Variation of crossing over all edges
See TPERIOD Min. - Max. values
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
—
—
—
0
2.4993
2.9991
3.7489
2.5133
3.016
3.77
TPERIOD
Average Period(3)
200MHz nominal / -0.5% spread
4.9985
—
5.0266
ns
166.66MHz nominal / -0.5% spread
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
5.9982
7.4978
9.997
—
—
—
6.032
7.54
10.0533
96MHz nominal
10.4135
2.4143
2.9141
3.6639
—
—
—
—
10.4198
—
400MHz nominal / -0.5% spread
333.33MHz nominal / -0.5% spread
266.66MHz nominal / -0.5% spread
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
TABSMIN
Absolute Min Period(2,3)
ns
133.33MHz nominal / -0.5% spread
100MHz nominal / -0.5% spread
96MHz nominal
7.4128
9.912
10.1635
175
—
—
—
—
—
—
—
—
—
tR
tF
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
VOL = 0.175V, VOH = 0.525V
700
700
125
ps
ps
ps
Fall Time(2)
175
d-tR
Rise Time Variation(2)
—
d-tF
dT3
Fall Time Variation(2)
Duty Cycle(2)
—
45
—
—
125
55
ps
%
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
13
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIALPAIR,CONTINUED(1)
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
Max.
100
Unit
(2)
Skew, CPU[1:0]
tSK3
Skew, CPU2(2)
VT = 50%
—
—
250
ps
Skew, SRC(2)
—
—
—
—
—
—
250
85
(2)
Jitter, Cycle to Cycle, CPU[1:0]
Jitter, Cycle to Cycle, CPU2(2)
tJCYC-CYC
Measurement from differential waveform
100
ps
Jitter, Cycle to Cycle, SRC(2)
Jitter, Cycle to Cycle, DOT96(2)
—
—
—
—
125
250
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
33.33MHzoutputnominal
33.33MHzoutputspread
IOH = -1mA
Min.
—
Typ.
Max.
Unit
ppm
ns
ppm
StaticError(1,2)
ClockPeriod(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
30.009
30.1598
—
TPERIOD
29.991
29.991
2.4
—
VOH
VOL
IOH
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
V
IOL = 1mA
0.55
—
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
IOL
OutputLOWCurrent
30
—
mA
—
38
EdgeRate(1)
EdgeRate(1)
RiseTime(1)
FallTime(1)
1
4
V/ns
V/ns
ns
Fallingedgerate
1
4
tR1
tF1
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
ns
dT1
Duty Cycle(1)
55
%
(1)
tSK1
Skew
VT = 1.5V
—
500
500
ps
tJCYC-CYC
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
14
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
ELECTRICALCHARACTERISTICS,48MHZ,USB
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1,2)
ppm
StaticError
See Tperiod Min. - Max. values
48MHzoutputnominal
IOH = -1mA
TPERIOD
VOH
ClockPeriod(2)
20.8257
2.4
—
20.834
—
OutputHIGHVoltage
OutputLOWVoltage
Output HIGH Current
V
VOL
IOL = 1mA
0.55
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-29
—
mA
-23
—
IOL
OutputLOWCurrent
29
mA
—
27
EdgeRate(1)
1
2
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
2
tR1
tF1
RiseTime(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.5
0.5
45
1.2
1.2
55
FallTime(1)
ns
dT1
Duty Cycle(1)
%
tJCYC-CYC
Jitter, Cycle to Cycle
—
350
ps
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICALCHARACTERISTICS-REF-14.318MHZ
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
See Tperiod Min. - Max. values
14.318MHzoutputnominal
IOH = -1mA
Min.
—
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
0
Unit
ppm
ns
(1)
ppm
LongAccuracy
TPERIOD
VOH
Clock Period
69.827
2.4
—
69.855
—
OutputHIGHVoltage(1)
OutputLOWVoltage(1)
Output HIGH Current
V
VOL
IOL = 1mA
0.4
—
V
IOH
VOH at Min. = 1V
VOH at Max. = 3.135V
VOL at Min. = 1.95V
VOL at Max. = 0.4V
Risingedgerate
-33
—
mA
-33
—
IOL
OutputLOWCurrent
30
mA
—
38
EdgeRate(1)
1
4
V/ns
V/ns
ns
EdgeRate(1)
Fallingedgerate
1
4
tR1
tF1
Rise Time(1)
VOL = 0.8V, VOH = 2V
VOL = 0.8V, VOH = 2V
VT = 1.5V
0.3
0.3
45
1.2
1.2
55
Fall Time(1)
ns
dT1
Duty Cycle(1)
Jitter, Cycle to Cycle(1)
%
tJCYC-CYC
VT = 1.5V
—
1000
ps
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
15
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PCISTOPFUNCTIONALITY
ThePCI_STOP#signalisonanactivelowinputcontrollingPCIandSRCoutputs.IfPCIF[1:0]andSRCclockscanbesettobefree-runningthroughSMBus
programming, theywillignore boththe PCI_STOP#pinandthe PCI_STOPregisterbit.
PCI_STOP#
CPU
CPU#
Normal
Normal
SRC
Normal
SRC#
Normal
Low
PCIF/PCI
33MHz
Low
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
TheclocksamplesthePCI_STOP#signalonarisingedgeofPCIFclock.AfterdetectingthePCI_STOP#assertionlow,allPCI[6:0]andstoppablePCIF[1:0]
clocks willlatchlowontheirnexthightolowtransition. Afterthe PCIclocks are latchedlow, the SRCclock, (ifsettostoppable)willlatchhighatIREF *6(or
tristate if Byte 5 Bit 7 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
tSU
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP#-DE-ASSERTION
Thede-assertionofthePCI_STOP#signalistobesampledontherisingedgeofthePCIFfreerunningclockdomain.AfterdetectingPCI_STOP#de-assertion,
allPCI[6:0], stoppable PCIF[1:0]andstoppable SRCclocks willresume ina glitchfree manner.
tSU
tDRIVE_SRC
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
16
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
CPUSTOPFUNCTIONALITY
The CPU_STOP#signalis anactive lowinputcontrollingthe CPUoutputs. This signalcanbe assertedasynchronously.
CPU_STOP#
CPU
Normal
CPU#
Normal
Low
SRC
SRC#
Normal
Normal
PCIF/PCI
33MHz
USB
DOT96
Normal
Normal
DOT96#
Normal
Normal
REF
1
0
Normal
Normal
48MHz
48MHz
14.318MHz
14.318MHz
IREF * 6 or float
33MHz
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
AssertingCPU_STOP#pinstopsallCPUoutputsthataresettobestoppableaftertheirnexttransition.WhentheSMBusCPU_STOPtri-statebitcorresponding
totheCPUoutputofinterestisprogrammedtoa‘0’,CPUoutputwillstopCPU_True=HighandCPU_Complement=Low.WhentheSMBusCPU_STOP#
tri-statebitcorrespondingtotheCPUoutputofinterestisprogrammedtoa‘1’,CPUoutputswillbetri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
Withthede-assertionofCPU_STOP#allstoppedCPUoutputswillresumewithoutaglitch.Themaximumlatencyfromthede-assertiontoactiveoutputs
istwotosixCPUclockperiods.Ifthecontrolregistertristatebitcorrespondingtotheoutputofinterestisprogrammedto‘1’,thenthestoppedCPUoutputswill
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
17
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PD, POWER DOWN
PDisanasynchronousactivehighinputusedtoshutoffallclockscleanlypriortoclockpower. WhenPDisassertedhighallclockswillbedrivenlowbefore
turningofftheVCO.InPDde-assertionallclockswillstartwithoutglitches.
PD
0
CPU
Normal
CPU#
Normal
Float
SRC
Normal
SRC#
Normal
Float
PCIF/PCI
33MHz
Low
USB
48MHz
Low
DOT96
Normal
DOT96#
Normal
Float
REF
14.318MHz
Low
1
IREF * 2 or float
IREF * 2 or float
IREF * 2 or float
PDASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
18
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PDDE-ASSERTION
tSTABLE <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN
<300μS, <200mV
19
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
DIFFERENTIALCLOCKTRISTATE
Tominimizepowerconsumption,CPU[2:0]clockoutputsareindividuallyconfigurablethroughSMBustobedrivenortristatedduringPDandCPU_STOP#
modeandtheSRCclockis configurabletobedrivenortristatedduringPCI_STOP#andPD mode.Eachdifferentialclock(SRC,CPU[2:0])outputcanbe
disabledbysettingthecorrespondingoutput’sregisterOEbitto“0”(disable).Disabledoutputsaretobetristatedregardlessof“CPU_STOP”,“SRC_STOP”
and“PD”registerbitsettings.
Signal
CPU
CPU
CPU
CPU
CPU
Pin PD
Pin CPU_STOP#
CPU_STOPTristate Bit
PD Tristate Bit
Non-StoppableOutputs Stoppable Outputs
0
0
0
1
1
1
X
0
X
X
X
0
Running
Running
Running
Driven at IREF x 6
Tristate
0
0
1
Running
X
X
X
X
Driven at IREF x 2
Tristate
Driven at IREF x 2
Tristate
1
NOTES:
1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
Signal
SRC
SRC
SRC
SRC
SRC
Pin PD
Pin PCI_STOP#
PCI_STOPTristate Bit
PD Tristate Bit
Non-StoppableOutputs Stoppable Outputs
0
0
0
1
1
1
X
0
X
X
X
0
Running
Running
Running
Driven at IREF x 6
Tristate
0
0
1
Running
X
X
X
X
Driven at IREF x 2
Tristate
Driven at IREF x 2
Tristate
1
NOTES:
1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
TRISTATEDOT96CLOCKCONTROL
Signal
DOT96
DOT96
DOT96
Pin PD
PD Tristate Bit
Output
1
0
0
X
0
Running
Driven at IREF x 2
Tristate
1
NOTES:
1. DOT output has two corresponding control register bits; OE and PD.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
20
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
LVDSACTIMINGREQUIREMENTS
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = 0°C to +70°C
Symbol
tR1
Parameter
Clock Rise Time(1,2,3)
Min.
175
175
—
Typ.
—
Max.
700
700
125
125
20
Unit
ps
tF1
Clock Fall Time(1,2,3)
—
ps
Δ tR
Δ tF
Clock Rise Time Variation(2,3,4)
Clock Fall Time Variation(2,3,4)
Rise/Fall Matching(2,3,5)
—
ps
—
—
ps
—
—
%
(2,3,6)
VHIGH
Voltage HIGH
660
700
850
mV
VLOW
Voltage LOW (2,3,7)
Crossing Voltage (abs)(2,3,8,9,10)
-150
250
0
—
mV
mV
VCROSS(ABS)
—
550
VCROSS(REL)
TOTAL Δ VCROSS
tJCYC-CYC
dT3
Crossing Voltage (rel)(2,3,10,11)
Calc.
—
—
—
—
—
—
Calc.
Total Variation of VCROSS Over All Edges(2,3,12)
Cycle-to-Cycle Jitter(2,13)
140
350
mV
ps
—
Duty Cycle(2,13)
45
55
%
VOVS
Maximum Voltage Allowed at Output (overshoot)(2,3,14)
—
VHIGH + 0.3V
V
VUDS
Minimum Voltage Allowed at Output (undershoot)(2,3,15)
Ringback Margin(2,3)
-0.3
n/a
—
—
—
V
V
VRB
0.2
NOTES:
1. Measured from VOL = 1.75V to VOH =0.525V. Only valid for Rising LVDS and Falling LVDS#. Signal must be monotonic through the VOL to VOH region for tRISE and tFALL.
2. Test configuration is Rs = 32.2Ω, Rp = 49.9Ω, 2pF.
3. Measurement taken from single-ended waveform.
4. Measured with oscilloscope, averaging off, using Min. Max. statistics. Variation is the delta between Min. and Max.
5. Measured with oscilloscope, averaging off, the difference between the tRISE (average) of LVDS versus the tFALL (average) of LVDS#.
6. VHIGH is defined as the statistical average HIGH value as obtained by using the oscilloscope VHIGH math function.
7. VLOW is defined as the statistical average LOW value as obtained by using the oscilloscope VLOW math function.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of LVDS equals the falling edge of LVDS#.
9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
10. The crossing point must meet the absolute and relative crossing point specifications simultaniously.
11. VCROSS (rel) Min. and Max. are derived using the following: VCROSS (rel) Min. = 0.25V + 0.5 (VHAVG - 0.7V), VCROSS (rel) Max. = 0.55V + 0.5 (0.7V - VHAVG).
12. Δ VCROSS is defined as the total variation of all crossing voltages of Rising LVDS and Falling LVDS#. This is the maximum allowed variance in VCROSS for any particular system.
13. Measurement is taken from differential waveform.
14. Overshoot is defined as the absolute value of the maximum voltage.
15. Undershoot is defined as the absolute value of the minimum voltage.
21
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
LVDS AVERAGE PERIOD, TPERIOD(1,2,3,4)
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = 0°C to +70°C
96MHz
100MHz
Spread
Min.
Max.
Min.
9.99
9.99
9.99
9.99
9.99
9.99
9.99
9.99
9.99
9.96
9.95
9.94
9.93
9.91
9.89
9.865
9.84
Max.
10.01
10.09
10.11
10.135
10.16
10.185
10.21
10.26
10.31
10.04
10.05
10.06
10.07
10.09
10.11
10.135
10.16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0% (no spread)
10.406
10.406
10.406
10.406
10.406
10.406
10.406
10.406
10.406
10.375
10.365
10.354
10.344
10.323
10.302
10.276
10.25
10.427
10.511
10.531
10.557
10.583
10.61
0.8%down-spread
1% down-spread
1.25%down-spread
1.5%down-spread
1.75%down-spread
2% down-spread
10.636
10.688
10.74
2.5%down-spread
3% down-spread
±0.3% down-spread
±0.4% down-spread
±0.5% down-spread
±0.6% down-spread
±0.8% down-spread
±1% down-spread
±1.25%down-spread
±1.5% down-spread
10.458
10.469
10.479
10.49
10.511
10.531
10.557
10.583
NOTES:
1. Test configuration is Rs = 32.2Ω, Rp = 49.9Ω, 2pF.
2. The average period over any 1μS period of time must be greater than the minimum and less than the maximum specified period.
3. Measurement is taken from differential waveform.
4. Calculated using a 0.1% accuracy in spread modulation. Assumes 300ppm long term accuracy on CLKIN.
tRISE (LVDS)
VOH = 0.525V
LVDS
LVDS#
VCROSS
VOL = 0.175V
tFALL (LVDS#)
Single-Ended Measurement Point for tRISE and tFALL
22
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
MISCELLANEOUSACTIMINGREQUIREMENTS
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = 0°C to +70°C
Symbol
tPZL
Parameter
Min.
Typ.
Max.
Unit
(1)
OutputEnableDelay(AllOutputs)
0
—
10
μs
tPZH
tPLZ
OutputDisableDelay(AllOutputs)(1)
0
—
10
μs
tPHZ
tSTABLE
tSPREAD
AllClockStabilizationfromPower-Up(2)
—
—
—
—
3
3
ms
ms
Setting Period for Spread Selection Change(2,3)
NOTES:
1. These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless
it is disabled.
2. The time specified is from when VDD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating
within specification.
3. The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency.
If there is another change in spread selection or output frequency during the tSPREAD settling period, then the settling period start resets to the most recent change in spread selection
and output frequency.
23
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
PWRDWN(POWERDOWN)CLARIFICATION
PWRDWN
CLOCK VCO
LVDS
On
Off
tPHZ
LVDS#
PWRDWN Assertion
VDD
PWRDWN
CLOCK VCO
LVDS
Off
Starting
Stable
tSTABLE
tPZH
LVDS#
PWRDWN De-Assertion
24
IDTCV133
COMMERCIALTEMPERATURERANGE
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
LVDSSYSTEMIMPLEMENTATION
Clock
Rs
Rp
Unit
LVDS Clock
33.2
5%
49.9
1%
Ω
33Ω
5%
Clock
LVDS
CV133
TLA
TLB
33Ω
5%
Clock#
LVDS#
49.9Ω
1%
49.9Ω
1%
475Ω
1%
2pF
5%
2pF
5%
Test Load Board Configuration
25
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
Thin Small Shrink Outline Package
TSSOP - Green
PA
PAG
Programmable FlexPC Clock for P4 Processor
133
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
logichelp@idt.com
26
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