CV143PYG [IDT]
PLL Based Clock Driver, 143 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN, SSOP-28;
| 型号： | CV143PYG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 143 Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, GREEN, SSOP-28 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1-TO-4 DIFFERENTIAL
CLOCK BUFFER
IDTCV143
DESCRIPTION:
FEATURES:
TheCV143differentialbufferiscompliantwithIntelDB400specifications. It
isintendedtodistributetheSRC(serialreferenceclock)asacompanionchip
tothemainclockoftheCK409, CK410/CK410M, CK410B, etc. PLLisoffin
bypassmodeandhasnoclockdetect.
• Compliant with Intel DB400 spec
• Four differential clock pairs at 0.7V
• 50ps skew
• 50ps cycle-to-cycle jitter
• Programmable Bandwidth
• PLL bypass configurable
• Available in SSOP package
FUNCTIONALBLOCKDIAGRAM
OE_INV
(1)OE_1, OE_6
(1)SRC_STOP
(1)PWRDWN
Output
Control
DIF_1
DIF_1#
DIF_2
SCL
SDA
SM Bus
Controller
DIF_2#
Output
Buffer
DIF_5
DIF_5#
PLL/BYPASS#
SRC_IN
DIF_6
SRC_IN#
DIF_6#
DIV
HIGH_BW#
PLL
NOTE:
1. See OE_INV table for active HIGH or active LOW.
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
MARCH 18, 2008
1
© 2005 Integrated Device Technology, Inc.
DSC-6739/18
IDTCV143
1-TO-4DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VDDA
Description
Min
Max
4.6
Unit
V
3.3V Core Supply Voltage
1
VDD
SRC_IN
SRC_IN#
VDDA
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
4.6
V
VSSA
2
TSTG
Storage Temperature
–65
0
+150
+70
+115
°C
°C
°C
V
IREF
3
TAMBIENT
TCASE
Ambient Operating Temperature
Case Temperature
OE_INV
4
VSS
VDD
5
VDD
ESD Prot Input ESD Protection
Human Body Model
NOTE:
2000
6
DIF_1
DIF_1#
(1)OE_1
DIF_2
DIF_6
7
DIF_6#
OE_6 (1)
DIF_5
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
9
10
11
12
13
14
DIF_5#
VDD
DIF_2#
VDD
PLL/BPASS#
SCL
HIGH_BW#
SRC_STOP(1)
(1)
SDA
PWRDWN
HIGH_BW#SELECTION
HIGH_BW# = 0
HIGH_BW#=1
Min. Typ. Max. Unit
NOTE:
Min. Typ. Max.
1. See OE_INV table for active HIGH or active LOW.
PLL BW
2
3
1
4
3
0.7
1
1
1.4
3
MHz
dB
PLLPeaking
—
—
SSOP
TOP VIEW
OE_INV
OE_INV = 0
OE_INV = 1
Active LOW
Active HIGH
Active HIGH
OE_1, OE_6
Active HIGH
Active LOW
Active LOW
PWRDWN
SRC_STOP
OE FUNCTIONALITY [OE_INV = 0]
OE_1, OE_6 Pin
OE_1, OE_6 SMBus bit
DIF_1, DIF_6
Normal
DIF_1#,DIF_6#
Normal
1
1
0
0
1
0
1
0
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
OE FUNCTIONALITY [OE_INV = 1]
OE_1, OE_6 Pin
OE_1, OE_6 SMBus bit
DIF_1, DIF_6
Tristate
DIF_1#,DIF_6#
Tristate
1
1
0
0
1
0
1
0
Tristate
Tristate
Normal
Normal
Tristate
Tristate
2
IDTCV143
COMMERCIALTEMPERATURERANGE
1-TO-4DIFFERENTIALCLOCKBUFFER
PINDESCRIPTION
Pin Name
Type
Pin #
Description
SRC_IN, SRC_IN#
IN, DIF
2,3
0.7VdifferentialSRCinput
DIF_[2:1], DIF_ [2:1]#
DIF_[6:5], DIF_ [6:5]#
OE_1, OE_6(1)
OUT, DIF
OUT, DIF
IN
6, 7, 9, 10
19, 20, 22, 23
8, 21
0.7Vdifferentialclockoutput
0.7Vdifferentialclockoutput
3.3VLVTTLinputforenablingdifferentialoutputs
1 = PLL mode, 0 = bypass, PLL OFF
PLL/Bypass#
IN
12
SCL
SDA
IN
13
14
15
16
17
25
26
SMBus clock
I/O, Open Collector
SMBus data
PWRDWN
SRC_STOP
HIGH_BW#
OE_INV
IREF
IN
IN
IN
IN
IN
3.3V LVTTL power down (see OE_INV table)
SRC stop (see OE_INV table)
0 = HIGH BW, 1 = LOW BW (see HIGH_BW# Selection table)
See OE_INV table
Referencecurrentfordifferentialoutput
NOTE:
1. OE_1 controls DIF_1/DIF_1#, and OE_6 controls DIF_6/DIF_6#.
SMPROTOCOL
INDEXBLOCK WRITEPROTOCOL
INDEXBLOCKREADPROTOCOL
Mastercanstopreadinganytimebyissuingthestopbitwithoutwaiting
untilNthbyte(bytecountbit30-37).
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Description
1
8
1
8
1
8
1
8
1
8
1
Start
DCh
2-9
Bit
1
# of bits
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Description
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
1
8
1
8
1
1
8
1
8
Start
DCh
11-18
19
2-9
10
Ack (Acknowledge)
Registeroffsetbyte(startingbyte)
Ack (Acknowledge)
RepeatedStart
20-27
28
11-18
19
29-36
37
20
21-28
29
DDh
38-45
46
Ack (Acknowledge)
Ack (Acknowledge)
:
30-37
Byte count, N (block read back of N
bytes)
38
39-46
47
1
8
1
8
Master
Slave
Master
Slave
Ack (Acknowledge)
firstdatabyte(Offsetdatabyte)
Ack (Acknowledge)
2nddatabyte
Master
Slave
Nthdatabyte
Acknowledge
Master
Stop
48-55
Ack (Acknowledge)
:
Master
Slave
Ack (Acknowledge)
Nthdatabyte
Notacknowledge
Stop
Master
INDEX BYTE READ
INDEX BYTE WRITE
Setting bit[11:18] = starting address. After reading back the first data byte,
masterissuesStopbit.
Settingbit[11:18]=startingaddress,bit[20:27]=01h.
3
IDTCV143
1-TO-4DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
CONTROLREGISTERS
BYTE 0
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
PowerDown dirve mode
SRC_STOP# drive mode
Reserved
Driven
Driven
Tri-state
Tri-state
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
1
1
1
Reserved
Reserved
High_BW#
Logically AND with HW pin
Logically AND with HW pin
High band width
Bypass
Low band width
PLL mode
PLL/Bypass#
Reserved
BYTE 1
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
DIFF_6
RW
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
1
OutputEnable
OutputEnable
Tristate
Tristate
Enable
Enable
DIFF_5
Reserved
Reserved
DIFF_2
OutputEnable
OutputEnable
Tristate
Tristate
Enable
Enable
DIFF_1
Reserved
BYTE 2
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
DIFF_6
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free
Free
stopped
stopped
DIFF_5
Reserved
Reserved
DIFF_2
Free Running with SRC_STOP#
Free Running with SRC_STOP#
Free
Free
stopped
stopped
DIFF_1
Reserved
BYTE 3
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
4
IDTCV143
COMMERCIALTEMPERATURERANGE
1-TO-4DIFFERENTIALCLOCKBUFFER
BYTE 4
Bit
Output(s)Affected
Description / Function
0
1
Type
Power On
7
6
5
4
3
2
1
0
Revision ID
Revision ID
Revision ID
Revision ID
VendorID
VendorID
VendorID
VendorID
R
R
R
R
R
R
R
R
0
0
0
0
0
1
0
1
BYTE 62 = 30h
BYTE 63 = 14h
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage
3.3V ± 5%
2
—
VDD + 0.3
V
VIL
IIH
Input LOW Voltage
Input HIGH Current
3.3V ± 5%
VIN = VDD
VSS - 0.3
–5
—
—
0.8
5
V
µA
IIL1
IIL2
Input LOW Current
Input LOW Current
Pin Inductance(2)
VIN = 0V, inputs with no pull-up resistors
VIN = 0V, inputs with pull-up resistors
–5
–200
—
—
—
—
—
—
7
µA
µA
nH
pF
LPIN
CIN
Input Capacitance(2)
Logic inputs
—
—
—
—
5
6
COUT
Output pin capacitance
5
IDTCV143
1-TO-4DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
ELECTRICALCHARACTERISTICS-DIF0.7CURRENTMODEDIFFERENTIALPAIR
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
VHigh
VLow
Vovs
Voltage High
Voltage Low
Max Voltage
Statistical measurement on single ended
signal using oscilloscope math function.
Measurement on single ended signal using
absolute value.
660
-150
850
mV
150
1150
mV
Vuds
Min Voltage
-300
250
Vcross(abs)
d-Vcross
ppm
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Rise Time
550
140
0
mV
mV
ppm
ps
Variation of crossing over all edges
see Tperiod min-max values
VOL = 0.175V, VOH = 0.525V
tr
175
175
700
tf
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
VOH = 0.525V VOL = 0.175V
700
125
125
55
ps
ps
ps
%
d-tr
d-tf
dt3
tsk3
Measurement from differential wavefrom
45
50
Skew
VT = 50%
PLL mode
BYPASS mode as additive jitter
50
50
50
ps
ps
ps
40
15
tjcyc-cyc
Jitter, Cycle to cycle
NOTES:
1. Parameter is guaranteed by design, but not 100% production tested.
SRC_IN 0.7V AC TIMING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
600
MAX
UNITS
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Measured differentially
VIHDIF
Differential Input High Voltage
1150
300
mV
mV
VILDIF
Differential Input Low Voltage
VSS - 300
dv/dt
IIN
Input Slew Rate - DIF_IN(2)
Input Leakage Current
0.4
-5
8
5
V/ns
uA
VIN = VDD , VIN =GND
dtin
Input Duty Cycle
Input SRC Jitter - Cycle to
Cycle
Measurement from differential wavefrom
45
55
%
SRCJC2CIn
Differential Measurement
125
ps
NOTES:
1. Parameter is guaranteed by design, but not 100% production tested.
2. Slew rate measured through Vswing centered around differential zero.
6
IDTCV143
COMMERCIALTEMPERATURERANGE
1-TO-4DIFFERENTIALCLOCKBUFFER
DIF AC TIMING CHARACTERISTICS
PLLBandwidthandPeaking
Symbol
TPROP,PLL
Parameter
Min
-250
2.5
—
Typ
—
—
—
3
Max
250
4.5
250
4
Units
ps
SRC_IN to DIF Propagation Delay, PLL Mode(1)
SRC_IN to DIF Propagation Delay, Bypass Mode(1)
DIF_[7:0] Pin to Pin Skew(1)
HIGH_BW#=0 (high bandwidth)(1)
HIGH_BW#=1 (low bandwidth)(1)
PLLPeaking(1,2)
Cycle to Cycle Jitter(1)
PLL Mode(1)
Bypass (assume input is 50%)(1)
TPROP,BYPASS
TSKEW
ns
ps
PLLbandwidth
PLLbandwidth
PLLPeaking
TCCJITTER
2
MHz
MHz
dB
0.7
—
1
1.4
3
1
—
—
—
—
50
pS
Duty cycle
Duty cycle
45
55
%
40
60
%
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. Measured at 3dB downpoint.
OUTPUTCONTROL
Symbol
Parameter
Min
—
—
2
Typ
—
Max
300
1
Units
TDRIVE_PWRDWN
TACTIVE_PWRDWN
TACTIVE_OE
CLK driven from PD De_Assertion
CLKTogglingfromPDDe_Assertion
CLKtogglingfromOE_[7:0]Assertion
CLKTri-statedfromOE_[7:0]De_Assertion
µs
ms
—
—
6
Clock Periods
Clock Periods
TINACTIVE_OE
2
—
6
PWRDWN (OE_INV = 0)
ThePWRDWN signalisade-bouncedsignalinthatitsstatemustremainunchanged
during two consecutive rising edges of DIF# to be recognized as a valid assertion or
de-assertion.
SRC_STOP (OE_INV = 0)
TheSRC_STOPsignalisade-bouncedsignalinthatitsstatemustremainunchanged
duringtwoconsecutiverisingedgesofDIF#toberecognizedasavalidassertionorde-
assertion.
PWRDWN
DIF
DIF#
Normal
Float
SRC_STOP
DIF
DIF#
Normal
Float
1
0
Normal
1
0
Normal
Iref*2orFloat
Iref*6orFloat
PWRDWN (OE_INV = 1)
SRC_STOP (OE_INV = 1)
PWRDWN
DIF
DIF#
Float
SRC_STOP
DIF
DIF#
Float
1
0
Iref*2orFloat
Normal
1
0
Iref*6orFloat
Normal
Normal
Normal
7
IDTCV143
1-TO-4DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
SRCSTOPFUNCTIONALITY
The SRC_STOP signal is an input controlling DIF[1, 2, 5, 6] and DIF[1, 2, 5, 6] # outputs. This signal can be asserted asynchronously.
SRC_STOP = DRIVEN, PWRDWN = DRIVEN
1mS
(1) SRC_Stop
(1) PWRDWN
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP = TRISTATE, PWRDWN = DRIVEN
1mS
(1) SRC_Stop
(1) PWRDWN
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
NOTE:
1. The polarity depends on OE_INV.
8
IDTCV143
COMMERCIALTEMPERATURERANGE
1-TO-4DIFFERENTIALCLOCKBUFFER
SRC_STOP = DRIVEN, PWRDWN = TRISTATE
1mS
(1) SRC_Stop
(1) PWRDWN
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
SRC_STOP = TRISTATE, PWRDWN = TRISTATE
1mS
(1) SRC_Stop
(1) PWRDWN
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
NOTE:
1. The polarity depends on OE_INV.
9
IDTCV143
1-TO-4DIFFERENTIALCLOCKBUFFER
COMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDTCV
XXX
XX
X
Device Type
Package
Grade
Commercial Temperature Range
Blank
(0°C to +70°C)
PY
PYG
Small Shrink Outline Package
SSOP - Green
1-to-4 Differential Clock Buffer
143
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for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
pcclockhekp@idt.com
www.idt.com
10
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